The wiki is being retired!
Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!
These instructions may easily become out of date as coreboot or RISC-V moves forward. If that happens, please complain on the discussion page or IRC (or just fix it).
Building the toolchain
- clone the coreboot git repository
- download and apply this patch and this patch.
make crossgcc-riscvand a have a cup of $BEVERAGE
- download Spike from https://github.com/riscv/riscv-isa-sim
- download and apply this patch that implements an 8250 UART
- TODO: fesvr: patch device_list_t::handle_command to ignore HTIF writes
- TODO: running make
Building coreboot without a payload
- TODO: patch patch patch
make menuconfigand select Emulation/SPIKE ucb riscv from the Mainboard menu
util/riscvtools/make-spike-elf.sh build/coreboot.rom build/coreboot.elfto create an ELF file (spike can only load ELF files)
For general spike usage, look at its GitHub page.
git clone https://github.com/riscv/riscv-linux
- download linux 4.6.x from kernel.org
cd linux-4.6.x/arch; ln -s ../../riscv-linux/arch/riscv .
make ARCH=riscv defconfig
make ARCH=riscv menuconfig, configure General setup/Cross-compiler tool prefix
- TODO: libc stuff
- TODO: payload linker script foo
- TODO: patching the console output handler
- mkdir build
- cd build; ../configure --with-payload=path/to/vmlinux CC=path/to/riscv64-unknown-elf-gcc LD=path/to/riscv64-unknown-elf-ld
Building coreboot with bbl
- apply the same coreboot patches as above, and select Emulation/Spike ucb riscv
- in the Payload menu of
menuconfig, select "ELF Payload" and enter the path to the bbl binary
Block devices currently missing