The wiki is being retired!
Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!
This board has a dual BIOS chip. Both chips are 8Mbit; the main BIOS is called M_BIOS, the backup BIOS is called B_BIOS. GIGABYTE claims the backup BIOS can not be flashed by the user. It contains code that will overwrite M_BIOS if it determines that M_BIOS is corrupted.
The M_BIOS chip is a Winbond W25Q64.V.
If you flash coreboot into M_BIOS and something goes wrong, you can force B_BIOS to boot and reflash M_BIOS by bridging pins 4 (GND) and 7 (#HOLD) on the M_BIOS chip. Power up the machine and wait for the screen to turn on. It could take up to 20 seconds, so be patient. Once the screen turned on, you can release the #HOLD pin. The B_BIOS will take over at that point — you will hear a beep, and see the B_BIOS boot and forcibly re-flash M_BIOS.
Dumping the original BIOS
To dump the BIOS from M_BIOS chip you don't need to de-solder the chip as flashrom support is there.
To dump the bios run:
sudo flashrom -r bios.bin
Extract at least Intel Firmware Descriptor and Intel ME binaries.
The system won't boot without this two files, that need to be included into the coreboot rom.
To write coreboot into M_BIOS run the following command.
sudo flashrom -w build/coreboot.rom
The board doesn't have a serial port at the back, but there are pin-headers at the bottom. The pin-headers are labeled "COM" and are connected to Serial0.
Native RAM init
Coreboot supports native ram init, instead of running Intel's Memory Reference Code, to initialize the DRAM. The code seems to work for a subset of boards/CPUs/memories. On this board only channel 1 sometimes works. Channel 0 doesn't work.
Last time tested: June 27th 2015