Difference between revisions of "Board:gigabyte/m57sli"

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(Various fixes.)
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== Which board do you have? ==
== Which board do you have? ==


The GIGABYTE GA-M57SLI-S4 seems to exist in 4 versions as of 2007/05.
The '''GIGABYTE GA-M57SLI-S4''' seems to exist in 4 versions as of 2007/05.


There is a version with a PLCC socket for the BIOS chip ([http://www.motherboards.org/imageview.html?i=/images/reviews/motherboards/1628_p6_6.jpg socketed BIOS]), but this might be a pre-production board since nobody has so far (2007/03) confirmed the purchase of a GA-M57SLI-S4 board with socketed BIOS. The mainboard photo on the backside of the GA-M57SLI-S4 box shows a ROM socket too.
There is a version with a PLCC socket for the BIOS chip ([http://www.motherboards.org/imageview.html?i=/images/reviews/motherboards/1628_p6_6.jpg socketed BIOS]), but this might be a pre-production board since nobody has so far (2007/03) confirmed the purchase of a GA-M57SLI-S4 board with socketed BIOS. The mainboard photo on the backside of the GA-M57SLI-S4 box shows a ROM socket too.
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|WakeOnMouse_status = Untested
|WakeOnMouse_status = Untested
|Flashrom_status = OK
|Flashrom_status = OK
|Flashrom_comments = As of revision 2958, [[Flashrom]] now works under coreboot if you have a PLCC version of this board. Flashrom works fine under the proprietary BIOS. SPI flashing support is on its way, but not 100% there yet. A workaround exists (see "Burning coreboot")
|Flashrom_comments = As of revision 2958, [[Flashrom]] now works under coreboot if you have a PLCC version of this board. Flashrom works fine under the proprietary BIOS. SPI flashing support is on its way, but not 100% there yet. A workaround exists (see [[#Burning coreboot|Burning coreboot]]).


}}
}}
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=== Flashrom ===
=== Flashrom ===


Flashrom works fine under the proprietary BIOS (PLCC32 version). There seem to be some issues under coreboot (PLCC32 version), see this  [http://tracker.coreboot.org/trac/coreboot/ticket/87 this issue tracker ticket].  
Flashrom works fine under the proprietary BIOS (PLCC32 version). There seem to be some issues under coreboot (PLCC32 version), see [http://tracker.coreboot.org/trac/coreboot/ticket/87 this issue tracker ticket].


Flashrom does not yet work on the SOIC version of the board, but that is being worked on. It will detect the SOIC chip, but the read and write functions are not implemented yet (as of 2007-10-13).
Flashrom does not yet work on the SOIC version of the board, but that is being worked on. It will detect the SOIC chip, but the read and write functions are not implemented yet (as of 2007-10-13).


Flashrom can write the MX25L4005 SPI chip, but just under propritary bios.
Flashrom can write the MX25L4005 SPI chip, but only under proprietary BIOS.


== Payload ==
== Payload ==
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== Buildrom vs. manual build ==
== Buildrom vs. manual build ==


You can build a coreboot image with a kconfig-style configuration tool (buildrom) if you want to use FILO or LAB. This is by far the easiest way to build a ROM image. Continue to the [[#Buildrom|Buildrom section]].
You can build a coreboot image with a kconfig-style configuration tool ([[buildrom]]) if you want to use FILO or LAB. This is by far the easiest way to build a ROM image. Continue to the [[#Buildrom|Buildrom section]].


If you want another payload or would like to get closer to the metal, you can use the manual build method outlined below under [[#Manual build|Manual build]].
If you want another payload or would like to get closer to the metal, you can use the manual build method outlined below under [[#Manual build|Manual build]].
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</pre>
</pre>


Note the root device - FILO sees the first sata device as hd4.
Note the root device - FILO sees the first SATA device as '''hd4'''.


In order to get serial output from GRUB, you will also need to add something like this to your menu.lst:
In order to get serial output from GRUB, you will also need to add something like this to your menu.lst:
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The binary will also be considerably larger than its dynamically linked cousin.
The binary will also be considerably larger than its dynamically linked cousin.


Note that you <b>must</b> build a 32-bit version of kexec, because buildrom puts a 32 bit kernel into the ROM image. A 32-bit kexec can kexec into a 64 bit kernel, so if your system is 64 bit this will work just fine.
Note that you '''must''' build a 32-bit version of kexec, because buildrom puts a 32 bit kernel into the ROM image. A 32-bit kexec can kexec into a 64 bit kernel, so if your system is 64 bit this will work just fine.


The LAB code currently expects lab.conf and kexec to live in / on /dev/sda1.
The LAB code currently expects lab.conf and kexec to live in / on /dev/sda1.
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</pre>
</pre>


Note the root device - FILO sees the first sata device as hd4.
Note the root device - FILO sees the first SATA device as '''hd4'''.


Also, the GA-M57SLI-S4 will not boot unless you add acpi_use_timer_override as a kernel option - and use a modern kernel (tested on 2.6.20.1 and up). Hopefully this will be fixed in newer kernels. If you have a somewhat older kernel (tested with 2.6.16 and up), add these options: apic=debug acpi_dbg_level=0xffffffff pci=noacpi,routeirq snd-hda-intel.enable_msi=1.
Also, the GA-M57SLI-S4 will not boot unless you add '''acpi_use_timer_override''' as a kernel option - and use a modern kernel (tested on 2.6.20.1 and up). Hopefully this will be fixed in newer kernels. If you have a somewhat older kernel (tested with 2.6.16 and up), add these options: '''apic=debug acpi_dbg_level=0xffffffff pci=noacpi,routeirq snd-hda-intel.enable_msi=1'''.


=== Current status of the coreboot v2 tree ===
=== Current status of the coreboot v2 tree ===
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   make
   make


This will generate a coreboot.rom image, which is 512KB large. That's the file that should be burned into your BIOS chip.
This will generate a linuxbios.rom image, which is 512KB large. That's the file that should be burned into your BIOS chip.


== Burning coreboot ==
== Burning coreboot ==
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You can use flashrom from the coreboot v2 tree to burn the image:
You can use flashrom from the coreboot v2 tree to burn the image:


   util/flashrom/flashrom -v -w coreboot.rom
   util/flashrom/flashrom -v -w linuxbios.rom


(that's assuming the image is called coreboot.rom; if you used buildrom it would be called gigabyte-m57sli.rom and live in the 'deploy' subdirectory).
(that's assuming the image is called linuxbios.rom; if you used buildrom it would be called gigabyte-m57sli.rom and live in the 'deploy' subdirectory).


NOTE : on the revision v2.0 of the motherboard there was an issue with the decoding of the IO addresses into the LPC bridge of the MCP55 southbridge. It occurred only after booting with coreboot (the factory bios didn't have this issue). It prevented flashrom to access correctly the SPI interface of the IT8716 chip, thus no reflashing was possible after a first burn of coreboot.. (without modchip) This issue was fixed and a full coreboot patch is on the tracks. There is also a workaround for the actual release of coreboot: before using flashrom after booting with coreboot, execute the commands:
'''Note'''': on the revision v2.0 of the motherboard there was an issue with the decoding of the I/O addresses into the LPC bridge of the MCP55 southbridge. It occurred only after booting with coreboot (the factory BIOS didn't have this issue). It prevented flashrom to access correctly the SPI interface of the ITE IT8716F chip, thus no reflashing was possible after a first burn of coreboot (without modchip). This issue was fixed and a full coreboot patch is on the tracks. There is also a workaround for the actual release of coreboot: before using flashrom after booting with coreboot, execute the commands:


   setpci -s 00:01.0 a0.l=70000001
   setpci -s 00:01.0 a0.l=70000001

Revision as of 13:50, 17 January 2008