The wiki is being retired!
Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!
This page describes using coreboot on the HP Pavilion Chromebook 14.
See Chromebooks for additional details.
- 1 Linux quirks
- 2 EHCI debug port
- 3 Make a backup of the original ROM
- 4 Building a complete coreboot image
EHCI debug port
With the default settings, the USB port next to the HDMI connector is the EHCI debug port.
Make a backup of the original ROM
With this chromebook, making a backup of the original ROM is highly recommended. Use the usual procedure of entering developer mode and backing up with the built-in flashrom before proceeding.
Building a complete coreboot image
The following options will need to be enabled to get a working image:
General setup ---> [*] Allow use of binary-only repository Chipset ---> [*] Add a System Agent binary Chipset ---> [*] Add Intel Management Engine firmware
The Video BIOS is available in the blobs repository:
VGA BIOS ---> [*] Add a VGA BIOS image VGA BIOS ---> VGA BIOS path and filename: "3rdparty/mainboard/google/butterfly/snm_2130_coreboot.bin"
It's also a good idea to enable console via CBMEM, while disabling serial and EHCI debug:
Console ---> [ ] Serial port console output Console ---> [ ] USB 2.0 EHCI debug dongle support Console ---> [*] Send console output to a CBMEM buffer Console ---> [*] Show POST codes on the debug console
Unless you plan to run ChromeOS, disable ChromeOS features:
ChromeOS ---> [ ] Build for ChromeOS
The following options may(TM) make life easier in the future:
General setup ---> [*] Use CMOS for configuration values General setup ---> [*] Create a table of timestamps collected during boot
Including the MAC address and keyboard layout
The coreboot that ships with the laptop will read the keyboard layout and MAC address from the flash. Since ChromeOS uses a different layout than CBFS, the region containing these parameters must me included in the CBFS of the custom coreboot. When not building for ChromeOS, coreboot will read this region from a CBFS file named vpd.bin. NOTE: This will only work when "Builf for ChromeOS" is NOT selected. If building for ChromeOS, coreboot will ignore vpd.bin, and try to locate these parameters using fmap.
Find the RO_VPD section
Build flashmap, then run fmap_decode on the extracted chromebook firmware.
$ ./fmap_decode original_chrome_image.rom
Locate the RO_VPD section in the output:
area_offset="0x00600000" area_size="0x00004000" area_name="RO_VPD" area_flags_raw="0x01" area_flags="static"
Extract the RO_VPD section from ROM image.
First, convert area_offset and area_size to decimal, as dd does not accept hexadecimal input, then use dd to extract the RO_VPD section.
$ dd if=original_chrome_image.rom bs=1 skip=ibs=$((area_offset)) count=$((area_size)) of=vpd.bin
Insert vpd.bin in the custom coreboot image:
$ cbfstool build/coreboot.rom add -f vpd.bin -n vpd.bin -t raw