Difference between revisions of "Board:jetway/nf81-t56n-lf"

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(get rid of lspci o/p, we should be done with that detail at this stage)
(remove old and wrong sio dump)
Line 233: Line 233:
 
  flashrom -p ft2232_spi:type=2232H,port=A -c "MX25L1605A/MX25L1606E" -w build/coreboot.rom
 
  flashrom -p ft2232_spi:type=2232H,port=A -c "MX25L1605A/MX25L1606E" -w build/coreboot.rom
 
''assuming'' you have a SPI flasher setup.
 
''assuming'' you have a SPI flasher setup.
−
 
−
== Various logs ==
 
−
 
−
=== SuperI/O tool log ===
 
−
 
−
superiotool r4.0-5364-gb16690d
 
−
Found Fintek F71869AD (vid=0x3419, id=0x0710) at 0x2e
 
−
Register dump:
 
−
idx 02 07 20 21 25 26 27 28  29 2a 2b 2c 2d
 
−
val 00 0b 10 07 00 00 a1 01  6f 24 00 60 2f
 
−
def 00 00 08 14 00 00 MM 38  6f 07 0f 00 28
 
−
LDN 0x00 (Floppy)
 
−
idx 30 60 61 70 74 f0 f2 f4
 
−
val 00 03 f0 06 02 0e ff 00
 
−
def 01 03 f0 06 02 0e 03 00
 
−
LDN 0x01 (COM1)
 
−
idx 30 60 61 70 f0
 
−
val 01 03 f8 04 00
 
−
def 01 03 f8 04 00
 
−
LDN 0x02 (COM2)
 
−
idx 30 60 61 70 f0 f1
 
−
val 00 02 f8 03 00 44
 
−
def 01 02 f8 03 00 04
 
−
LDN 0x03 (Parallel port)
 
−
idx 30 60 61 70 74 f0
 
−
val 00 03 78 07 03 42
 
−
def 01 03 78 07 03 42
 
−
LDN 0x04 (Hardware monitor)
 
−
idx 30 60 61 70
 
−
val 01 02 25 00
 
−
def 01 02 95 00
 
−
LDN 0x05 (Keyboard)
 
−
idx 30 60 61 70 72 f0 fe ff
 
−
val 01 00 60 01 0c ff 81 29
 
−
def 01 00 60 01 0c 83 81 29
 
−
LDN 0x06 (GPIO)
 
−
idx 30 60 61 70 f0 f1 f2 f3  e0 e1 e2 e3 e4 e5 e6 d0  d1 d2 d3 c0 c1 c2 b0 b1  b2 b3 a0 a1 a2 a3 90 91  92 93
 
−
val 01 0a 00 00 00 3f 00 00  20 df 91 00 00 00 05 00  ff a7 00 ff 00 00 00 ff  73 00 00 1f 00 ff 00 ff  00 00
 
−
def 00 00 00 00 00 3f NA 00  00 ff NA 00 00 00 00 00  ff NA 00 00 ff NA 00 0f  NA 00 00 1f NA 00 00 3f  NA 00
 
−
LDN 0x07 (BSEL)
 
−
idx 30 60 61 f0 f2 f3 f4 f5  f6 f7
 
−
val 00 00 00 01 ff ff ff 12  0a 01
 
−
def 00 00 00 01 00 00 NA 00  0a 00
 
−
LDN 0x0a (PME, ACPI)
 
−
idx 30 f0 f1 f2 f3 f4 f5 f6  f7 f8 f9 fe ff
 
−
val 00 00 6a 00 00 46 1c 1f  86 00 00 00 00
 
−
def 00 00 00 NA NA 06 1c 1f  86 00 00 00 00
 
  
 
=== Coreboot S3 resume log ===
 
=== Coreboot S3 resume log ===

Revision as of 05:38, 15 April 2014

This page describes how to use coreboot on the Jetway NF81-T56N-LF mainboard.

This page is a work in progress. ACPI is still being worked on, however due to the nature of ACPI it may take some time to get this right.

Known Issues

  • pcie 06.0 bridge sometimes hangs probing the nic behind it. Linux reports a borked IRQ addr. They are likely connected? (Fix ACPI).
  • superio not controlling fan - fix known, patch WIP!
  • suspend/resume could do with some work to clean up nasty warnings.. (Fix ACPI).
  • some werid AGESA issue affects a number of boards

pcie 06.0 bridge hang issue

The pcie 06.0 bridge hang issue is the primary remaining issue.

The Interrupt Mask Register (IMR) and Interrupt Service Register (ISR) are responsible for firing up different IRQs. The IMR bits line up with the ISR bits to work in sync. If an IMR bit is low, then the corresponding ISR bit with never fire an IRQ when the time comes for it to happen. The IMR is located at 0x3C and the ISR is located at 0x3E.


Observe in the vendor bios pci configuration space dump attached below that, indx. 0x3C (IMR) = 0x0b and indx. 0x3E (ISR) = 0x10. 

IMR val. = 0000 1011 = INTB
ISR val. = 0000 1010
====================
        &= 0000 1010
====================

root@archiso ~ # hexdump -C /sys/bus/pci/devices/0000:00:06.0/config
00000000  22 10 14 15 07 00 10 00  00 00 04 06 10 00 01 00  |"...............|
00000010  00 00 00 00 00 00 00 00  00 02 02 00 e1 e1 00 00  |................|
00000020  f0 ff 00 00 11 d0 11 d0  00 00 00 00 00 00 00 00  |................|
00000030  00 00 00 00 50 00 00 00  00 00 00 00 0b 01 10 00  |....P...........|
00000040  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
00000050  01 58 03 c8 00 00 00 00  10 a0 42 01 20 80 00 00  |.X........B. ...|
00000060  00 08 00 00 11 0c 30 03  40 00 11 70 80 25 34 00  |......0.@..p.%4.|
00000070  00 00 48 01 00 00 01 00  00 00 00 00 1f 00 00 00  |..H.............|
00000080  06 00 00 00 00 00 00 00  21 00 00 00 00 00 00 00  |........!.......|
00000090  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
000000a0  05 b0 80 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
000000b0  0d b8 00 00 22 10 34 12  08 00 03 a8 00 00 00 00  |....".4.........|
000000c0  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
*
000000e0  50 00 00 00 02 00 00 00  00 00 00 00 00 00 00 00  |P...............|
000000f0  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
00000100  0b 00 01 00 01 00 01 01  00 00 00 00 00 00 00 00  |................|
00000110  02 00 01 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
00000120  01 00 00 00 ff 00 00 80  00 00 00 00 01 00 00 00  |................|
00000130  00 00 00 00 00 00 02 00  00 00 00 00 00 00 00 00  |................|
00000140  03 00 01 00 01 00 00 00  00 87 0c 00 00 00 00 00  |................|
00000150  01 00 01 00 00 00 00 00  00 00 00 00 30 20 06 00  |............0 ..|
00000160  00 00 00 00 00 20 00 00  00 00 00 00 00 00 00 00  |..... ..........|
00000170  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
*
00000190  0d 00 01 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
000001a0  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
*
00001000

Investigate in board support: 

* acpi/routing.asl
* mptable.c

weird AGESA issue

The function call goes something like this; In 

mainboard/jetway/nf81-t56n-lf/agesawrapper.c

the function 

UINT32 agesawrapper_amdinitpost(VOID)

calls 

status = AmdInitPost ((AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr);

this returns a error code of 

AGESA_WARNING = 0x4

this triggers 

if(status != AGESA_SUCCESS) agesawrapper_amdreadeventlog();

giving the resulting message: 

EventLog:       EventClass = 2, EventInfo = 8040100.
...

grep'ing we have that: 

AGESA.h:#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT     0x08040100ul

However tracing the call back to where AGESA_WARNING is set goes back to: 

vendor/amd/agesa/f14/Proc/Mem/Main/mmflow.c

line 290 here: 

Retval = NBPtr[Die].MCTPtr->ErrCode;

with Die=0.

Status

Device/functionality Status Comments
CPU
CPU works OK
L1 cache enabled OK Always on
L2 cache enabled OK Always on
L3 cache enabled N/A
Multiple CPU support N/A
Multi-core support N/A
Hardware virtualization WIP
RAM
EDO N/A
SDRAM N/A
SO-DIMM N/A
DDR N/A
DDR2 N/A
DDR3 OK Tested with 4GB two-rank module.
Dual channel support N/A
ECC support  ?
On-board Hardware
On-board IDE 3.5" N/A
On-board IDE 2.5" N/A
On-board SATA OK
On-board SCSI N/A
On-board USB OK
On-board VGA OK BIOS/console: works.
On-board Ethernet OK
On-board Audio OK Basic two channel audio works fine.
On-board Modem N/A
On-board FireWire N/A
On-board Smartcard reader N/A
On-board CompactFlash N/A
On-board PCMCIA N/A
On-board Wifi N/A
On-board Bluetooth N/A
On-board SD card reader N/A
Add-on slots/cards
ISA add-on cards N/A
Audio/Modem-Riser (AMR/CNR) cards N/A
PCI add-on cards OK
Mini-PCI add-on cards N/A
Mini-PCI-Express add-on cards Unknown
PCI-X add-on cards N/A
AGP graphics cards N/A
PCI Express x1 add-on cards OK miniPCIe slot works, mSATA/miniPCIe slot does not!?
PCI Express x2 add-on cards N/A
PCI Express x4 add-on cards N/A
PCI Express x8 add-on cards N/A
PCI Express x16 add-on cards N/A
PCI Express x32 add-on cards N/A
HTX add-on cards N/A
Legacy / Super I/O
Floppy N/A
Serial port 1 (COM1) OK
Serial port 2 (COM2) N/A
Parallel port N/A
PS/2 keyboard OK
PS/2 mouse OK
Game port N/A
Infrared Untested CIR header currently turned off in devicetree.cb
PC speaker OK
DiskOnChip N/A
Input
Trackpoint N/A
Touchpad N/A
Fn Hotkeys N/A
Fingerprint Reader N/A
Laptop
Docking VGA N/A
Docking LAN N/A
Docking USB N/A
Docking Audio N/A
Docking Displayport N/A
Thinklight N/A
Webcam N/A
Miscellaneous
Sensors / fan control Pending See Gerrit 5500
Hardware watchdog Pending See Gerrit 5500
SMBus OK
CAN bus N/A
CPU frequency scaling OK
Other powersaving features N/A
ACPI WIP Mostly working, needs a good Review!
Reboot OK
Poweroff OK
Suspend OK
Nonstandard LEDs N/A
High precision event timers (HPET) OK
Random number generator (RNG) OK
Wake on modem ring N/A
Wake on LAN Untested
Wake on keyboard Untested
Wake on mouse Untested
TPM Unknown
Flashrom OK MXIC MX25L1606E 2MB SPI Flash

Hardware

Overview

  • AMD Fusion G-series AMD Fusion G-T56N (1.65 GHz dual core) APU
  • AMD A55E part of the chipset, AMD A55E (Hudson-E1) southbridge
  • F71869AD Fintek F71869AD Super I/O
  • RTL8111E Twin Realtek RTL8111E network controllers
  • VT1705 6-Channel HD Audio (via VIA VT1705), AC97 AD/DA

Details

The NF81-T56N-LF is a IPC form factor embedded board:

  • AMD Fusion G-T56N (1.65 GHz dual core) APU
    • 2x SO-DIMM sockets for DDR3 800-1066 SDRAM (Fixed at 1.5V)
    • VGA and LVDS (via Analogix ANX3110)
  • AMD A55E (Hudson-E1) southbridge
    • 6x USB 2.0/1.1 ports
    • 5x SATA3 6Gb/s, 1x mSATA socket
    • 6-Channel HD Audio (via VIA VT1705)
    • PCI and ISA (via ITE IT8888)??
    • NEC uPD78F0532 microcontroller on I2C ("SEMA")??
  • 2x RJ45 GbE (via Realtek RTL8111E x2)
  • Fintek F71869AD Super I/O
    • PS/2 KB/MS port
    • RS232 header (via Unisonic UTC 75232 RS232 driver/receiver)
    • GPIO header
    • CIR header
  • 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)

Note: MX25L1606E is 16Mbit, 8bits in a byte, so 2MB. Jetway lies claiming the SPI flash is 16MB. They also use red pen over the chip so you wont see this deceit.

Building a coreboot image

Make a fresh clone of Coreboot into a empty directory and run: 

make crossgcc-i386

Make a cup of tea.. Then run: 

make menuconfig

and select Jetway/NF81-t56N-LF under "Mainboard -> Mainboard vendor/model" leaving everything else as defaults. Then finally do, 

make

To flash the board with flashrom run: 

flashrom -p ft2232_spi:type=2232H,port=A -c "MX25L1605A/MX25L1606E" -w build/coreboot.rom

assuming you have a SPI flasher setup.

Coreboot S3 resume log

S3 Suspend/Resume works by running: 

# echo "mem" > /sys/power/state

However a issue remains of wanrings about resources being not assigned.

For details see in src/device/pnp_device.c the function: 

static void pnp_set_resource(device_t dev, struct resource *resource)
{
	if (!(resource->flags & IORESOURCE_ASSIGNED)) {
		printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx "
		       "not assigned\n", dev_path(dev), resource->index,
		       resource_type(resource), resource->size); 
		return;
	}
 ...

and in src/device/device_util.c the function: 

const char *resource_type(struct resource *resource)
{
	static char buffer[RESOURCE_TYPE_MAX];
	snprintf(buffer, sizeof (buffer), "%s%s%s%s",
		 ((resource->flags & IORESOURCE_READONLY) ? "ro" : ""),
		 ((resource->flags & IORESOURCE_PREFETCH) ? "pref" : ""),
		 ((resource->flags == 0) ? "unused" :
		  (resource->flags & IORESOURCE_IO) ? "io" :
		  (resource->flags & IORESOURCE_DRQ) ? "drq" :
		  (resource->flags & IORESOURCE_IRQ) ? "irq" :
		  (resource->flags & IORESOURCE_MEM) ? "mem" : "??????"),
		 ((resource->flags & IORESOURCE_PCI64) ? "64" : ""));
	return buffer;
}

and in src/include/device/resource.h the struct resource: 

struct resource {
..
 	unsigned long index;	/* Bus specific per device resource id */
..

Analysis: 

 ERROR: PCI: 00:18.0 1088 ??????64 size: 0x0000000000 not assigned
        -----------^ ---^ -------^       -----------^
                   |    |        |                  |
                   |    |        |                  +--- resource->size
                   |    |        |
                   |    |        +--- resource_type(resource)
                   |    |
                   |    +--- resource->index
                   |
                   +--- dev_path(dev)

A dev_path of type DEVICE_PATH_PCI (Host Bridge) at 18.0 of IORESOURCE_MEM type has a bus specific index of 1088.

Possibly related to the devicetree.cb ??

See log below: 

Booting from Hard Disk...
Booting from 0000:7c00



coreboot-4.0-5634-gfe71e8b-ap-jupiter-alpha Mon Mar 10 02:01:03 EST 2014 starting...
S3 detected
CBFS: loading stage fallback/coreboot_ram @ 0x200000 (1429552 bytes), entry @ 0x200000
coreboot-4.0-5634-gfe71e8b-ap-jupiter-alpha Mon Mar 10 02:01:03 EST 2014 booting...
Enumerating buses...
Mainboard NF81-T56N-LF Enable.
setup_bsp_ramtop, TOP MEM: msr.lo = 0xe0000000, msr.hi = 0x00000000
setup_bsp_ramtop, TOP MEM2: msr.lo = 0x1f000000, msr.hi = 0x00000001
setup_uma_memory: uma size 0x18000000, memory start 0xc8000000
PCI: Static device PCI: 00:04.0 not found, disabling it.
sm_init().
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
done
Allocating resources...
Reading resources...
APIC: 00 missing read_resources
APIC: 01 missing read_resources
I2C: 00:50 missing read_resources
I2C: 00:51 missing read_resources
Done reading resources.
Setting resources...
ERROR: PCI: 00:18.0 1080 ??????64 size: 0x0000000000 not assigned
ERROR: PCI: 00:18.0 1088 ??????64 size: 0x0000000000 not assigned
Done setting resources.
Done allocating resources.
Enabling resources...
done.
Initializing devices...
Initializing CPU #0
Enabling cache
Setting up local apic...done.
CPU #0 initialized
Initializing CPU #1
Waiting for 1 CPUS to stop
Enabling cache
Setting up local apic...done.
CPU #1 initialized
Devices initialized
Finalize devices...
Devices finalized

Coreboot boot log

See [1] for a recent log.

Public domain I, the copyright holder of this work, hereby release it into the public domain. This applies worldwide.

In case this is not legally possible:
I grant anyone the right to use this work for any purpose, without any conditions, unless such conditions are required by law.

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