From coreboot
Revision as of 12:06, 10 March 2016 by IruCai (talk | contribs) (update the USBDEBUG issue, CPU)
Jump to navigation Jump to search

The wiki is being retired!

Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to Contributions welcome!


Thanks for your interest in Lenovo T420 port. The code has not been merged yet, you can see the code on gerrit.


  • The USB port that used for EHCI debug cannot funtion after S3 resume if CONFIG_USBDEBUG is set (seems to be the southbridge problem, occurs in older systems but not in newer systems, I just can't figure out why, work around: reload ehci-pci module)
  • Badly seated RAM may prevent booting (not really a problem but coreboot is more suspicious to this than vendor BIOS)


  • CPU: Sandy Bridge i5-2520M, i7-2630QM, and Ivy Bridge i5-3360M, i7-3720QM
  • RAM module combinations of 2G+0, 4G+0, 8G+0, 0+8G, 4G+8G, 8G+8G
  • S3 (Suspend to RAM)
  • mSATA
  • USB
  • Video (internal, VGA)
  • Sound (integrated speakers, integrated mic, external headphones, external mic)
  • LAN
  • Mini-PCIe slots (WLAN)
  • Bluetooth
  • Fingerprint reader
  • Linux (through GRUB-as-payload and a typical MBR install through SeaBIOS)
  • Windows (through SeaBIOS as payload or chainload SeaBIOS from GRUB payload, using a VGA BIOS)
  • DVD-ROM drive
  • SD card slot
  • TrackPoint
  • Touchpad
  • Webcam
  • Fn hotkeys (backlight control, suspend, thinklight)
  • Thinklight
  • Dock (tested with a TYPE 4337)

Not Tested:

  • Video (DisplayPort)
  • ExpressCard slot (including hotplugging)
  • Mini PCIe WWAN
  • Thermal management

Proprietary components status

  • CPU Microcode (optional): you may need it if your system is unstable (especially you're using a ES/QS processor)
  • VGA Option ROM (optional): you need it if you want graphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode)
  • ME (Management Engine) => you do not have to touch it (just leave as is)
  • EC (Embedded Controller) => you do not have to touch it (just leave as is)


A build instruction has been written on bitbucket.

To obtain ME, Intel Descriptor, GbE images you will need to read the BIOS off your T420. Using ifdtool you can extract those images from the backup BIOS image.

 ifdtool -x </path/to/extracted/flash.bin>

The bios_extract did not work on my backup so I had to use PhoenixTool to dump the VGA BIOS. Using UEFITool to dump the VGA BIOS is recommended. On some T420's, a weird graphical glitch might occur using native graphics initialization. I managed to workaround through this problem by using the Option ROM initialization instead of the native way but YMMV (could the 1600x900 panel or a too new VBIOS (2119) cause issues?).


T420 has an SOIC-8 flash chip of 8M (Winbond W25Q64CVSIG). It's subdivided in roughly in 3 parts:

  • Descriptor (12K)
  • ME firmware (5M-12K)
  • System flash (3M)

ME firmware is not readable. Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).

Proceed as follows:

  • Turn off your laptop, remove battery and AC adapter.
  • Disassemble the T420 laptop as the hardware maintenance manual says. You have to take out the mainboard, because the flash chip is under the magnesium stucture frame.
  • Connect your external SPI flasher to the SPI chip. Using an SOIC-8 clip is recommended although the flash can be done without one. Make a backup of the original BIOS in a safe place.
  • Flash the chip with coreboot using flashrom.
  • Reassemble the laptop.
  • Plug in the AC adapter and turn on the laptop.

Using the Bus Pirate as an SPI flasher the pinout is as such:

       Bus Pirate   W25Q64BV
       CS           /CS (1)
       3.3V         VCC (8)
       MISO         DO (2)
       CLK          CLK (6)
       GND          GND (4)
       MOSI         DI (5)

To read the chip using the Bus Pirate:

 flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -r <output file>

To flash the chip using the Bus Pirate:

 flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -w <coreboot image>

Reading and writing using the Bus Pirate takes time. Use the version 6.2 bootloader to make the reads and flashes faster.

I highly recommend reading the chip twice to make sure you have a stable connection. Make sure to read and compare your images like so:

 flashrom -p <yourprogrammer> -r flash.bin
 flashrom -p <yourprogrammer> -r flash2.bin
 diff flash.bin flash2.bin

If you have trouble reading the chip successfully, the most common problems are:

  • Insufficient power supply
  • Bad contacts
  • Too long wires
  • Bad pinout

For more information on the chip, refer to the official datasheet of the chip available here: Winbond W25Q64CV

When the laptop is running coreboot, you can reflash the firmware using flashrom:

 flashrom -p internal:laptop=force_I_want_a_brick -w <coreboot image>

Ivy Bridge processor support

Sandy Bridge and Ivy Bridge processors use the same socket, so an Ivy Bridge processor can be installed. To use native graphics init, you should use a patch on gerrit so that coreboot can use the correct code for native graphics init, this change has been merged to upstream and you need to change the Kconfig symbol SANDYBRIDGE_LVDS to SANDYBRIDGE_IVYBRIDGE_LVDS. You can also use a VGA option ROM with SeaBIOS. Manually adding VGA option ROMs for both type of GPUs is recommended (see the build instructions above).