The wiki is being retired!
Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!
Thanks for your interest in Lenovo T420 port.
- The USB/eSATA hybrid port that are used for EHCI debug cannot funtion after S3 resume if CONFIG_USBDEBUG is set (seems to be the southbridge problem, occurs in older Linux systems but not in newer Linux systems, I just can't figure out why, work around: reload ehci-pci module)
- Badly seated RAM may prevent booting (not really a problem but coreboot is more suspicious to this than vendor BIOS)
- CPU: Sandy Bridge i5-2520M, i7-2630QM, and Ivy Bridge i5-3360M, i7-3720QM
- RAM module combinations of 2G+0, 4G+0, 4G+4G, 8G+0, 0+8G, 4G+8G, 8G+8G
- S3 (Suspend to RAM)
- Video (internal, VGA)
- Sound (integrated speakers, integrated mic, external headphones, external mic)
- Mini-PCIe slots (WLAN)
- Fingerprint reader
- Linux (through GRUB-as-payload and a typical MBR install through SeaBIOS)
- Windows (through SeaBIOS as payload or chainload SeaBIOS from GRUB payload, using a VGA BIOS)
- DVD-ROM drive
- SD card slot
- Fn hotkeys (backlight control, suspend, thinklight)
- Dock (tested with a TYPE 4337)
- ExpressCard slot (hotplugging not work)
- eSATA (hotplugging not work)
- Ctrl-Fn swap
- Video (DisplayPort)
- Mini PCIe WWAN
- Thermal management
Proprietary components status
- CPU Microcode (optional): you may need it if your system is unstable (especially you're using a ES/QS processor)
- VGA Option ROM (optional): you need it if you want graphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode)
- ME (Management Engine) => you do not have to touch it (just leave as is)
- EC (Embedded Controller) => you do not have to touch it (just leave as is)
make nconfig, and select the board Lenovo T420. Other configurations include:
- Size of CBFS can be set up to 3M (0x300000), if you use a stripped ME from HM65 chipset, it can be more.
- You can select 'Use CMOS for configuration values'.
- You can use native graphics initialization.
- EHCI debug dongle support is recommended for debugging.
To obtain ME, Intel Descriptor, GbE images you will need to read the BIOS off your T420. Using
ifdtool you can extract those images from the backup BIOS image.
ifdtool -x </path/to/extracted/flash.bin>
You can use UEFITool or PhoenixTool to extract the VGA BIOS from factory firmware or Lenovo firmware update images, or dump the VGA BIOS via sysfs on Linux. See Retrieve VGA BIOS page for more details.
To use VGA option ROMs, you can manually add it to CBFS using cbfstool multiple times to support more GPUs on a single board. Or make use of file aliasing from SeaBIOS:
./build/cbfstool build/coreboot.rom add -f vgabios.rom -n pci8086,0106.rom -t optionrom ./build/cbfstool build/coreboot.rom add -f links -n links -t raw
The content of file
links is as follows:
pci8086,0116.rom pci8086,0106.rom pci8086,0126.rom pci8086,0106.rom pci8086,0166.rom pci8086,0106.rom
If the payload is not SeaBIOS, coreboot also support running VGA option ROMs, and the fallback file name is
pci8086,0106.rom, so you can just add it with this name.
On some T420's, a weird graphical glitch might occur using native graphics initialization. I managed to workaround through this problem by using the Option ROM initialization instead of the native way but YMMV (could the 1600x900 panel or a too new VBIOS (2119) cause issues?).
T420 has an SOIC-8 flash chip of 8M (Winbond W25Q64CVSIG). It's subdivided in roughly in 3 parts:
- Descriptor (12K)
- ME firmware (5M-12K)
- System flash (3M)
ME firmware is not readable. Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).
Proceed as follows:
- Turn off your laptop, remove battery and AC adapter.
- Disassemble the T420 laptop as the hardware maintenance manual says. You have to take out the mainboard, because the flash chip is under the magnesium stucture frame.
- Connect your external SPI flasher to the SPI chip. Using an SOIC-8 clip is recommended although the flash can be done without one. Make a backup of the original BIOS in a safe place.
- Flash the chip with coreboot using flashrom.
- Reassemble the laptop.
- Plug in the AC adapter and turn on the laptop.
Using the Bus Pirate as an SPI flasher the pinout is as such:
Bus Pirate W25Q64BV CS /CS (1) 3.3V VCC (8) MISO DO (2) CLK CLK (6) GND GND (4) MOSI DI (5)
To read the chip using the Bus Pirate:
flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -r <output file>
To flash the chip using the Bus Pirate:
flashrom -p buspirate_spi:dev=/dev/ttyUSB0 -w <coreboot image>
Reading and writing using the Bus Pirate takes time. Use the version 6.2 bootloader to make the reads and flashes faster.
I highly recommend reading the chip twice to make sure you have a stable connection. Make sure to read and compare your images like so:
flashrom -p <yourprogrammer> -r flash.bin flashrom -p <yourprogrammer> -r flash2.bin diff flash.bin flash2.bin
If you have trouble reading the chip successfully, the most common problems are:
- Insufficient power supply
- Bad contacts
- Too long wires
- Bad pinout
For more information on the chip, refer to the official datasheet of the chip available here: Winbond W25Q64CV
When the laptop is running coreboot, you can reflash the firmware using flashrom:
flashrom -p internal:laptop=force_I_want_a_brick -w <coreboot image>