The wiki is being retired!
Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!
Thanks for your interest in Lenovo X230 port. Issues:
- no MRC cache (longer boot time)
- yellow USB port isn't powered in power-off state.
- Badly seated RAM may prevent booting (not really a problem but coreboot is more suspicious to this than vendor BIOS)
- S3 (Suspend to RAM)
- RAM module combinations of 8G+8G, 8G+0, 0+8G, 4G+8G, 8G+4G, 8G+1G, 1G+0, 0+1G, 4G+0, 0+4G
- USB (both 2.0 and 3.0 ports)
- Video (both internal and VGA)
- Expresscard slot (including hotplugging)
- Sound (integrated speakers, integrated mic, external headphones, external mic)
- mini-PCIe slots (both wlan and wwan)
- Linux (through GRUB-as-payload)
- Windows (through GRUB-as-payload loading SeaBIOS image from disk; you have to use extracted VGA blob, dumped from memory isn't good enough)
- SD card slot
- Thermal management
- Fingerprint reader.
- Fn hotkeys
- Keyboard backlight
- msata (fixed in commit c8f54a1109072706e2fa091dc9ab4ad3eb057b42)
- mini displayport
- digitizer on x230t variant
proprietary components status
- CPU Microcode
- VGA Option ROM (optional): you need it if you want graphics in SeaBIOS but most payloads should work without it (text mode or corebootfb mode)
- ME (Management Engine) => you do not have to touch it (just leave it where it is)
- EC (Embedded Controller) => you do not have to touch it (just leave it where it is)
- The code has been merged into coreboot master:
$ git clone https://review.coreboot.org/coreboot.git
X230 has 2 flash chips of 8M and 4M. They're concatenated to one virtual flash chip of 12M which is itself subdivided in roughly in 3 parts:
- Descriptor (12K)
- ME firmware (5M-12K)
- System flash (7M)
ME firmware is not readable. Vendor firmware locks the flash and so you need to flash externally (unless until someone figures out a way around it).
Proceeds as follows:
- Turn off your laptop, remove battery and AC adapter.
- Remove the keyboard.
- Connect your external SPI flasher to the top SPI chip which is under palm resting space, on left side of the board. It's a 4M chip. IF you've chosen CBFS_SIZE 4M or smaller that' the only chip you need to reflash.
I recommend using SOIC clip. Depending on the flasher you use, you may have to use separate 3.3V source. Make sure not to feed more than 3.3V ot the chip. I used buspirate as flasher and 3.3V power lines from another computer.
- Read the flash. Twice. Compare the files to be sure. Save a copy of it on
flashrom -p <yourprogrammer> -r flash.bin flashrom -p <yourprogrammer> -r flash2.bin diff flash.bin flash2.bin
If they don't match, do not proceed. If the file is 8M, you're flashing wrong chip, connect to the right one.
- Write the flash. Since you have to write only top 4M, first split out those 4M:
dd of=top.rom bs=1M if=build/coreboot.rom skip=8
- Use flashrom to flash top.rom.
If you have trouble reading the chip successfully, the most common problems are
- insufficient power supply
- bad contacts
- too long wires
- bad pinout
The cable shipped with buspirate was too long, and needed to be trimmed.
See also In-System Programming