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The wiki is being retired!

Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to Contributions welcome!

This page lists the coreboot status of the Nokia IP530 mainboard. It's maintained by Marc Bertens.


The Nokia IP530 is originally a Firewall that runs on the proprietary IPSO operating system of Nokia, it was based in the FreeBSD operating system. The original is only capable of starting a FreeBSD FS. There is as far as i known no CD support in the orginal BIOS.

The System has NO VGA, all console activity must be done through a serial console.


Device/functionality Status Comments
CPU works OK
L1 cache enabled OK CPU: L1 I cache: 16K, L1 D cache: 16K
L2 cache enabled WIP L2 cache is not being enabled at the moment. We're working on fixing it.
L3 cache enabled N/A
Multiple CPU support N/A
Multi-core support N/A
Hardware virtualization N/A
Dual channel support N/A
ECC support WIP Not yet supported by the coreboot 440BX code, but it's on our TODO list.
On-board Hardware
On-board IDE 3.5" OK
On-board IDE 2.5" N/A
On-board SATA N/A
On-board SCSI N/A
On-board USB N/A
On-board VGA N/A
On-board Ethernet OK
On-board Audio N/A
On-board Modem N/A
On-board FireWire N/A
On-board Smartcard reader N/A
On-board CompactFlash OK
On-board PCMCIA OK
On-board Wifi N/A
On-board Bluetooth N/A
On-board SD card reader N/A
Add-on slots/cards
ISA add-on cards N/A
Audio/Modem-Riser (AMR/CNR) cards N/A
PCI add-on cards OK Tested: With 4 Ethernet adapter card of Nokia
Mini-PCI add-on cards N/A
Mini-PCI-Express add-on cards Unknown
PCI-X add-on cards N/A
AGP graphics cards N/A
PCI Express x1 add-on cards N/A
PCI Express x2 add-on cards N/A
PCI Express x4 add-on cards N/A
PCI Express x8 add-on cards N/A
PCI Express x16 add-on cards N/A
PCI Express x32 add-on cards N/A
HTX add-on cards N/A
Legacy / Super I/O
Floppy N/A
Serial port 1 (COM1) OK
Serial port 2 (COM2) OK
Parallel port N/A
PS/2 keyboard N/A
PS/2 mouse N/A
Game port N/A
Infrared N/A
PC speaker N/A
DiskOnChip N/A
Trackpoint N/A
Touchpad N/A
Fn Hotkeys N/A
Fingerprint Reader N/A
Docking VGA N/A
Docking LAN N/A
Docking USB N/A
Docking Audio N/A
Docking Displayport N/A
Thinklight N/A
Webcam N/A
Sensors / fan control No
Hardware watchdog N/A
CAN bus N/A
CPU frequency scaling N/A
Other powersaving features N/A
ACPI No There's no ACPI implementation for this board, but it's on our TODO list.
Reboot N/A
Poweroff N/A
Suspend Unknown
Nonstandard LEDs No Special-purpose LEDs available on the board, but it's on our TODO list.
High precision event timers (HPET) N/A
Random number generator (RNG) N/A
Wake on modem ring N/A
Wake on LAN N/A
Wake on keyboard N/A
Wake on mouse N/A
TPM Unknown
Flashrom OK

System Setup

Below the description is given for the connectors on the mainboard of the Nokia IP530. Due missing documentation of the manufacturer.


The JDEBUG connector can be used for attaching a external ROM (flash chip) to the board for BIOS development.

JDEBUG connector
Pin# Name Description Pin# Name Description
1 unknown ? 2 VCC +5 Volt n/a
3 A16 Address line A16 4 A18 Address line A18
5 A15 Address line A15 6 A17 Address line A17
7 A12 Address line A12 8 A14 Address line A14
9 A7 Address line A7 10 A13 Address line A13
10 A7 Address line A7 10 A13 Address line A13
11 A6 Address line A6 12 A8 Address line A8
13 A5 Address line A5 14 A9 Address line A9
15 A4 Address line A4 16 A11 Address line A11
17 A3 Address line A3 18 OE# Chip Enable Line OE#
19 A2 Address line A2 20 A10 Address line A10
21 A1 Address line A1 22 JP800.1 BIOSCS#
23 A0 Address line A0 24 D7 Data line D7
25 D0 Data line A0 26 D6 Data line D6
27 D1 Data line D1 28 D5 Data line D5
29 D2 Data line D2 30 D4 Data line D4
31 IOW# Control line IOW# 32 D3 Data line D3
33 GND Ground 34 IOR# Control line IOR#

Jumper JP800 - BIOSCS select

This jumper selected the on-board flash or the J-DEBUG connector where the BIOSCS# line is routed.

J800 Jumper
Pin# Name Description
1 JDEBUG.P22 This is connected to PIN 22 of the JDEBUG connection on the board
2 BIOSCS# Connected to the ROMCS# line of the Northbridge
3 CS# This is connected to CS# of the on-board flash chip.

The WP# line of the on-board flashchip is controlled by Pin39 of the SMSC 37B787 super IO chip

On the production boards the J800 is not present and the R814 (0 Ohm) is placed, remove this resistor and solder in the 3 pin-jumper for JP800. And place the jumper on position 2-3 to select the on-board flash chip.

Jumper JP900

This is a input signal on the super IO chip

J900 Jumper
Pin# Name Description
1 GND Ground if the system
2 GPIO16 Pin 4 of the SMSC 37B787 super IO chip.

Pin 2 is pulled-up by resistor up VCC

Jumper JP901

This is a input signal on the super IO chip

J901 Jumper
Pin# Name Description
1 GND Ground if the system
2 GPIO67 Pin 90 of the SMSC 37B787 super IO chip.

Pin 2 is pulled-up by resistor up VCC

Jumper JKBD

JKBD Connector
Pin# Name Description
1 VCC VCC +5 volt
2 DATA The DAT line of the PS2 keyboard (pin 70 SMSC 37B787)
3 CLOCK The CLK line of the PS2 keyboard (pin 71 SMSC 37B787)
4 GND Ground if the system

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