Difference between revisions of "Board:via/epia-m850"
|(One intermediate revision by the same user not shown)|
|Line 167:||Line 167:|
| 2: ||GND || #CS || MOSI || ??
| 2: ||GND || #CS || MOSI || ? ?
| 1: || VCC || CLK || MISO ||
| 1: || VCC || CLK || MISO ||
Latest revision as of 20:56, 18 January 2014
Placeholder for EPIA-M850 board. Content coming soon. Please yell at mrnuke on #coreboot if nothing changes soon. He's from Texas, he won't mind.
The EPIA-M850 is a mini-ITX board from VIA. It comes with either a 1.3GHz or 1.6GHz via Nano CPU, and a VX900 chipset.
This board is not fully supported. It has a number of issues one should be prepared to deal with.
- On DIMMs with two memory ranks, odd ranks are disabled by default. The memory initialization does not deal with odd ranks very well, and leaves them disabled.
- Even with a VGA BIOS, you will get a garbled display. GRUB2 and linux are able to get a working text console though, but only if a VGA BIOS has been run.
- IRQs only work in PIC mode (no APIC and no ACPI). Do not expect to boot anything other than linux, and be prepared to boot with "noapic acpi=off 3": that is disable APICs _and_ do not use ACPI _and_ start in runlevel 3.
- Cards plugged in PCI-Express slots may not work.
- Linux sometimes likes to just hang. It stops responding: no serial output, no panic message, no response to keyboard presses.
If you still want to try coreboot on this board, have a way to recover by flashing externally in case things go south. There is an SPI header that can be used to reprogram the ROM if the board is powered off. flashrom does NOT work when running coreboot; this is NOT a good recovery plan.
- 1 Status
- 2 Getting ready for coreboot
- 3 Hacking
- 4 Photos
|L1 cache enabled||OK||Always on|
|L2 cache enabled||OK||Always on|
|L3 cache enabled||N/A|
|Multiple CPU support||N/A|
|DDR3||Even ranks only|
|Dual channel support||N/A|
|On-board IDE 3.5"||N/A||N/A|
|On-board IDE 2.5"||N/A|
|On-board VGA||Not OK|
|On-board Smartcard reader||N/A|
|On-board SD card reader||N/A|
|ISA add-on cards||N/A|
|Audio/Modem-Riser (AMR/CNR) cards||N/A|
|PCI add-on cards||N/A|
|Mini-PCI add-on cards||Unknown|
|Mini-PCI-Express add-on cards||Unknown|
|PCI-X add-on cards||Unknown|
|AGP graphics cards||N/A|
|PCI Express x1 add-on cards||?|
|PCI Express x2 add-on cards||?|
|PCI Express x4 add-on cards||?|
|PCI Express x8 add-on cards||N/A|
|PCI Express x16 add-on cards||N/A|
|PCI Express x32 add-on cards||N/A|
|HTX add-on cards||N/A|
|Legacy / Super I/O|
|Serial port 1 (COM1)||OK|
|Serial port 2 (COM2)||Not tested|
|PS/2 mouse||Not tested|
|PC speaker||Not tested|
|Sensors / fan control||Not tested|
|Hardware watchdog||Not tested|
|CPU frequency scaling||Not tested|
|Other powersaving features||N/A|
|High precision event timers (HPET)||Not tested|
|Random number generator (RNG)||N/A|
|Wake on modem ring||Untested|
|Wake on LAN||Untested|
|Wake on keyboard||Untested|
|Wake on mouse||Untested|
|Flashrom||No||Only works with vendor BIOS|
Getting ready for coreboot
Do not expect a graphics console to work
Prepare an external programmer
The EPIA-M850 has an SPI ROM. The ROM can be programmed externally via the SPI header. (TODO: Add picture and pinout of header). While the board is powered off, a programmer is generally capable of supplying enough power. An FT4232H module has been tested to work.
Make sure the programmer can read the chip. If it can't read it, it won't be able to write it in case recovery is needed.
Extract the VGA BIOS
Use bios_extract to to get the VGA BIOS from the vendor's BIOS. Put it in an easy-to-find place. Let's call it path/to/vgabios.bin.
$ make menuconfig
$ make xconfig
- Mainboard -> Select VIA->EPIA-M850
- VGA BIOS -> Select "Add a VGA BIOS image" + "VGA BIOS path and filename:" path/to/vgabios.bin
- Console -> Make sure serial console is on and turned all the way up to SPEW (in case things go south)
- System tables -> Make sure at least a PIRQ table is generated. Generating other tables does not hurt us, so they can remain enabled.
- Debugging -> Output verbose RAM init debug messages.
- For the first try, it is higly recommended to use SeaBIOS as a payload.
- Save and exit
For the time being, append the following options to the boot parameters: "acpi=off noapic 3" to the linux that will be booting this board after coreboot finishes. If you forget to do this, you will also be able to change them at the GRUB2 prompt, assuming you are using GRUB2.
Prepare a serial console
The board has a serial port in the back. How convenient! Use it.
Build and flash coreboot
Start monitoring the serial console and power on the board
If you encounter any errors, or even if you succeed and are happy, let us know.
The board features a conveniently located SPI header that can be used to program the ROM when the board is powered off. The pinout is incorrectly documented in the user manual.
|2:||GND||#CS||MOSI||? PCIRST ?|