Console and outputs: Difference between revisions
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{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! Output name | ! Output name | ||
! direction (from the target | ! direction (from the coreboot target machine point of view) | ||
! | ! Requirements | ||
! Compatibility with software loaded after coreboot, like OS and payloads | |||
|- | |- | ||
! [[Serial console]] | ! [[Serial console]] | ||
Line 10: | Line 11: | ||
* input | * input | ||
* output | * output | ||
| | |||
* An internal(not USB) serial port: | |||
** it can be on the mainboard | |||
** it can also be a PCIe OXPCIe952 card with the 0x1415 and 0xc158 vendor and device ID (respectively). | |||
** USB serial ports are not supported by coreboot yet. | |||
| | | | ||
* seabios | * seabios | ||
Line 23: | Line 29: | ||
* input? | * input? | ||
* output | * output | ||
| | |||
* An USB debug port supported by coreboot. | |||
* To find on which usb connector it goes. | |||
| | |||
* grub | |||
* linux kernel in its early initialisation (I'm not sure that it can be kept afterward, because, after the early initialisation, by default it tries to initialise the USB port normally) | |||
|- | |- | ||
! [[Spkmodem| Console trough spkmodem]] | ! [[Spkmodem| Console trough spkmodem]] | ||
Line 28: | Line 40: | ||
| | | | ||
* output only | * output only | ||
| | |||
* A working "beep" sound card at boot. | |||
* On some laptops it's necessary to tell the embedded controller to enable sound output to get it working. | |||
| | | | ||
For writting to it from the coreboot target computer: | For writting to it from the coreboot target computer: | ||
Line 39: | Line 54: | ||
| | | | ||
* output | * output | ||
* probably no input | |||
| | |||
* A ne2k compatible ethernet card on the coreboot target system. | |||
* A network between the coreboot computer and the computer receiving the logs. | |||
| | |||
For sending the logs: | |||
* the linux kernel | |||
For receiving the logs: | |||
* nc and similar networking uttilities. | |||
|- | |- | ||
! [[Cbmem console]] | ! [[Cbmem console]] | ||
Line 44: | Line 68: | ||
| | | | ||
* output only for coreboot. | * output only for coreboot. | ||
* | * output for grub. Can also print cbmem console content. | ||
* It requires the computer to be booted to retrive the logs. | * It requires the computer to be booted to retrive the logs. | ||
| | |||
* A coreboot device that supports cbmem: not all devices supports it in coreboot. | |||
| | | | ||
For writting to the buffer which is in the coreboot target computer: | For writting to the buffer which is in the coreboot target computer: | ||
Line 54: | Line 80: | ||
* grub with the cbmemc command | * grub with the cbmemc command | ||
* coreboot's userspace cbmem -c uttility | * coreboot's userspace cbmem -c uttility | ||
|- | |||
|- | |||
! [[POST card]] | |||
| | |||
* output only. | |||
| | |||
| | |||
|- | |- | ||
|} | |} | ||
* [[ | If none of the above works for your case, you might consider: | ||
* | * Trying [[Developer_Manual/Tools#Flash_emulators_.28used_to_flash_and_debug.29 | Flash emulators]] to trace the code being accessed. | ||
* [[Developer_Manual/Tools#Oscilloscope| Osciloscopes]] for hardware related lower level debuging. | |||
* [https://www.serialice.com SerialICE] if you can add support for your board serial or [[EHCI Debug Port]] in [https://www.serialice.com SerialICE] |
Revision as of 14:28, 13 March 2016
Coreboot has various possible consoles:
Output name | direction (from the coreboot target machine point of view) | Requirements | Compatibility with software loaded after coreboot, like OS and payloads |
---|---|---|---|
Serial console
(sends coreboot logs over the serial port) |
|
|
|
Console Over EHCI debug port
(sends coreboot logs over the usb debug port) |
|
|
|
Console trough spkmodem
(sends coreboot logs over the sound card) |
|
|
For writting to it from the coreboot target computer:
For reading it from a remote computer:
|
Network console
(sends coreboot logs over the network) |
|
|
For sending the logs:
For receiving the logs:
|
Cbmem console
(Ram buffer, like dmesg) |
|
|
For writting to the buffer which is in the coreboot target computer:
For reading the buffer on the coreboot target computer, after coreboot booted:
|
POST card |
|
If none of the above works for your case, you might consider:
- Trying Flash emulators to trace the code being accessed.
- Osciloscopes for hardware related lower level debuging.
- SerialICE if you can add support for your board serial or EHCI Debug Port in SerialICE