Difference between revisions of "Coreboot Options"

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This is an automatically generated list of '''coreboot compile-time options'''.
 
This is an automatically generated list of '''coreboot compile-time options'''.
  
Last update: 4.6-1891-gbb98b38b93
+
Last update: 4.7-365-gf984a05cc7
 
{| border="0" style="font-size: smaller"
 
{| border="0" style="font-size: smaller"
 
|- bgcolor="#6699dd"
 
|- bgcolor="#6699dd"
Line 86: Line 86:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| UTIL_GENPARSER || toplevel || bool || Generate SCONFIG & BLOBTOOL parser using flex and bison ||  
+
| UTIL_GENPARSER || toplevel || bool || Generate SCONFIG & BINCFG parser using flex and bison ||  
 
Enable this option if you are working on the sconfig device tree
 
Enable this option if you are working on the sconfig device tree
parser or blobtool and made changes to the .l or .y files.
+
parser or bincfg and made changes to the .l or .y files.
  
 
Otherwise, say N to use the provided pregenerated scanner/parser.
 
Otherwise, say N to use the provided pregenerated scanner/parser.
Line 203: Line 203:
  
 
If unsure, select 'N'
 
If unsure, select 'N'
 
||
 
|- bgcolor="#eeeeee"
 
| BOARD_ID_STRING || toplevel || string || Board ID ||
 
This string is placed in the 'board_id' CBFS file for indicating
 
board type.
 
 
||
 
|- bgcolor="#eeeeee"
 
| RAM_CODE_SUPPORT || toplevel || bool ||  ||
 
If enabled, coreboot discovers RAM configuration (value obtained by
 
reading board straps) and stores it in coreboot table.
 
  
 
||
 
||
Line 359: Line 347:
  
 
||
 
||
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: Debugging || || || ||
 +
|- bgcolor="#eeeeee"
 +
| DISABLE_UART_ON_TESTPADS || mainboard/intel/dcp847ske || bool || Disable UART on testpads ||
 +
Serial output requires soldering to the testpad next to
 +
NCT5577D pin 18 (txd) and gnd.
 +
 +
||
 +
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| VGA_BIOS_FILE || mainboard/intel/strago || string ||  ||  
 
| VGA_BIOS_FILE || mainboard/intel/strago || string ||  ||  
Line 438: Line 435:
 
The VGA_BIOS_ID for the C0 version of the video bios is hardcoded
 
The VGA_BIOS_ID for the C0 version of the video bios is hardcoded
 
in soc/intel/braswell/Makefile.inc as 8086,22b1
 
in soc/intel/braswell/Makefile.inc as 8086,22b1
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FMDFILE || mainboard/google/kahlee || string ||  ||
 +
The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
 +
but in some cases more complex setups are required.
 +
When an fmd is specified, it overrides the default format.
  
 
||
 
||
Line 550: Line 554:
  
 
||
 
||
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NO_POST || mainboard/purism/librem_skl || int ||  ||
 +
This platform does not have any way to see POST codes
 +
so disable them by default.
  
 
||
 
||
Line 565: Line 575:
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| NO_POST || mainboard/purism/librem13v1 || int ||  ||  
 
| NO_POST || mainboard/purism/librem13v1 || int ||  ||  
This platform does not have any way to see POST codes
 
so disable them by default.
 
 
||
 
|- bgcolor="#eeeeee"
 
| NO_POST || mainboard/purism/librem13v2 || int ||  ||
 
 
This platform does not have any way to see POST codes
 
This platform does not have any way to see POST codes
 
so disable them by default.
 
so disable them by default.
Line 624: Line 628:
  
 
||
 
||
|- bgcolor="#6699dd"
 
! align="left" | Menu: On-Chip Device Power Down Control || || || ||
 
 
|- bgcolor="#6699dd"
 
! align="left" | Menu: Watchdog Timer setting || || || ||
 
 
|- bgcolor="#6699dd"
 
! align="left" | Menu: IDE controller setting || || || ||
 
|- bgcolor="#eeeeee"
 
| IDE_STANDARD_COMPATIBLE || mainboard/dmp/vortex86ex || bool || Standard IDE Compatible ||
 
Built-in IDE controller PCI vendor/device ID is 17F3:1012, which
 
is not recognized by some OSes.
 
 
This option can change IDE controller PCI vendor/device ID to
 
other value for software compatibility.
 
 
||
 
|- bgcolor="#eeeeee"
 
| IDE_COMPATIBLE_SELECTION || mainboard/dmp/vortex86ex || hex || IDE Compatible Selection ||
 
IDE controller PCI vendor/device ID value setting.
 
 
Higher 16-bit is vendor ID, lower 16-bit is device ID.
 
 
||
 
 
|- bgcolor="#6699dd"
 
! align="left" | Menu: GPIO setting || || || ||
 
 
|- bgcolor="#6699dd"
 
! align="left" | Menu: UART setting || || || ||
 
 
|- bgcolor="#6699dd"
 
! align="left" | Menu: LPT setting || || || ||
 
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| || || (comment) || || see under vendor LiPPERT ||
 
| || || (comment) || || see under vendor LiPPERT ||
Line 775: Line 745:
  
 
||
 
||
 +
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MAINBOARD_HAS_TPM2 || toplevel || bool ||  ||
+
| CBFS_AUTOGEN_ATTRIBUTES || toplevel || bool ||  ||  
There is a TPM device installed on the mainboard, and it is
 
compliant with version 2 TCG TPM specification. Could be connected
 
over LPC, SPI or I2C.
 
 
 
||
 
 
 
|- bgcolor="#eeeeee"
 
| CBFS_AUTOGEN_ATTRIBUTES || toplevel || bool ||  ||  
 
 
If this option is selected, every file in cbfs which has a constraint
 
If this option is selected, every file in cbfs which has a constraint
 
regarding position or alignment will get an additional file attribute
 
regarding position or alignment will get an additional file attribute
Line 877: Line 840:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_FSP_BAYTRAIL || soc/intel/fsp_baytrail || bool ||  ||  
+
| SOC_INTEL_APOLLOLAKE || soc/intel/apollolake || bool ||  ||  
Bay Trail I part support using the Intel FSP.
+
Intel Apollolake support
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SMM_TSEG_SIZE || soc/intel/fsp_baytrail || hex ||  ||  
+
| SOC_INTEL_GLK || soc/intel/apollolake || bool ||  ||  
This is set by the FSP
+
Intel GLK support
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VGA_BIOS_ID || soc/intel/fsp_baytrail || string ||  ||  
+
| TPM_ON_FAST_SPI || soc/intel/apollolake || bool ||  ||  
This is the default PCI ID for the Bay Trail graphics
+
TPM part is conntected on Fast SPI interface, but the LPC MMIO
devices.  This string names the vbios ROM in cbfs.
+
TPM transactions are decoded and serialized over the SPI interface.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_BUILTIN_COM1 || soc/intel/fsp_baytrail || bool || Enable built-in legacy Serial Port ||  
+
| PCR_BASE_ADDRESS || soc/intel/apollolake || hex || ||  
The Baytrail SOC has one legacy serial port. Choose this option to
+
This option allows you to select MMIO Base Address of sideband bus.
configure the pads and enable it. This serial port can be used for
 
the debug console.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_FILE || soc/intel/fsp_baytrail/fsp || string ||  ||  
+
| DCACHE_RAM_SIZE || soc/intel/apollolake || hex ||  ||  
The path and filename of the Intel FSP binary for this platform.
+
The size of the cache-as-ram region required during bootblock
 +
and/or romstage.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_LOC || soc/intel/fsp_baytrail/fsp || hex ||  ||  
+
| DCACHE_BSP_STACK_SIZE || soc/intel/apollolake || hex ||  ||  
The location in CBFS that the FSP is located. This must match the
+
The amount of anticipated stack usage in CAR by bootblock and
value that is set in the FSP binary.  If the FSP needs to be moved,
+
other stages.
rebase the FSP with Intel's BCT (tool).
 
 
 
The Bay Trail FSP is built with a preferred base address of
 
0xFFFC0000.
 
  
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| ROMSTAGE_ADDR || soc/intel/apollolake || hex ||  ||
 +
The base address (in CAR) where romstage should be linked
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HAVE_CMC || soc/intel/sch || bool || Add a CMC state machine binary ||  
+
| VERSTAGE_ADDR || soc/intel/apollolake || hex || ||  
Select this option to add a CMC state machine binary to
+
The base address (in CAR) where verstage should be linked
the resulting coreboot image.
 
 
 
Note: Without this binary coreboot will not work
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CMC_FILE || soc/intel/sch || string || Intel CMC path and filename ||  
+
| FSP_M_ADDR || soc/intel/apollolake || hex || ||  
The path and filename of the file to use as CMC state machine
+
The address FSP-M will be relocated to during build time
binary.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_CANNONLAKE || soc/intel/cannonlake || bool || ||  
+
| NEED_LBP2 || soc/intel/apollolake || bool || Write contents for logical boot partition 2. ||  
Intel Cannonlake support
+
Write the contents from a file into the logical boot partition 2
 +
region defined by LBP2_FMAP_NAME.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| UART_FOR_CONSOLE || soc/intel/cannonlake || int || Index for LPSS UART port to use for console ||  
+
| LBP2_FMAP_NAME || soc/intel/apollolake || string || Name of FMAP region to put logical boot partition 2 ||  
Index for LPSS UART port to use for console:
+
Name of FMAP region to write logical boot partition 2 data.
0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DCACHE_RAM_SIZE || soc/intel/cannonlake || int || ||  
+
| LBP2_FILE_NAME || soc/intel/apollolake || string || Path of file to write to logical boot partition 2 region ||  
The size of the cache-as-ram region required during bootblock
+
Name of file to store in the logical boot partition 2 region.
and/or romstage.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DCACHE_BSP_STACK_SIZE || soc/intel/cannonlake || hex || ||  
+
| NEED_IFWI || soc/intel/apollolake || bool || Write content into IFWI region ||  
The amount of anticipated stack usage in CAR by bootblock and
+
Write the content from a file into IFWI region defined by
other stages.
+
IFWI_FMAP_NAME.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PCR_BASE_ADDRESS || soc/intel/cannonlake || hex || ||  
+
| IFWI_FMAP_NAME || soc/intel/apollolake || string || Name of FMAP region to pull IFWI into ||  
This option allows you to select MMIO Base Address of sideband bus.
+
Name of FMAP region to write IFWI.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_BRASWELL || soc/intel/braswell || bool || ||  
+
| IFWI_FILE_NAME || soc/intel/apollolake || string || Path of file to write to IFWI region ||  
Braswell M/D part support.
+
Name of file to store in the IFWI region.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DCACHE_RAM_SIZE || soc/intel/braswell || hex ||  ||  
+
| NHLT_DMIC_1CH_16B || soc/intel/apollolake || bool ||  ||  
The size of the cache-as-ram region required during bootblock
+
Include DSP firmware settings for 1 channel 16B DMIC array.
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
 
must add up to a power of 2.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| RESET_ON_INVALID_RAMSTAGE_CACHE || soc/intel/braswell || bool || Reset the system on S3 wake when ramstage cache invalid. ||  
+
| NHLT_DMIC_2CH_16B || soc/intel/apollolake || bool || ||  
The haswell romstage code caches the loaded ramstage program
+
Include DSP firmware settings for 2 channel 16B DMIC array.
in SMM space. On S3 wake the romstage will copy over a fresh
 
ramstage that was cached in the SMM space. This option determines
 
the action to take when the ramstage cache is invalid. If selected
 
the system will reset otherwise the ramstage will be reloaded from
 
cbfs.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_BUILTIN_COM1 || soc/intel/braswell || bool || Enable builtin COM1 Serial Port ||  
+
| NHLT_DMIC_4CH_16B || soc/intel/apollolake || bool || ||  
The PMC has a legacy COM1 serial port. Choose this option to
+
Include DSP firmware settings for 4 channel 16B DMIC array.
configure the pads and enable it. This serial port can be used for
 
the debug console.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_APOLLOLAKE || soc/intel/apollolake || bool ||  ||  
+
| NHLT_MAX98357 || soc/intel/apollolake || bool ||  ||  
Intel Apollolake support
+
Include DSP firmware settings for headset codec.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_GLK || soc/intel/apollolake || bool ||  ||  
+
| NHLT_DA7219 || soc/intel/apollolake || bool ||  ||  
Intel GLK support
+
Include DSP firmware settings for headset codec.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| TPM_ON_FAST_SPI || soc/intel/apollolake || bool || ||  
+
| NHLT_DA7219 || soc/intel/apollolake || bool || Cache-as-ram implementation ||  
TPM part is conntected on Fast SPI interface, but the LPC MMIO
+
This option allows you to select how cache-as-ram (CAR) is set up.
TPM transactions are decoded and serialized over the SPI interface.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PCR_BASE_ADDRESS || soc/intel/apollolake || hex || ||  
+
| CAR_NEM || soc/intel/apollolake || bool || Non-evict mode ||  
This option allows you to select MMIO Base Address of sideband bus.
+
Traditionally, CAR is set up by using Non-Evict mode. This method
 +
does not allow CAR and cache to co-exist, because cache fills are
 +
block in NEM mode.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DCACHE_RAM_SIZE || soc/intel/apollolake || hex || ||  
+
| CAR_CQOS || soc/intel/apollolake || bool || Cache Quality of Service ||  
The size of the cache-as-ram region required during bootblock
+
Cache Quality of Service allows more fine-grained control of cache
and/or romstage.
+
usage. As result, it is possible to set up portion of L2 cache for
 +
CAR and use remainder for actual caching.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DCACHE_BSP_STACK_SIZE || soc/intel/apollolake || hex || ||  
+
| USE_APOLLOLAKE_FSP_CAR || soc/intel/apollolake || bool || Use FSP CAR ||  
The amount of anticipated stack usage in CAR by bootblock and
+
Use FSP APIs to initialize & tear down the Cache-As-Ram.
other stages.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ROMSTAGE_ADDR || soc/intel/apollolake || hex ||  ||  
+
| APL_SKIP_SET_POWER_LIMITS || soc/intel/apollolake || bool ||  ||  
The base address (in CAR) where romstage should be linked
+
Some Apollo Lake mainboards do not need the Running Average Power
 +
Limits (RAPL) algorithm for a constant power management.
 +
Set this config option to skip the RAPL configuration.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VERSTAGE_ADDR || soc/intel/apollolake || hex ||  ||  
+
| SOC_ESPI || soc/intel/apollolake || bool ||  ||  
The base address (in CAR) where verstage should be linked
+
Use eSPI bus instead of LPC
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_M_ADDR || soc/intel/apollolake || hex ||  ||  
+
| SOC_INTEL_BAYTRAIL || soc/intel/baytrail || bool ||  ||  
The address FSP-M will be relocated to during build time
+
Bay Trail M/D part support.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NEED_LBP2 || soc/intel/apollolake || bool || Write contents for logical boot partition 2. ||  
+
| HAVE_MRC || soc/intel/baytrail || bool || Add a Memory Reference Code binary ||  
Write the contents from a file into the logical boot partition 2
+
Select this option to add a blob containing
region defined by LBP2_FMAP_NAME.
+
memory reference code.
 +
Note: Without this binary coreboot will not work
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| LBP2_FMAP_NAME || soc/intel/apollolake || string || Name of FMAP region to put logical boot partition 2 ||  
+
| MRC_FILE || soc/intel/baytrail || string || Intel memory refeference code path and filename ||  
Name of FMAP region to write logical boot partition 2 data.
+
The path and filename of the file to use as System Agent
 +
binary. Note that this points to the sandybridge binary file
 +
which is will not work, but it serves its purpose to do builds.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| LBP2_FILE_NAME || soc/intel/apollolake || string || Path of file to write to logical boot partition 2 region ||  
+
| DCACHE_RAM_SIZE || soc/intel/baytrail || hex || ||  
Name of file to store in the logical boot partition 2 region.
+
The size of the cache-as-ram region required during bootblock
 +
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
 +
must add up to a power of 2.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NEED_IFWI || soc/intel/apollolake || bool || Write content into IFWI region ||  
+
| DCACHE_RAM_MRC_VAR_SIZE || soc/intel/baytrail || hex || ||  
Write the content from a file into IFWI region defined by
+
The amount of cache-as-ram region required by the reference code.
IFWI_FMAP_NAME.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| IFWI_FMAP_NAME || soc/intel/apollolake || string || Name of FMAP region to pull IFWI into ||  
+
| RESET_ON_INVALID_RAMSTAGE_CACHE || soc/intel/baytrail || bool || Reset the system on S3 wake when ramstage cache invalid. ||  
Name of FMAP region to write IFWI.
+
The baytrail romstage code caches the loaded ramstage program
 +
in SMM space. On S3 wake the romstage will copy over a fresh
 +
ramstage that was cached in the SMM space. This option determines
 +
the action to take when the ramstage cache is invalid. If selected
 +
the system will reset otherwise the ramstage will be reloaded from
 +
cbfs.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| IFWI_FILE_NAME || soc/intel/apollolake || string || Path of file to write to IFWI region ||  
+
| ENABLE_BUILTIN_COM1 || soc/intel/baytrail || bool || Enable builtin COM1 Serial Port ||  
Name of file to store in the IFWI region.
+
The PMC has a legacy COM1 serial port. Choose this option to
 +
configure the pads and enable it. This serial port can be used for
 +
the debug console.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NHLT_DMIC_1CH_16B || soc/intel/apollolake || bool || ||  
+
| HAVE_REFCODE_BLOB || soc/intel/baytrail || bool || An external reference code blob should be put into cbfs. ||  
Include DSP firmware settings for 1 channel 16B DMIC array.
+
The reference code blob will be placed into cbfs.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NHLT_DMIC_2CH_16B || soc/intel/apollolake || bool || ||  
+
| REFCODE_BLOB_FILE || soc/intel/baytrail || string || Path and filename to reference code blob. ||  
Include DSP firmware settings for 2 channel 16B DMIC array.
+
The path and filename to the file to be added to cbfs.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NHLT_DMIC_4CH_16B || soc/intel/apollolake || bool ||  ||  
+
| SOC_INTEL_BRASWELL || soc/intel/braswell || bool ||  ||  
Include DSP firmware settings for 4 channel 16B DMIC array.
+
Braswell M/D part support.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NHLT_MAX98357 || soc/intel/apollolake || bool ||  ||  
+
| DCACHE_RAM_SIZE || soc/intel/braswell || hex ||  ||  
Include DSP firmware settings for headset codec.
+
The size of the cache-as-ram region required during bootblock
 +
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
 +
must add up to a power of 2.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NHLT_DA7219 || soc/intel/apollolake || bool || ||  
+
| RESET_ON_INVALID_RAMSTAGE_CACHE || soc/intel/braswell || bool || Reset the system on S3 wake when ramstage cache invalid. ||  
Include DSP firmware settings for headset codec.
+
The haswell romstage code caches the loaded ramstage program
 
+
in SMM space. On S3 wake the romstage will copy over a fresh
 +
ramstage that was cached in the SMM space. This option determines
 +
the action to take when the ramstage cache is invalid. If selected
 +
the system will reset otherwise the ramstage will be reloaded from
 +
cbfs.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NHLT_DA7219 || soc/intel/apollolake || bool || Cache-as-ram implementation ||  
+
| ENABLE_BUILTIN_COM1 || soc/intel/braswell || bool || Enable builtin COM1 Serial Port ||  
This option allows you to select how cache-as-ram (CAR) is set up.
+
The PMC has a legacy COM1 serial port. Choose this option to
 +
configure the pads and enable it. This serial port can be used for
 +
the debug console.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CAR_NEM || soc/intel/apollolake || bool || Non-evict mode ||  
+
| SOC_INTEL_BROADWELL || soc/intel/broadwell || bool || ||  
Traditionally, CAR is set up by using Non-Evict mode. This method
+
Intel Broadwell and Haswell ULT support.
does not allow CAR and cache to co-exist, because cache fills are
 
block in NEM mode.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CAR_CQOS || soc/intel/apollolake || bool || Cache Quality of Service ||  
+
| DCACHE_RAM_SIZE || soc/intel/broadwell || hex || ||  
Cache Quality of Service allows more fine-grained control of cache
+
The size of the cache-as-ram region required during bootblock
usage. As result, it is possible to set up portion of L2 cache for
+
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
CAR and use remainder for actual caching.
+
must add up to a power of 2.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| USE_APOLLOLAKE_FSP_CAR || soc/intel/apollolake || bool || Use FSP CAR ||  
+
| DCACHE_RAM_MRC_VAR_SIZE || soc/intel/broadwell || hex || ||  
Use FSP APIs to initialize & tear down the Cache-As-Ram.
+
The amount of cache-as-ram region required by the reference code.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| USE_APOLLOLAKE_FSP_CAR || soc/intel/apollolake || bool || MPINIT code implementation ||  
+
| HAVE_MRC || soc/intel/broadwell || bool || Add a Memory Reference Code binary ||  
This option allows you to select MP Init Code path either
+
Select this option to add a Memory Reference Code binary to
from Intel Common Code implementation, or from SOC files.
+
the resulting coreboot image.
 +
 
 +
Note: Without this binary coreboot will not work
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NO_COMMON_MPINIT || soc/intel/apollolake || bool || Not using Common MP Init code ||  
+
| MRC_FILE || soc/intel/broadwell || string || Intel Memory Reference Code path and filename ||  
Common code MP Init path is not used.
+
The filename of the file to use as Memory Reference Code binary.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COMMON_MPINIT || soc/intel/apollolake || bool || Using Common MP Init code ||  
+
| PRE_GRAPHICS_DELAY || soc/intel/broadwell || int || Graphics initialization delay in ms ||  
Common code MP Init path is used.
+
On some systems, coreboot boots so fast that connected monitors
 +
(mostly TVs) won't be able to wake up fast enough to talk to the
 +
VBIOS. On those systems we need to wait for a bit before executing
 +
the VBIOS.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| APL_SKIP_SET_POWER_LIMITS || soc/intel/apollolake || bool || ||  
+
| RESET_ON_INVALID_RAMSTAGE_CACHE || soc/intel/broadwell || bool || Reset the system on S3 wake when ramstage cache invalid. ||  
Some Apollo Lake mainboards do not need the Running Average Power
+
The romstage code caches the loaded ramstage program in SMM space.
Limits (RAPL) algorithm for a constant power management.
+
On S3 wake the romstage will copy over a fresh ramstage that was
Set this config option to skip the RAPL configuration.
+
cached in the SMM space. This option determines the action to take
 +
when the ramstage cache is invalid. If selected the system will
 +
reset otherwise the ramstage will be reloaded from cbfs.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_DENVERTON_NS || soc/intel/denverton_ns || bool ||  ||  
+
| SERIRQ_CONTINUOUS_MODE || soc/intel/broadwell || bool ||  ||  
Intel Denverton-NS SoC support
+
If you set this option to y, the serial IRQ machine will be
 +
operated in continuous mode.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_T_ADDR || soc/intel/denverton_ns || hex || Intel FSP-T (temp ram init) binary location ||  
+
| HAVE_REFCODE_BLOB || soc/intel/broadwell || bool || An external reference code blob should be put into cbfs. ||  
The memory location of the Intel FSP-T binary for this platform.
+
The reference code blob will be placed into cbfs.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_M_ADDR || soc/intel/denverton_ns || hex || Intel FSP-M (memory init) binary location ||  
+
| REFCODE_BLOB_FILE || soc/intel/broadwell || string || Path and filename to reference code blob. ||  
The memory location of the Intel FSP-M binary for this platform.
+
The path and filename to the file to be added to cbfs.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_S_ADDR || soc/intel/denverton_ns || hex || Intel FSP-S (silicon init) binary location ||  
+
| SOC_INTEL_CANNONLAKE || soc/intel/cannonlake || bool || ||  
The memory location of the Intel FSP-S binary for this platform.
+
Intel Cannonlake support
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| IQAT_MEMORY_REGION_SIZE || soc/intel/denverton_ns || hex || ||  
+
| UART_FOR_CONSOLE || soc/intel/cannonlake || int || Index for LPSS UART port to use for console ||  
Do not change this value
+
Index for LPSS UART port to use for console:
 +
0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NON_LEGACY_UART_MODE || soc/intel/denverton_ns || bool || Non Legacy Mode ||  
+
| DCACHE_RAM_SIZE || soc/intel/cannonlake || int || ||  
Disable legacy UART mode
+
The size of the cache-as-ram region required during bootblock
 +
and/or romstage.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| LEGACY_UART_MODE || soc/intel/denverton_ns || bool || Legacy Mode ||  
+
| DCACHE_BSP_STACK_SIZE || soc/intel/cannonlake || hex || ||  
Enable legacy UART mode
+
The amount of anticipated stack usage in CAR by bootblock and
 +
other stages.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DENVERTON_NS_CAR_NEM_ENHANCED || soc/intel/denverton_ns || bool || Enhanced Non-evict mode ||  
+
| NHLT_DMIC_1CH_16B || soc/intel/cannonlake || bool || ||  
A current limitation of NEM (Non-Evict mode) is that code and data sizes
+
Include DSP firmware settings for 1 channel 16B DMIC array.
are derived from the requirement to not write out any modified cache line.
 
With NEM, if there is no physical memory behind the cached area,
 
the modified data will be lost and NEM results will be inconsistent.
 
ENHANCED NEM guarantees that modified data is always
 
kept in cache while clean data is replaced.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_BAYTRAIL || soc/intel/baytrail || bool ||  ||  
+
| NHLT_DMIC_2CH_16B || soc/intel/cannonlake || bool ||  ||  
Bay Trail M/D part support.
+
Include DSP firmware settings for 2 channel 16B DMIC array.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HAVE_MRC || soc/intel/baytrail || bool || Add a Memory Reference Code binary ||  
+
| NHLT_DMIC_4CH_16B || soc/intel/cannonlake || bool || ||  
Select this option to add a blob containing
+
Include DSP firmware settings for 4 channel 16B DMIC array.
memory reference code.
 
Note: Without this binary coreboot will not work
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MRC_FILE || soc/intel/baytrail || string || Intel memory refeference code path and filename ||  
+
| NHLT_MAX98357 || soc/intel/cannonlake || bool || ||  
The path and filename of the file to use as System Agent
+
Include DSP firmware settings for headset codec.
binary. Note that this points to the sandybridge binary file
+
 
which is will not work, but it serves its purpose to do builds.
+
||
 +
|- bgcolor="#eeeeee"
 +
| NHLT_MAX98373 || soc/intel/cannonlake || bool ||  ||
 +
Include DSP firmware settings for headset codec.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DCACHE_RAM_SIZE || soc/intel/baytrail || hex ||  ||  
+
| NHLT_DA7219 || soc/intel/cannonlake || bool ||  ||  
The size of the cache-as-ram region required during bootblock
+
Include DSP firmware settings for headset codec.
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
 
must add up to a power of 2.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DCACHE_RAM_MRC_VAR_SIZE || soc/intel/baytrail || hex ||  ||  
+
| PCR_BASE_ADDRESS || soc/intel/cannonlake || hex ||  ||  
The amount of cache-as-ram region required by the reference code.
+
This option allows you to select MMIO Base Address of sideband bus.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| RESET_ON_INVALID_RAMSTAGE_CACHE || soc/intel/baytrail || bool || Reset the system on S3 wake when ramstage cache invalid. ||  
+
| STACK_SIZE || soc/intel/cannonlake || hex || Cache-as-ram implementation ||  
The baytrail romstage code caches the loaded ramstage program
+
This option allows you to select how cache-as-ram (CAR) is set up.
in SMM space. On S3 wake the romstage will copy over a fresh
 
ramstage that was cached in the SMM space. This option determines
 
the action to take when the ramstage cache is invalid. If selected
 
the system will reset otherwise the ramstage will be reloaded from
 
cbfs.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_BUILTIN_COM1 || soc/intel/baytrail || bool || Enable builtin COM1 Serial Port ||  
+
| USE_CANNONLAKE_CAR_NEM_ENHANCED || soc/intel/cannonlake || bool || Enhanced Non-evict mode ||  
The PMC has a legacy COM1 serial port. Choose this option to
+
A current limitation of NEM (Non-Evict mode) is that code and data
configure the pads and enable it. This serial port can be used for
+
sizes are derived from the requirement to not write out any modified
the debug console.
+
cache line. With NEM, if there is no physical memory behind the
 +
cached area, the modified data will be lost and NEM results will be
 +
inconsistent. ENHANCED NEM guarantees that modified data is always
 +
kept in cache while clean data is replaced.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HAVE_REFCODE_BLOB || soc/intel/baytrail || bool || An external reference code blob should be put into cbfs. ||  
+
| USE_CANNONLAKE_FSP_CAR || soc/intel/cannonlake || bool || Use FSP CAR ||  
The reference code blob will be placed into cbfs.
+
Use FSP APIs to initialize and tear down the Cache-As-Ram.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| REFCODE_BLOB_FILE || soc/intel/baytrail || string || Path and filename to reference code blob. ||  
+
| SOC_INTEL_DENVERTON_NS || soc/intel/denverton_ns || bool || ||  
The path and filename to the file to be added to cbfs.
+
Intel Denverton-NS SoC support
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_QUARK || soc/intel/quark || bool || ||  
+
| FSP_T_ADDR || soc/intel/denverton_ns || hex || Intel FSP-T (temp ram init) binary location ||  
Intel Quark support
+
The memory location of the Intel FSP-T binary for this platform.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_BUILTIN_HSUART0 || soc/intel/quark || bool || Enable built-in HSUART0 ||  
+
| FSP_M_ADDR || soc/intel/denverton_ns || hex || Intel FSP-M (memory init) binary location ||  
The Quark SoC has two HSUART. Choose this option to configure the pads
+
The memory location of the Intel FSP-M binary for this platform.
and enable HSUART0, which can be used for the debug console.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_BUILTIN_HSUART1 || soc/intel/quark || bool || Enable built-in HSUART1 ||  
+
| FSP_S_ADDR || soc/intel/denverton_ns || hex || Intel FSP-S (silicon init) binary location ||  
The Quark SoC has two HSUART. Choose this option to configure the pads
+
The memory location of the Intel FSP-S binary for this platform.
and enable HSUART1, which can be used for the debug console.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| TTYS0_BASE || soc/intel/quark || hex || HSUART Base Address ||  
+
| IQAT_MEMORY_REGION_SIZE || soc/intel/denverton_ns || hex || ||  
Memory mapped MMIO of HSUART.
+
Do not change this value
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_DEBUG_LED || soc/intel/quark || bool || ||  
+
| NON_LEGACY_UART_MODE || soc/intel/denverton_ns || bool || Non Legacy Mode ||  
Enable the use of the SD LED for early debugging before serial output
+
Disable legacy UART mode
is available.  Setting this LED indicates that control has reached the
 
desired check point.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_DEBUG_LED_ESRAM || soc/intel/quark || bool || SD LED indicates ESRAM initialized ||  
+
| LEGACY_UART_MODE || soc/intel/denverton_ns || bool || Legacy Mode ||  
Indicate that ESRAM has been successfully initialized. If the SD LED
+
Enable legacy UART mode
does not light then the ESRAM initialization needs to be debugged.
+
||
 +
|- bgcolor="#eeeeee"
 +
| DENVERTON_NS_CAR_NEM_ENHANCED || soc/intel/denverton_ns || bool || Enhanced Non-evict mode ||
 +
A current limitation of NEM (Non-Evict mode) is that code and data sizes
 +
are derived from the requirement to not write out any modified cache line.
 +
With NEM, if there is no physical memory behind the cached area,
 +
the modified data will be lost and NEM results will be inconsistent.
 +
ENHANCED NEM guarantees that modified data is always
 +
kept in cache while clean data is replaced.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_DEBUG_LED_FINDFSP || soc/intel/quark || bool || SD LED indicates fsp.bin file was found ||  
+
| SOC_INTEL_FSP_BAYTRAIL || soc/intel/fsp_baytrail || bool || ||  
Indicate that fsp.bin was found.  If the SD LED does not light then
+
Bay Trail I part support using the Intel FSP.
the code between ESRAM initialization through find_fsp needs to
 
debugged.  Start by verifying that the correct fsp.bin is in the
 
image.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY || soc/intel/quark || bool || SD LED indicates bootblock.c successfully entered ||  
+
| SMM_TSEG_SIZE || soc/intel/fsp_baytrail || hex || ||  
Indicate that bootblock_c_entry was entered.  If the SD LED does not
+
This is set by the FSP
light then debug the code between ESRAM and bootblock_c_entry.  For
 
FSP 1.1, use ENABLE_DEBUG_LED_FINDFSP to split this code.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY || soc/intel/quark || bool || SD LED indicates bootblock_soc_early_init successfully entered ||  
+
| VGA_BIOS_ID || soc/intel/fsp_baytrail || string || ||  
Indicate that bootblock_soc_early_init was enteredIf the SD LED
+
This is the default PCI ID for the Bay Trail graphics
does not light then debug the code in bootblock_main_with_timestamp.
+
devicesThis string names the vbios ROM in cbfs.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_DEBUG_LED_SOC_EARLY_INIT_EXIT || soc/intel/quark || bool || SD LED indicates bootblock_soc_early_init successfully exited ||  
+
| ENABLE_BUILTIN_COM1 || soc/intel/fsp_baytrail || bool || Enable built-in legacy Serial Port ||  
Indicate that bootblock_soc_early_init exited. If the SD LED does not
+
The Baytrail SOC has one legacy serial port. Choose this option to
light then debug the scripts in bootblock_soc_early_init.
+
configure the pads and enable it. This serial port can be used for
 +
the debug console.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_DEBUG_LED_SOC_INIT_ENTRY || soc/intel/quark || bool || SD LED indicates bootblock_soc_init successfully entered ||  
+
| FSP_FILE || soc/intel/fsp_baytrail/fsp || string || ||  
Indicate that bootblock_soc_init was entered.  If the SD LED does not
+
The path and filename of the Intel FSP binary for this platform.
light then debug the code in bootblock_mainboard_early_init and
 
console_init.  If the SD LED does light but there is no serial then
 
debug the serial port configuration and initialization.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DISPLAY_ESRAM_LAYOUT || soc/intel/quark || bool || Display ESRAM layout ||  
+
| FSP_LOC || soc/intel/fsp_baytrail/fsp || hex || ||  
Select this option to display coreboot's use of ESRAM.
+
The location in CBFS that the FSP is located. This must match the
 +
value that is set in the FSP binary.  If the FSP needs to be moved,
 +
rebase the FSP with Intel's BCT (tool).
 +
 
 +
The Bay Trail FSP is built with a preferred base address of
 +
0xFFFC0000.
 +
 
 +
||
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CBFS_SIZE || soc/intel/quark || hex ||  ||  
+
| SOC_INTEL_FSP_BROADWELL_DE || soc/intel/fsp_broadwell_de || bool ||  ||  
Specify the size of the coreboot file system in the read-only (recovery)
+
Broadwell-DE support using the Intel FSP.
portion of the flash part. On Quark systems the firmware image stores
 
more than just coreboot, including:
 
- The chipset microcode (RMU) binary file located at 0xFFF00000
 
- Intel Trusted Execution Engine firmware
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ADD_FSP_RAW_BIN || soc/intel/quark || bool || Add the Intel FSP binary to the flash image without relocation ||  
+
| INTEGRATED_UART || soc/intel/fsp_broadwell_de || bool || Integrated UART ports ||  
Select this option to add an Intel FSP binary to
+
Use Broadwell-DE Integrated UART ports @3F8h and 2F8h.
the resulting coreboot image.
 
  
Note: Without this binary, coreboot builds relying on the FSP
+
||
will not boot
+
|- bgcolor="#eeeeee"
 +
| SERIRQ_CONTINUOUS_MODE || soc/intel/fsp_broadwell_de || bool ||  ||
 +
If you set this option to y, the serial IRQ machine will be
 +
operated in continuous mode.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_FILE || soc/intel/quark || string || Intel FSP binary path and filename ||  
+
| FSP_FILE || soc/intel/fsp_broadwell_de/fsp || string || ||  
 
The path and filename of the Intel FSP binary for this platform.
 
The path and filename of the Intel FSP binary for this platform.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_LOC || soc/intel/quark || hex ||  ||  
+
| FSP_LOC || soc/intel/fsp_broadwell_de/fsp || hex ||  ||  
 
The location in CBFS that the FSP is located. This must match the
 
The location in CBFS that the FSP is located. This must match the
 
value that is set in the FSP binary.  If the FSP needs to be moved,
 
value that is set in the FSP binary.  If the FSP needs to be moved,
 
rebase the FSP with Intel's BCT (tool).
 
rebase the FSP with Intel's BCT (tool).
 +
 +
The Broadwell-DE FSP is built with a preferred base address of
 +
0xffeb0000.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_ESRAM_LOC || soc/intel/quark || hex || ||  
+
| FSP_MEMORY_DOWN || soc/intel/fsp_broadwell_de/fsp || bool || Enable Memory Down ||  
The location in ESRAM where a copy of the FSP binary is placed.
+
Load SPD data from ROM instead of trying to read from SMBus.
  
||
+
If the platform has DIMM sockets, say N. If memory is down, say Y and
|- bgcolor="#eeeeee"
+
supply the appropriate SPD data for each Channel/DIMM.
| RELOCATE_FSP_INTO_DRAM || soc/intel/quark || bool || Relocate FSP into DRAM ||
 
Relocate the FSP binary into DRAM before the call to SiliconInit.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ADD_RMU_FILE || soc/intel/quark || bool || Should the RMU binary be added to the flash image? ||  
+
| FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT || soc/intel/fsp_broadwell_de/fsp || bool || Channel 0, DIMM 0 Present ||  
The RMU file is required to get the chip out of reset.
+
Select Y if Channel 0, DIMM 0 is present.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| RMU_FILE || soc/intel/quark || string || ||  
+
| FSP_MEMORY_DOWN_CH0DIMM0_SPD_FILE || soc/intel/fsp_broadwell_de/fsp || string || Channel 0, DIMM 0 SPD File ||  
The path and filename of the Intel Quark RMU binary.
+
Path to the file which contains the SPD data for Channel 0, DIMM 0.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| RMU_LOC || soc/intel/quark || hex || ||  
+
| FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT || soc/intel/fsp_broadwell_de/fsp || bool || Channel 0, DIMM 1 Present ||  
The location in CBFS that the RMU is located. It must match the
+
Select Y if Channel 0, DIMM 1 is present.
strap-determined base address.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| STORAGE_TEST || soc/intel/quark || bool || Test SD/MMC/eMMC card or device access ||  
+
| FSP_MEMORY_DOWN_CH0DIMM1_SPD_FILE || soc/intel/fsp_broadwell_de/fsp || string || Channel 0, DIMM 1 SPD File ||  
Read block 0 from each parition of the storage device.  User
+
Path to the file which contains the SPD data for Channel 0, DIMM 1.
must also enable one or both of COMMONLIB_STORAGE_SD or
 
COMMONLIB_STORAGE_MMC.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| I2C_DEBUG || soc/intel/quark || bool || Enable I2C debugging ||  
+
| FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT || soc/intel/fsp_broadwell_de/fsp || bool || Channel 1, DIMM 0 Present ||  
Display the I2C segments and controller errors
+
Select Y if Channel 1, DIMM 0 is present.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON || soc/intel/common || bool || ||  
+
| FSP_MEMORY_DOWN_CH1DIMM0_SPD_FILE || soc/intel/fsp_broadwell_de/fsp || string || Channel 1, DIMM 0 SPD File ||  
common code for Intel SOCs
+
Path to the file which contains the SPD data for Channel 1, DIMM 0.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || Intel SoC Common Code ||
+
| FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT || soc/intel/fsp_broadwell_de/fsp || bool || Channel 1, DIMM 1 Present ||  
|- bgcolor="#eeeeee"
+
Select Y if Channel 1, DIMM 1 is present.
| SOC_INTEL_COMMON_BLOCK || soc/intel/common/block || bool || ||  
 
SoC driver for intel common IP code
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || Intel SoC Common IP Code ||
+
| FSP_MEMORY_DOWN_CH1DIMM1_SPD_FILE || soc/intel/fsp_broadwell_de/fsp || string || Channel 1, DIMM 1 SPD File ||  
|- bgcolor="#eeeeee"
+
Path to the file which contains the SPD data for Channel 1, DIMM 1.
| SOC_INTEL_COMMON_BLOCK_TIMER || soc/intel/common/block/timer || bool || ||  
 
Intel Processor common TIMER support
 
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_XDCI || soc/intel/common/block/xdci || bool || ||  
+
| FSP_HYPERTHREADING || soc/intel/fsp_broadwell_de/fsp || bool || Enable Hyper-Threading ||  
Intel Processor common XDCI support
+
Enable Intel(r) Hyper-Threading Technology for the Broadwell-DE SoC.
  
 
||
 
||
 +
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_SCS || soc/intel/common/block/scs || bool ||  ||  
+
| SOC_INTEL_QUARK || soc/intel/quark || bool ||  ||  
Intel Processor common storage and communication subsystem support
+
Intel Quark support
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_SATA || soc/intel/common/block/sata || bool || ||  
+
| ENABLE_BUILTIN_HSUART0 || soc/intel/quark || bool || Enable built-in HSUART0 ||  
Intel Processor common SATA support
+
The Quark SoC has two HSUART. Choose this option to configure the pads
 +
and enable HSUART0, which can be used for the debug console.
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_LPC || soc/intel/common/block/lpc || bool || ||  
+
| ENABLE_BUILTIN_HSUART1 || soc/intel/quark || bool || Enable built-in HSUART1 ||  
Use common LPC code for platform. Only soc specific code needs to
+
The Quark SoC has two HSUART. Choose this option to configure the pads
be implemented as per requirement.
+
and enable HSUART1, which can be used for the debug console.
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_SMM || soc/intel/common/block/smm || bool || ||  
+
| TTYS0_BASE || soc/intel/quark || hex || HSUART Base Address ||  
Intel Processor common SMM support
+
Memory mapped MMIO of HSUART.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP || soc/intel/common/block/smm || bool ||  ||  
+
| ENABLE_DEBUG_LED || soc/intel/quark || bool ||  ||  
Intel Processor trap flag if it is supported
+
Enable the use of the SD LED for early debugging before serial output
 +
is available.  Setting this LED indicates that control has reached the
 +
desired check point.
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_SA || soc/intel/common/block/systemagent || bool || ||  
+
| ENABLE_DEBUG_LED_ESRAM || soc/intel/quark || bool || SD LED indicates ESRAM initialized ||  
Intel Processor common System Agent support
+
Indicate that ESRAM has been successfully initialized.  If the SD LED
 +
does not light then the ESRAM initialization needs to be debugged.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SA_PCIEX_LENGTH || soc/intel/common/block/systemagent || hex || ||  
+
| ENABLE_DEBUG_LED_FINDFSP || soc/intel/quark || bool || SD LED indicates fsp.bin file was found ||  
This option allows you to select length of PCIEX region.
+
Indicate that fsp.bin was found.  If the SD LED does not light then
 +
the code between ESRAM initialization through find_fsp needs to
 +
debugged.  Start by verifying that the correct fsp.bin is in the
 +
image.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SA_ENABLE_IMR || soc/intel/common/block/systemagent || bool || ||  
+
| ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY || soc/intel/quark || bool || SD LED indicates bootblock.c successfully entered ||  
This option allows you to add the isolated memory ranges (IMRs).
+
Indicate that bootblock_c_entry was entered.  If the SD LED does not
 +
light then debug the code between ESRAM and bootblock_c_entry.  For
 +
FSP 1.1, use ENABLE_DEBUG_LED_FINDFSP to split this code.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SA_ENABLE_DPR || soc/intel/common/block/systemagent || bool || ||  
+
| ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY || soc/intel/quark || bool || SD LED indicates bootblock_soc_early_init successfully entered ||  
This option allows you to add the DMA Protected Range (DPR).
+
Indicate that bootblock_soc_early_init was entered.  If the SD LED
 +
does not light then debug the code in bootblock_main_with_timestamp.
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_LPSS || soc/intel/common/block/lpss || bool || ||  
+
| ENABLE_DEBUG_LED_SOC_EARLY_INIT_EXIT || soc/intel/quark || bool || SD LED indicates bootblock_soc_early_init successfully exited ||  
Intel Processor common LPSS support
+
Indicate that bootblock_soc_early_init exited.  If the SD LED does not
 +
light then debug the scripts in bootblock_soc_early_init.
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_FAST_SPI || soc/intel/common/block/fast_spi || bool || ||  
+
| ENABLE_DEBUG_LED_SOC_INIT_ENTRY || soc/intel/quark || bool || SD LED indicates bootblock_soc_init successfully entered ||  
Intel Processor common FAST_SPI support
+
Indicate that bootblock_soc_init was entered.  If the SD LED does not
 +
light then debug the code in bootblock_mainboard_early_init and
 +
console_init.  If the SD LED does light but there is no serial then
 +
debug the serial port configuration and initialization.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FAST_SPI_DISABLE_WRITE_STATUS || soc/intel/common/block/fast_spi || bool || Disable write status SPI opcode ||  
+
| DISPLAY_ESRAM_LAYOUT || soc/intel/quark || bool || Display ESRAM layout ||  
Disable the write status SPI opcode in Intel Fast SPI block.
+
Select this option to display coreboot's use of ESRAM.
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_UART || soc/intel/common/block/uart || bool ||  ||  
+
| CBFS_SIZE || soc/intel/quark || hex ||  ||  
Intel Processor common UART support
+
Specify the size of the coreboot file system in the read-only (recovery)
 +
portion of the flash part.  On Quark systems the firmware image stores
 +
more than just coreboot, including:
 +
- The chipset microcode (RMU) binary file located at 0xFFF00000
 +
- Intel Trusted Execution Engine firmware
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_M_VAL || soc/intel/common/block/uart || hex || ||  
+
| ADD_FSP_RAW_BIN || soc/intel/quark || bool || Add the Intel FSP binary to the flash image without relocation ||  
Clock m-divisor value for m/n divider
+
Select this option to add an Intel FSP binary to
 +
the resulting coreboot image.
 +
 
 +
Note: Without this binary, coreboot builds relying on the FSP
 +
will not boot
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_N_VAL || soc/intel/common/block/uart || hex || ||  
+
| FSP_FILE || soc/intel/quark || string || Intel FSP binary path and filename ||  
Clock m-divisor value for m/n divider
+
The path and filename of the Intel FSP binary for this platform.
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_GSPI || soc/intel/common/block/gspi || bool ||  ||  
+
| FSP_LOC || soc/intel/quark || hex ||  ||  
Intel Processor Common GSPI support
+
The location in CBFS that the FSP is located. This must match the
 +
value that is set in the FSP binary.  If the FSP needs to be moved,
 +
rebase the FSP with Intel's BCT (tool).
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_GSPI_MAX || soc/intel/common/block/gspi || int ||  ||  
+
| FSP_ESRAM_LOC || soc/intel/quark || hex ||  ||  
Maximum number of GSPI controllers supported by the PCH. SoC
+
The location in ESRAM where a copy of the FSP binary is placed.
must define this config if SOC_INTEL_COMMON_BLOCK_GSPI is
 
selected.
 
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_XHCI || soc/intel/common/block/xhci || bool || ||  
+
| RELOCATE_FSP_INTO_DRAM || soc/intel/quark || bool || Relocate FSP into DRAM ||  
Intel Processor common XHCI support
+
Relocate the FSP binary into DRAM before the call to SiliconInit.
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_PCIE || soc/intel/common/block/pcie || bool || ||  
+
| ADD_RMU_FILE || soc/intel/quark || bool || Should the RMU binary be added to the flash image? ||  
Intel Processor common PCIE support
+
The RMU file is required to get the chip out of reset.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PCIE_DEBUG_INFO || soc/intel/common/block/pcie || bool ||  ||  
+
| RMU_FILE || soc/intel/quark || string ||  ||  
Enable debug logs in PCIe module. Allows debug information on memory
+
The path and filename of the Intel Quark RMU binary.
base and limit, prefetchable memory base and limit, prefetchable memory
 
base upper 32 bits and prefetchable memory limit upper 32 bits.
 
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_PCR || soc/intel/common/block/pcr || bool ||  ||  
+
| RMU_LOC || soc/intel/quark || hex ||  ||  
Intel Processor common Private configuration registers (PCR)
+
The location in CBFS that the RMU is located. It must match the
 +
strap-determined base address.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PCR_COMMON_IOSF_1_0 || soc/intel/common/block/pcr || bool || ||  
+
| STORAGE_TEST || soc/intel/quark || bool || Test SD/MMC/eMMC card or device access ||  
The mapping of addresses via the SBREG_BAR assumes the IOSF-SB
+
Read block 0 from each parition of the storage device.  User
agents are using 32-bit aligned accesses for their configuration
+
must also enable one or both of COMMONLIB_STORAGE_SD or
registers. For IOSF versions greater than 1_0, IOSF-SB
+
COMMONLIB_STORAGE_MMC.
agents can use any access (8/16/32 bit aligned) for their
 
configuration registers
 
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_ACPI || soc/intel/common/block/acpi || bool || ||  
+
| I2C_DEBUG || soc/intel/quark || bool || Enable I2C debugging ||  
Intel Processor common code for ACPI
+
Display the I2C segments and controller errors
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_RTC || soc/intel/common/block/rtc || bool ||  ||  
+
| SOC_INTEL_SKYLAKE || soc/intel/skylake || bool ||  ||  
Intel Processor common RTC support
+
Intel Skylake support
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_CPU || soc/intel/common/block/cpu || bool ||  ||  
+
| SOC_INTEL_KABYLAKE || soc/intel/skylake || bool ||  ||  
This option selects Intel Common CPU Model support code
+
Intel Kabylake support
which provides various CPU related APIs which are common
 
between all Intel Processor families. Common CPU code is supported
 
for SOCs starting from SKL,KBL,APL, and future.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_CPU_MPINIT || soc/intel/common/block/cpu || bool ||  ||  
+
| DCACHE_RAM_SIZE || soc/intel/skylake || hex ||  ||  
This option selects Intel Common CPU MP Init code. In
+
The size of the cache-as-ram region required during bootblock
this common MP Init mechanism, the MP Init is occurring before
+
and/or romstage.
calling FSP Silicon Init. Hence, MP Init will be pulled to
 
BS_DEV_INIT_CHIPS Entry. And on Exit of BS_DEV_INIT, it is
 
ensured that all MTRRs are re-programmed based on the DRAM
 
resource settings.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_CAR || soc/intel/common/block/cpu || bool ||  ||  
+
| DCACHE_BSP_STACK_SIZE || soc/intel/skylake || hex ||  ||  
This option allows you to select how cache-as-ram (CAR) is set up.
+
The amount of anticipated stack usage in CAR by bootblock and
 +
other stages.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| INTEL_CAR_NEM || soc/intel/common/block/cpu || bool ||  ||  
+
| EXCLUDE_NATIVE_SD_INTERFACE || soc/intel/skylake || bool ||  ||  
Traditionally, CAR is set up by using Non-Evict mode. This method
+
If you set this option to n, will not use native SD controller.
does not allow CAR and cache to co-exist, because cache fills are
 
blocked in NEM.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| INTEL_CAR_CQOS || soc/intel/common/block/cpu || bool ||  ||  
+
| PCR_BASE_ADDRESS || soc/intel/skylake || hex ||  ||  
Cache Quality of Service allows more fine-grained control of cache
+
This option allows you to select MMIO Base Address of sideband bus.
usage. As result, it is possible to set up a portion of L2 cache for
 
CAR and use the remainder for actual caching.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| INTEL_CAR_NEM_ENHANCED || soc/intel/common/block/cpu || bool ||  ||  
+
| SERIRQ_CONTINUOUS_MODE || soc/intel/skylake || bool ||  ||  
A current limitation of NEM (Non-Evict mode) is that code and data sizes
+
If you set this option to y, the serial IRQ machine will be
are derived from the requirement to not write out any modified cache line.
+
operated in continuous mode.
With NEM, if there is no physical memory behind the cached area,
 
the modified data will be lost and NEM results will be inconsistent.
 
ENHANCED NEM guarantees that modified data is always
 
kept in cache while clean data is replaced.
 
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_CSE || soc/intel/common/block/cse || bool || ||  
+
| UART_FOR_CONSOLE || soc/intel/skylake || int || Index for LPSS UART port to use for console ||  
Driver for communication with Converged Security Engine (CSE)
+
Index for LPSS UART port to use for console:
over Host Embedded Controller Interface (HECI)
+
0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_EBDA || soc/intel/common/block/ebda || bool ||  ||  
+
| SKYLAKE_SOC_PCH_H || soc/intel/skylake || bool ||  ||  
Intel Processor common EBDA library support
+
Choose this option if you have a PCH-H chipset.
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_PMC || soc/intel/common/block/pmc || bool ||  ||  
+
| NHLT_DMIC_2CH || soc/intel/skylake || bool ||  ||  
Intel Processor common code for Power Management controller(PMC)
+
Include DSP firmware settings for 2 channel DMIC array.
subsystem
 
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_SMBUS || soc/intel/common/block/smbus || bool ||  ||  
+
| NHLT_DMIC_4CH || soc/intel/skylake || bool ||  ||  
Intel Processor common SMBus support
+
Include DSP firmware settings for 4 channel DMIC array.
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_GPIO || soc/intel/common/block/gpio || bool ||  ||  
+
| NHLT_NAU88L25 || soc/intel/skylake || bool ||  ||  
Intel Processor common GPIO support
+
Include DSP firmware settings for nau88l25 headset codec.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DEBUG_SOC_COMMON_BLOCK_GPIO || soc/intel/common/block/gpio || bool || Output verbose GPIO debug messages ||  
+
| NHLT_MAX98357 || soc/intel/skylake || bool || ||  
This option enables GPIO debug messages
+
Include DSP firmware settings for max98357 amplifier.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_SGX || soc/intel/common/block/sgx || bool ||  ||  
+
| NHLT_SSM4567 || soc/intel/skylake || bool ||  ||  
Software Guard eXtension(SGX) Feature. Intel SGX is a set of new CPU
+
Include DSP firmware settings for ssm4567 smart amplifier.
instructions that can be used by applications to set aside privat
 
regions of code and data.
 
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_I2C || soc/intel/common/block/i2c || bool ||  ||  
+
| NHLT_RT5514 || soc/intel/skylake || bool ||  ||  
Intel Processor Common I2C support
+
Include DSP firmware settings for rt5514 DSP.
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_ITSS || soc/intel/common/block/itss || bool ||  ||  
+
| NHLT_RT5663 || soc/intel/skylake || bool ||  ||  
Intel Processor common interrupt timer subsystem support
+
Include DSP firmware settings for rt5663 headset codec.
  
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| NHLT_MAX98927 || soc/intel/skylake || bool ||  ||
 +
Include DSP firmware settings for max98927 amplifier.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ACPI_CONSOLE || soc/intel/common || bool ||  ||  
+
| NHLT_DA7219 || soc/intel/skylake || bool ||  ||  
Provide a mechanism for serial console based ACPI debug.
+
Include DSP firmware settings for DA7219 headset codec.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_LPSS_CLOCK_MHZ || soc/intel/common || int || ||  
+
| NHLT_DA7219 || soc/intel/skylake || bool || Cache-as-ram implementation ||  
The clock speed that the controllers in LPSS(GSPI, I2C) are running
+
This option allows you to select how cache-as-ram (CAR) is set up.
at, in MHz. No default is set here as this is an SOC-specific value
 
and must be provided by the SOC.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_LPSS_I2C || soc/intel/common || bool || ||  
+
| USE_SKYLAKE_CAR_NEM_ENHANCED || soc/intel/skylake || bool || Enhanced Non-evict mode ||  
This driver supports the Intel Low Power Subsystem (LPSS) I2C
+
A current limitation of NEM (Non-Evict mode) is that code and data
controllers that are based on Synopsys DesignWare IP.
+
sizes are derived from the requirement to not write out any modified
 +
cache line. With NEM, if there is no physical memory behind the
 +
cached area, the modified data will be lost and NEM results will be
 +
inconsistent. ENHANCED NEM guarantees that modified data is always
 +
kept in cache while clean data is replaced.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_LPSS_I2C_DEBUG || soc/intel/common || bool || Enable debug output for LPSS I2C transactions ||  
+
| USE_SKYLAKE_FSP_CAR || soc/intel/skylake || bool || Use FSP CAR ||  
Enable debug output for I2C transactions.  This can be useful
+
Use FSP APIs to initialize and tear down the Cache-As-Ram.
when debugging I2C drivers.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MMA || soc/intel/common || bool || Enable MMA (Memory Margin Analysis) support for Intel Core ||  
+
| SKIP_FSP_CAR || soc/intel/skylake || bool || Skip cache as RAM setup in FSP ||  
Set this option to y to enable MMA (Memory Margin Analysis) support
+
Skip Cache as RAM setup in FSP.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| TPM_TIS_ACPI_INTERRUPT || soc/intel/common || int ||  ||  
+
| NO_FADT_8042 || soc/intel/skylake || bool ||  ||  
acpi_get_gpe() is used to provide interrupt status to TPM layer.
+
Choose this option if you want to disable 8042 Keyboard
This option specifies the GPE number.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_FSP_BROADWELL_DE || soc/intel/fsp_broadwell_de || bool ||  ||  
+
| SOC_INTEL_COMMON || soc/intel/common || bool ||  ||  
Broadwell-DE support using the Intel FSP.
+
common code for Intel SOCs
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| INTEGRATED_UART || soc/intel/fsp_broadwell_de || bool || Integrated UART ports ||  
+
| || || (comment) || || Intel SoC Common Code ||
Use Broadwell-DE Integrated UART ports @3F8h and 2F8h.
 
 
 
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SERIRQ_CONTINUOUS_MODE || soc/intel/fsp_broadwell_de || bool ||  ||  
+
| SOC_INTEL_COMMON_BLOCK || soc/intel/common/block || bool ||  ||  
If you set this option to y, the serial IRQ machine will be
+
SoC driver for intel common IP code
operated in continuous mode.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_FILE || soc/intel/fsp_broadwell_de/fsp || string ||  ||  
+
| || || (comment) || || Intel SoC Common IP Code ||
The path and filename of the Intel FSP binary for this platform.
+
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_TIMER || soc/intel/common/block/timer || bool ||  ||  
 +
Intel Processor common TIMER support
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_LOC || soc/intel/fsp_broadwell_de/fsp || hex ||  ||  
+
| SOC_INTEL_COMMON_BLOCK_XDCI || soc/intel/common/block/xdci || bool ||  ||  
The location in CBFS that the FSP is located. This must match the
+
Intel Processor common XDCI support
value that is set in the FSP binary.  If the FSP needs to be moved,
 
rebase the FSP with Intel's BCT (tool).
 
  
The Broadwell-DE FSP is built with a preferred base address of
+
||
0xffeb0000.
+
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_SCS || soc/intel/common/block/scs || bool ||  ||
 +
Intel Processor common storage and communication subsystem support
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_MEMORY_DOWN || soc/intel/fsp_broadwell_de/fsp || bool || Enable Memory Down ||  
+
| SOC_INTEL_COMMON_BLOCK_SATA || soc/intel/common/block/sata || bool || ||  
Load SPD data from ROM instead of trying to read from SMBus.
+
Intel Processor common SATA support
 
 
If the platform has DIMM sockets, say N. If memory is down, say Y and
 
supply the appropriate SPD data for each Channel/DIMM.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT || soc/intel/fsp_broadwell_de/fsp || bool || Channel 0, DIMM 0 Present ||  
+
| SOC_AHCI_PORT_IMPLEMENTED_INVERT || soc/intel/common/block/sata || bool || ||  
Select Y if Channel 0, DIMM 0 is present.
+
SATA PCI configuration space offset 0x92 Port
 +
implement register bit 0-2 represents respective
 +
SATA port enable status as in 0 = Disable; 1 = Enable.
 +
If this option is selected then port enable status will be
 +
inverted as in 0 = Enable; 1 = Disable.
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_MEMORY_DOWN_CH0DIMM0_SPD_FILE || soc/intel/fsp_broadwell_de/fsp || string || Channel 0, DIMM 0 SPD File ||  
+
| SOC_INTEL_COMMON_BLOCK_LPC || soc/intel/common/block/lpc || bool || ||  
Path to the file which contains the SPD data for Channel 0, DIMM 0.
+
Use common LPC code for platform. Only soc specific code needs to
 +
be implemented as per requirement.
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT || soc/intel/fsp_broadwell_de/fsp || bool || Channel 0, DIMM 1 Present ||  
+
| SOC_INTEL_COMMON_BLOCK_SPI || soc/intel/common/block/spi || bool || ||  
Select Y if Channel 0, DIMM 1 is present.
+
Intel Processor common SPI support
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_MEMORY_DOWN_CH0DIMM1_SPD_FILE || soc/intel/fsp_broadwell_de/fsp || string || Channel 0, DIMM 1 SPD File ||  
+
| SOC_INTEL_COMMON_BLOCK_P2SB || soc/intel/common/block/p2sb || bool || ||  
Path to the file which contains the SPD data for Channel 0, DIMM 1.
+
Intel Processor common P2SB driver
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT || soc/intel/fsp_broadwell_de/fsp || bool || Channel 1, DIMM 0 Present ||  
+
| SOC_INTEL_COMMON_BLOCK_SMM || soc/intel/common/block/smm || bool || ||  
Select Y if Channel 1, DIMM 0 is present.
+
Intel Processor common SMM support
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_MEMORY_DOWN_CH1DIMM0_SPD_FILE || soc/intel/fsp_broadwell_de/fsp || string || Channel 1, DIMM 0 SPD File ||  
+
| SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP || soc/intel/common/block/smm || bool || ||  
Path to the file which contains the SPD data for Channel 1, DIMM 0.
+
Intel Processor trap flag if it is supported
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT || soc/intel/fsp_broadwell_de/fsp || bool || Channel 1, DIMM 1 Present ||  
+
| SOC_INTEL_COMMON_BLOCK_SA || soc/intel/common/block/systemagent || bool || ||  
Select Y if Channel 1, DIMM 1 is present.
+
Intel Processor common System Agent support
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_MEMORY_DOWN_CH1DIMM1_SPD_FILE || soc/intel/fsp_broadwell_de/fsp || string || Channel 1, DIMM 1 SPD File ||  
+
| SA_PCIEX_LENGTH || soc/intel/common/block/systemagent || hex || ||  
Path to the file which contains the SPD data for Channel 1, DIMM 1.
+
This option allows you to select length of PCIEX region.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_HYPERTHREADING || soc/intel/fsp_broadwell_de/fsp || bool || Enable Hyper-Threading ||  
+
| SA_ENABLE_IMR || soc/intel/common/block/systemagent || bool || ||  
Enable Intel(r) Hyper-Threading Technology for the Broadwell-DE SoC.
+
This option allows you to add the isolated memory ranges (IMRs).
  
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| SA_ENABLE_DPR || soc/intel/common/block/systemagent || bool ||  ||
 +
This option allows you to add the DMA Protected Range (DPR).
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_BROADWELL || soc/intel/broadwell || bool ||  ||  
+
| SOC_INTEL_COMMON_BLOCK_HDA || soc/intel/common/block/hda || bool ||  ||  
Intel Broadwell and Haswell ULT support.
+
Intel Processor common High Definition Audio driver support
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DCACHE_RAM_SIZE || soc/intel/broadwell || hex ||  ||  
+
| SOC_INTEL_COMMON_BLOCK_LPSS || soc/intel/common/block/lpss || bool ||  ||  
The size of the cache-as-ram region required during bootblock
+
Intel Processor common LPSS support
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
 
must add up to a power of 2.
 
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DCACHE_RAM_MRC_VAR_SIZE || soc/intel/broadwell || hex ||  ||  
+
| SOC_INTEL_COMMON_BLOCK_FAST_SPI || soc/intel/common/block/fast_spi || bool ||  ||  
The amount of cache-as-ram region required by the reference code.
+
Intel Processor common FAST_SPI support
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HAVE_MRC || soc/intel/broadwell || bool || Add a Memory Reference Code binary ||  
+
| FAST_SPI_DISABLE_WRITE_STATUS || soc/intel/common/block/fast_spi || bool || Disable write status SPI opcode ||  
Select this option to add a Memory Reference Code binary to
+
Disable the write status SPI opcode in Intel Fast SPI block.
the resulting coreboot image.
 
  
Note: Without this binary coreboot will not work
+
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_UART || soc/intel/common/block/uart || bool ||  ||
 +
Intel Processor common UART support
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MRC_FILE || soc/intel/broadwell || string || Intel Memory Reference Code path and filename ||  
+
| SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_M_VAL || soc/intel/common/block/uart || hex || ||  
The filename of the file to use as Memory Reference Code binary.
+
Clock m-divisor value for m/n divider
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PRE_GRAPHICS_DELAY || soc/intel/broadwell || int || Graphics initialization delay in ms ||  
+
| SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_N_VAL || soc/intel/common/block/uart || hex || ||  
On some systems, coreboot boots so fast that connected monitors
+
Clock m-divisor value for m/n divider
(mostly TVs) won't be able to wake up fast enough to talk to the
 
VBIOS. On those systems we need to wait for a bit before executing
 
the VBIOS.
 
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| RESET_ON_INVALID_RAMSTAGE_CACHE || soc/intel/broadwell || bool || Reset the system on S3 wake when ramstage cache invalid. ||  
+
| SOC_INTEL_COMMON_BLOCK_GSPI || soc/intel/common/block/gspi || bool || ||  
The romstage code caches the loaded ramstage program in SMM space.
+
Intel Processor Common GSPI support
On S3 wake the romstage will copy over a fresh ramstage that was
 
cached in the SMM space. This option determines the action to take
 
when the ramstage cache is invalid. If selected the system will
 
reset otherwise the ramstage will be reloaded from cbfs.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SERIRQ_CONTINUOUS_MODE || soc/intel/broadwell || bool ||  ||  
+
| SOC_INTEL_COMMON_BLOCK_GSPI_MAX || soc/intel/common/block/gspi || int ||  ||  
If you set this option to y, the serial IRQ machine will be
+
Maximum number of GSPI controllers supported by the PCH. SoC
operated in continuous mode.
+
must define this config if SOC_INTEL_COMMON_BLOCK_GSPI is
 +
selected.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HAVE_REFCODE_BLOB || soc/intel/broadwell || bool || An external reference code blob should be put into cbfs. ||  
+
| SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 || soc/intel/common/block/gspi || bool || ||  
The reference code blob will be placed into cbfs.
+
Intel Processor Common GSPI support with quirks to handle
 +
SPI_CS_CONTROL changes introduced in CNL.
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| REFCODE_BLOB_FILE || soc/intel/broadwell || string || Path and filename to reference code blob. ||  
+
| SOC_INTEL_COMMON_BLOCK_XHCI || soc/intel/common/block/xhci || bool || ||  
The path and filename to the file to be added to cbfs.
+
Intel Processor common XHCI support
  
 
||
 
||
|- bgcolor="#eeeeee"
 
| SOC_INTEL_SKYLAKE || soc/intel/skylake || bool ||  ||
 
Intel Skylake support
 
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_KABYLAKE || soc/intel/skylake || bool ||  ||  
+
| SOC_INTEL_COMMON_BLOCK_PCIE || soc/intel/common/block/pcie || bool ||  ||  
Intel Kabylake support
+
Intel Processor common PCIE support
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DCACHE_RAM_SIZE || soc/intel/skylake || hex ||  ||  
+
| PCIE_DEBUG_INFO || soc/intel/common/block/pcie || bool ||  ||  
The size of the cache-as-ram region required during bootblock
+
Enable debug logs in PCIe module. Allows debug information on memory
and/or romstage.
+
base and limit, prefetchable memory base and limit, prefetchable memory
 +
base upper 32 bits and prefetchable memory limit upper 32 bits.
  
 
||
 
||
|- bgcolor="#eeeeee"
 
| DCACHE_BSP_STACK_SIZE || soc/intel/skylake || hex ||  ||
 
The amount of anticipated stack usage in CAR by bootblock and
 
other stages.
 
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EXCLUDE_NATIVE_SD_INTERFACE || soc/intel/skylake || bool ||  ||  
+
| SOC_INTEL_COMMON_BLOCK_PCR || soc/intel/common/block/pcr || bool ||  ||  
If you set this option to n, will not use native SD controller.
+
Intel Processor common Private configuration registers (PCR)
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PCR_BASE_ADDRESS || soc/intel/skylake || hex ||  ||  
+
| PCR_COMMON_IOSF_1_0 || soc/intel/common/block/pcr || bool ||  ||  
This option allows you to select MMIO Base Address of sideband bus.
+
The mapping of addresses via the SBREG_BAR assumes the IOSF-SB
 +
agents are using 32-bit aligned accesses for their configuration
 +
registers. For IOSF versions greater than 1_0, IOSF-SB
 +
agents can use any access (8/16/32 bit aligned) for their
 +
configuration registers
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SERIRQ_CONTINUOUS_MODE || soc/intel/skylake || bool ||  ||  
+
| SOC_INTEL_COMMON_BLOCK_ACPI || soc/intel/common/block/acpi || bool ||  ||  
If you set this option to y, the serial IRQ machine will be
+
Intel Processor common code for ACPI
operated in continuous mode.
 
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| UART_FOR_CONSOLE || soc/intel/skylake || int || Index for LPSS UART port to use for console ||  
+
| SOC_INTEL_COMMON_BLOCK_RTC || soc/intel/common/block/rtc || bool || ||  
Index for LPSS UART port to use for console:
+
Intel Processor common RTC support
0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
 
  
 
||
 
||
|- bgcolor="#eeeeee"
 
| SKYLAKE_SOC_PCH_H || soc/intel/skylake || bool ||  ||
 
Choose this option if you have a PCH-H chipset.
 
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NHLT_DMIC_2CH || soc/intel/skylake || bool ||  ||  
+
| SOC_INTEL_COMMON_BLOCK_CPU || soc/intel/common/block/cpu || bool ||  ||  
Include DSP firmware settings for 2 channel DMIC array.
+
This option selects Intel Common CPU Model support code
 +
which provides various CPU related APIs which are common
 +
between all Intel Processor families. Common CPU code is supported
 +
for SOCs starting from SKL,KBL,APL, and future.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NHLT_DMIC_4CH || soc/intel/skylake || bool ||  ||  
+
| SOC_INTEL_COMMON_BLOCK_CPU_MPINIT || soc/intel/common/block/cpu || bool ||  ||  
Include DSP firmware settings for 4 channel DMIC array.
+
This option selects Intel Common CPU MP Init code. In
 +
this common MP Init mechanism, the MP Init is occurring before
 +
calling FSP Silicon Init. Hence, MP Init will be pulled to
 +
BS_DEV_INIT_CHIPS Entry. And on Exit of BS_DEV_INIT, it is
 +
ensured that all MTRRs are re-programmed based on the DRAM
 +
resource settings.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NHLT_NAU88L25 || soc/intel/skylake || bool ||  ||  
+
| SOC_INTEL_COMMON_BLOCK_CAR || soc/intel/common/block/cpu || bool ||  ||  
Include DSP firmware settings for nau88l25 headset codec.
+
This option allows you to select how cache-as-ram (CAR) is set up.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NHLT_MAX98357 || soc/intel/skylake || bool ||  ||  
+
| INTEL_CAR_NEM || soc/intel/common/block/cpu || bool ||  ||  
Include DSP firmware settings for max98357 amplifier.
+
Traditionally, CAR is set up by using Non-Evict mode. This method
 +
does not allow CAR and cache to co-exist, because cache fills are
 +
blocked in NEM.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NHLT_SSM4567 || soc/intel/skylake || bool ||  ||  
+
| INTEL_CAR_CQOS || soc/intel/common/block/cpu || bool ||  ||  
Include DSP firmware settings for ssm4567 smart amplifier.
+
Cache Quality of Service allows more fine-grained control of cache
 +
usage. As result, it is possible to set up a portion of L2 cache for
 +
CAR and use the remainder for actual caching.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NHLT_RT5514 || soc/intel/skylake || bool ||  ||  
+
| INTEL_CAR_NEM_ENHANCED || soc/intel/common/block/cpu || bool ||  ||  
Include DSP firmware settings for rt5514 DSP.
+
A current limitation of NEM (Non-Evict mode) is that code and data sizes
 +
are derived from the requirement to not write out any modified cache line.
 +
With NEM, if there is no physical memory behind the cached area,
 +
the modified data will be lost and NEM results will be inconsistent.
 +
ENHANCED NEM guarantees that modified data is always
 +
kept in cache while clean data is replaced.
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NHLT_RT5663 || soc/intel/skylake || bool ||  ||  
+
| SOC_INTEL_COMMON_BLOCK_CSE || soc/intel/common/block/cse || bool ||  ||  
Include DSP firmware settings for rt5663 headset codec.
+
Driver for communication with Converged Security Engine (CSE)
 +
over Host Embedded Controller Interface (HECI)
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NHLT_MAX98927 || soc/intel/skylake || bool ||  ||  
+
| SOC_INTEL_COMMON_BLOCK_EBDA || soc/intel/common/block/ebda || bool ||  ||  
Include DSP firmware settings for max98927 amplifier.
+
Intel Processor common EBDA library support
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NHLT_MAX98927 || soc/intel/skylake || bool || Cache-as-ram implementation ||  
+
| SOC_INTEL_COMMON_BLOCK_PMC || soc/intel/common/block/pmc || bool || ||  
This option allows you to select how cache-as-ram (CAR) is set up.
+
Intel Processor common code for Power Management controller(PMC)
 +
subsystem
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CAR_NEM_ENHANCED || soc/intel/skylake || bool || Enhanced Non-evict mode ||  
+
| POWER_STATE_OFF_AFTER_FAILURE || soc/intel/common/block/pmc || bool || S5 Soft Off ||  
A current limitation of NEM (Non-Evict mode) is that code and data sizes
+
Choose this option if you want to keep system into
are derived from the requirement to not write out any modified cache line.
+
S5 after reapplying power after failure
With NEM, if there is no physical memory behind the cached area,
 
the modified data will be lost and NEM results will be inconsistent.
 
ENHANCED NEM guarantees that modified data is always
 
kept in cache while clean data is replaced.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| USE_SKYLAKE_FSP_CAR || soc/intel/skylake || bool || Use FSP CAR ||  
+
| POWER_STATE_ON_AFTER_FAILURE || soc/intel/common/block/pmc || bool || S0 Full On ||  
Use FSP APIs to initialize & tear Down the Cache-As-Ram.
+
Choose this option if you want to keep system into
 +
S0 after reapplying power after failure
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SKIP_FSP_CAR || soc/intel/skylake || bool || Skip cache as RAM setup in FSP ||  
+
| POWER_STATE_PREVIOUS_AFTER_FAILURE || soc/intel/common/block/pmc || bool || Keep Previous State ||  
Skip Cache as RAM setup in FSP.
+
Choose this option if you want to keep system into
 +
same power state as before failure even after reapplying
 +
power
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NO_FADT_8042 || soc/intel/skylake || bool ||  ||  
+
| PMC_INVALID_READ_AFTER_WRITE || soc/intel/common/block/pmc || bool ||  ||  
Choose this option if you want to disable 8042 Keyboard
+
Enable this for PMC devices where a read back of ACPI BAR and
 +
IO access bit does not return the previously written value.
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_AMD_STONEYRIDGE_FP4 || soc/amd/stoneyridge || bool ||  ||  
+
| SOC_INTEL_COMMON_BLOCK_SMBUS || soc/intel/common/block/smbus || bool ||  ||  
AMD Stoney Ridge FP4 support
+
Intel Processor common SMBus support
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_AMD_STONEYRIDGE_FT4 || soc/amd/stoneyridge || bool ||  ||  
+
| SOC_INTEL_COMMON_BLOCK_GPIO || soc/intel/common/block/gpio || bool ||  ||  
AMD Stoney Ridge FT4 support
+
Intel Processor common GPIO support
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DCACHE_BSP_STACK_SIZE || soc/amd/stoneyridge || hex || ||  
+
| DEBUG_SOC_COMMON_BLOCK_GPIO || soc/intel/common/block/gpio || bool || Output verbose GPIO debug messages ||  
The amount of anticipated stack usage in CAR by bootblock and
+
This option enables GPIO debug messages
other stages.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PRERAM_CBMEM_CONSOLE_SIZE || soc/amd/stoneyridge || hex ||  ||  
+
| SOC_INTEL_COMMON_BLOCK_SGX || soc/intel/common/block/sgx || bool ||  ||  
Increase this value if preram cbmem console is getting truncated
+
Software Guard eXtension(SGX) Feature. Intel SGX is a set of new CPU
 +
instructions that can be used by applications to set aside privat
 +
regions of code and data.
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOTTOMIO_POSITION || soc/amd/stoneyridge || hex || Bottom of 32-bit IO space ||  
+
| SOC_INTEL_COMMON_BLOCK_DSP || soc/intel/common/block/dsp || bool || ||  
If PCI peripherals with big BARs are connected to the system
+
Intel Processor common DSP support
the bottom of the IO must be decreased to allocate such
 
devices.
 
  
Declare the beginning of the 128MB-aligned MMIO region. This
+
||
option is useful when PCI peripherals requesting large address
+
||
ranges are present.
+
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_I2C || soc/intel/common/block/i2c || bool || ||
 +
Intel Processor Common I2C support
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VGA_BIOS_ID || soc/amd/stoneyridge || string || ||  
+
| SOC_INTEL_COMMON_BLOCK_I2C_DEBUG || soc/intel/common/block/i2c || bool || Enable debug output for LPSS I2C transactions ||  
The default VGA BIOS PCI vendor/device ID should be set to the
+
Enable debug output for I2C transactions.  This can be useful
result of the map_oprom_vendev() function in northbridge.c.
+
when debugging I2C drivers.
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| STONEYRIDGE_XHCI_ENABLE || soc/amd/stoneyridge || bool || Enable Stoney Ridge XHCI Controller ||  
+
| SOC_INTEL_COMMON_BLOCK_SRAM || soc/intel/common/block/sram || bool || ||  
The XHCI controller must be enabled and the XHCI firmware
+
Intel Processor common SRAM support
must be added in order to have USB 3.0 support configured
 
by coreboot. The OS will be responsible for enabling the XHCI
 
controller if the the XHCI firmware is available but the
 
XHCI controller is not enabled by coreboot.
 
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| STONEYRIDGE_XHCI_FWM || soc/amd/stoneyridge || bool || Add xhci firmware ||  
+
| SOC_INTEL_COMMON_BLOCK_ITSS || soc/intel/common/block/itss || bool || ||  
Add Stoney Ridge XHCI Firmware to support the onboard USB 3.0
+
Intel Processor common interrupt timer subsystem support
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| STONEYRIDGE_IMC_FWM || soc/amd/stoneyridge || bool || Add IMC firmware ||  
+
| SOC_INTEL_COMMON_BLOCK_GRAPHICS || soc/intel/common/block/graphics || bool || ||  
Add Stoney Ridge IMC Firmware to support the onboard fan control
+
Intel Processor common Graphics support
 +
 
 +
||
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| STONEYRIDGE_GEC_FWM || soc/amd/stoneyridge || bool ||  ||  
+
| ACPI_CONSOLE || soc/intel/common || bool ||  ||  
Add Stoney Ridge GEC Firmware to support the onboard gigabit Ethernet MAC.
+
Provide a mechanism for serial console based ACPI debug.
Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| STONEYRIDGE_SATA_MODE || soc/amd/stoneyridge || int || SATA Mode ||  
+
| SOC_INTEL_COMMON_LPSS_CLOCK_MHZ || soc/intel/common || int || ||  
Select the mode in which SATA should be driven.
+
The clock speed that the controllers in LPSS(GSPI, I2C) are running
The default is NATIVE.
+
at, in MHz. No default is set here as this is an SOC-specific value
0: NATIVE mode does not require a ROM.
+
and must be provided by the SOC.
2: AHCI may work with or without AHCI ROM. It depends on the payload support.
 
For example, seabios does not require the AHCI ROM.
 
3: LEGACY IDE
 
4: IDE to AHCI
 
5: AHCI7804: ROM Required, and AMD driver required in the OS.
 
6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || NATIVE ||
+
| MMA || soc/intel/common || bool || Enable MMA (Memory Margin Analysis) support for Intel Core ||  
 +
Set this option to y to enable MMA (Memory Margin Analysis) support
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || AHCI ||
+
| TPM_TIS_ACPI_INTERRUPT || soc/intel/common || int || ||  
|- bgcolor="#eeeeee"
+
acpi_get_gpe() is used to provide interrupt status to TPM layer.
| || || (comment) || || LEGACY IDE ||
+
This option specifies the GPE number.
|- bgcolor="#eeeeee"
 
| || || (comment) || || IDE to AHCI ||
 
|- bgcolor="#eeeeee"
 
| || || (comment) || || AHCI7804 ||
 
|- bgcolor="#eeeeee"
 
| || || (comment) || || IDE to AHCI7804 ||
 
|- bgcolor="#eeeeee"
 
| STONEYRIDGE_LEGACY_FREE || soc/amd/stoneyridge || bool || System is legacy free ||
 
Select y if there is no keyboard controller in the system.
 
This sets variables in AGESA and ACPI.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SERIRQ_CONTINUOUS_MODE || soc/amd/stoneyridge || bool ||  ||  
+
| SOC_AMD_STONEYRIDGE_FP4 || soc/amd/stoneyridge || bool ||  ||  
Set this option to y for serial IRQ in continuous mode.
+
AMD Stoney Ridge FP4 support
Otherwise it is in quiet mode.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| STONEYRIDGE_ACPI_IO_BASE || soc/amd/stoneyridge || hex ||  ||  
+
| SOC_AMD_STONEYRIDGE_FT4 || soc/amd/stoneyridge || bool ||  ||  
Base address for the ACPI registers.
+
AMD Stoney Ridge FT4 support
This value must match the hardcoded value of AGESA.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| STONEYRIDGE_UART || soc/amd/stoneyridge || bool || UART controller on Stoney Ridge ||  
+
| DCACHE_BSP_STACK_SIZE || soc/amd/stoneyridge || hex || ||  
There are two UART controllers in Stoney Ridge.
+
The amount of anticipated stack usage in CAR by bootblock and
The UART registers are memory-mapped. UART
+
other stages.
controller 0 registers range from FEDC_6000h
 
to FEDC_6FFFh. UART controller 1 registers
 
range from FEDC_8000h to FEDC_8FFFh.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| USE_PSPSCUREOS || soc/amd/stoneyridge || bool || Include PSP SecureOS blobs in AMD firmware ||  
+
| PRERAM_CBMEM_CONSOLE_SIZE || soc/amd/stoneyridge || hex || ||  
Include the PspSecureOs, PspTrustlet and TrustletKey binaries
+
Increase this value if preram cbmem console is getting truncated
in the amdfw section.
+
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOTTOMIO_POSITION || soc/amd/stoneyridge || hex || Bottom of 32-bit IO space ||
 +
If PCI peripherals with big BARs are connected to the system
 +
the bottom of the IO must be decreased to allocate such
 +
devices.
  
If unsure, answer 'y'
+
Declare the beginning of the 128MB-aligned MMIO region.  This
 +
option is useful when PCI peripherals requesting large address
 +
ranges are present.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| AMDFW_OUTSIDE_CBFS || soc/amd/stoneyridge || bool || The AMD firmware is outside CBFS ||  
+
| VGA_BIOS_ID || soc/amd/stoneyridge || string || ||  
The AMDFW (PSP) is typically locatable in cbfs. Select this
+
The default VGA BIOS PCI vendor/device ID should be set to the
option to manually attach the generated amdfw.rom outside of
+
result of the map_oprom_vendev() function in northbridge.c.
cbfs.  The location is selected by the FWM position.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| AMD_FWM_POSITION_INDEX || soc/amd/stoneyridge || int || Firmware Directory Table location (0 to 5) ||  
+
| STONEYRIDGE_XHCI_ENABLE || soc/amd/stoneyridge || bool || Enable Stoney Ridge XHCI Controller ||  
Typically this is calculated by the ROM size, but there may
+
The XHCI controller must be enabled and the XHCI firmware
be situations where you want to put the firmware directory
+
must be added in order to have USB 3.0 support configured
table in a different location.
+
by coreboot. The OS will be responsible for enabling the XHCI
0: 512 KB - 0xFFFA0000
+
controller if the the XHCI firmware is available but the
1: 1 MB  - 0xFFF20000
+
XHCI controller is not enabled by coreboot.
2: 2 MB  - 0xFFE20000
 
3: 4 MB  - 0xFFC20000
 
4: 8 MB  - 0xFF820000
 
5: 16 MB  - 0xFF020000
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || AMD Firmware Directory Table set to location for 512KB ROM ||
+
| STONEYRIDGE_XHCI_FWM || soc/amd/stoneyridge || bool || Add xhci firmware ||  
 +
Add Stoney Ridge XHCI Firmware to support the onboard USB 3.0
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || AMD Firmware Directory Table set to location for 1MB ROM ||
+
| STONEYRIDGE_IMC_FWM || soc/amd/stoneyridge || bool || Add IMC firmware ||  
 +
Add Stoney Ridge IMC Firmware to support the onboard fan control
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || AMD Firmware Directory Table set to location for 2MB ROM ||
+
| STONEYRIDGE_GEC_FWM || soc/amd/stoneyridge || bool ||  ||  
|- bgcolor="#eeeeee"
+
Add Stoney Ridge GEC Firmware to support the onboard gigabit Ethernet MAC.
| || || (comment) || || AMD Firmware Directory Table set to location for 4MB ROM ||
+
Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
|- bgcolor="#eeeeee"
 
| || || (comment) || || AMD Firmware Directory Table set to location for 8MB ROM ||
 
|- bgcolor="#eeeeee"
 
| || || (comment) || || AMD Firmware Directory Table set to location for 16MB ROM ||
 
|- bgcolor="#eeeeee"
 
| SOC_AMD_COMMON || soc/amd/common || bool ||  ||  
 
common code for AMD SOCs
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_AMD_COMMON_BLOCK || soc/amd/common/block || bool || ||  
+
| STONEYRIDGE_SATA_MODE || soc/amd/stoneyridge || int || SATA Mode ||  
SoC driver for AMD common IP code
+
Select the mode in which SATA should be driven.
 +
The default is NATIVE.
 +
0: NATIVE mode does not require a ROM.
 +
2: AHCI may work with or without AHCI ROM. It depends on the payload support.
 +
For example, seabios does not require the AHCI ROM.
 +
3: LEGACY IDE
 +
4: IDE to AHCI
 +
5: AHCI7804: ROM Required, and AMD driver required in the OS.
 +
6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || AMD SoC Common IP Code ||
+
| || || (comment) || || NATIVE ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || AHCI ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || LEGACY IDE ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || IDE to AHCI ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || AHCI7804 ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || IDE to AHCI7804 ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_AMD_COMMON_BLOCK_CAR || soc/amd/common/block/cpu || bool || ||  
+
| STONEYRIDGE_LEGACY_FREE || soc/amd/stoneyridge || bool || System is legacy free ||  
This option allows the SOC to use a standard AMD cache-as-ram (CAR)
+
Select y if there is no keyboard controller in the system.
implementation.  CAR setup is built into bootblock and teardown is
+
This sets variables in AGESA and ACPI.
in postcar.  The teardown procedure does not preserve the stack so
 
it may not be appropriate for a romstage implementation without
 
additional consideration. If this option is not used, the SOC must
 
implement these functions separately.
 
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_AMD_COMMON_BLOCK_PSP || soc/amd/common/block/psp || bool ||  ||  
+
| SERIRQ_CONTINUOUS_MODE || soc/amd/stoneyridge || bool ||  ||  
This option builds in the Platform Security Processor initialization
+
Set this option to y for serial IRQ in continuous mode.
functions.
+
Otherwise it is in quiet mode.
 
 
||
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE || soc/broadcom/cygnus || bool || Enable DDR auto self-refresh ||  
+
| STONEYRIDGE_ACPI_IO_BASE || soc/amd/stoneyridge || hex || ||  
Warning: M0 expects that auto self-refresh is enabled. Modify
+
Base address for the ACPI registers.
with caution.
+
This value must match the hardcoded value of AGESA.
  
 +
||
 +
|- bgcolor="#eeeeee"
 +
| STONEYRIDGE_UART || soc/amd/stoneyridge || bool || UART controller on Stoney Ridge ||
 +
There are two UART controllers in Stoney Ridge.
 +
The UART registers are memory-mapped. UART
 +
controller 0 registers range from FEDC_6000h
 +
to FEDC_6FFFh. UART controller 1 registers
 +
range from FEDC_8000h to FEDC_8FFFh.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DEBUG_DRAM || soc/mediatek/mt8173 || bool || Output verbose DRAM related debug message ||  
+
| USE_PSPSCUREOS || soc/amd/stoneyridge || bool || Include PSP SecureOS blobs in AMD firmware ||  
This option enables additional DRAM related debug messages.
+
Include the PspSecureOs, PspTrustlet and TrustletKey binaries
 +
in the amdfw section.
 +
 
 +
If unsure, answer 'y'
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DEBUG_I2C || soc/mediatek/mt8173 || bool || Output verbose I2C related debug message ||  
+
| AMDFW_OUTSIDE_CBFS || soc/amd/stoneyridge || bool || The AMD firmware is outside CBFS ||  
This option enables I2C related debug message.
+
The AMDFW (PSP) is typically locatable in cbfs.  Select this
 +
option to manually attach the generated amdfw.rom outside of
 +
cbfs.  The location is selected by the FWM position.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DEBUG_PMIC || soc/mediatek/mt8173 || bool || Output verbose PMIC related debug message ||  
+
| AMD_FWM_POSITION_INDEX || soc/amd/stoneyridge || int || Firmware Directory Table location (0 to 5) ||  
This option enables PMIC related debug message.
+
Typically this is calculated by the ROM size, but there may
 +
be situations where you want to put the firmware directory
 +
table in a different location.
 +
0: 512 KB - 0xFFFA0000
 +
1: 1 MB  - 0xFFF20000
 +
2: 2 MB  - 0xFFE20000
 +
3: 4 MB  - 0xFFC20000
 +
4: 8 MB  - 0xFF820000
 +
5: 16 MB  - 0xFF020000
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DEBUG_PMIC_WRAP || soc/mediatek/mt8173 || bool || Output verbose PMIC WRAP related debug message ||  
+
| || || (comment) || || AMD Firmware Directory Table set to location for 512KB ROM ||
This option enables PMIC WRAP related debug message.
 
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_MVMAP2315_UART_ADDRESS || soc/marvell/mvmap2315 || hex || ||  
+
| || || (comment) || || AMD Firmware Directory Table set to location for 1MB ROM ||
Map the UART to the respective MMIO address
 
 
 
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| TTYS0_BAUD || soc/marvell/mvmap2315 || int || ||  
+
| || || (comment) || || AMD Firmware Directory Table set to location for 2MB ROM ||
Baud rate for the UART
 
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| IPQ_QFN_PART || soc/qualcomm/ipq40xx || bool || ||  
+
| || || (comment) || || AMD Firmware Directory Table set to location for 4MB ROM ||
Is the SoC a QFN part (as opposed to a BGA part)
 
 
 
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SBL_ELF || soc/qualcomm/ipq40xx || string || file name of the QCA SBL ELF ||  
+
| || || (comment) || || AMD Firmware Directory Table set to location for 8MB ROM ||
The path and filename of the binary blob containing
 
ipq40xx early initialization code, as supplied by the
 
vendor.
 
 
 
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SBL_UTIL_PATH || soc/qualcomm/ipq40xx || string || Path for utils to combine SBL_ELF and bootblock ||  
+
| || || (comment) || || AMD Firmware Directory Table set to location for 16MB ROM ||
Path for utils to combine SBL_ELF and bootblock
 
 
 
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SBL_BLOB || soc/qualcomm/ipq806x || string || file name of the Qualcomm SBL blob ||  
+
| SOC_AMD_COMMON || soc/amd/common || bool || ||  
The path and filename of the binary blob containing
+
common code for AMD SOCs
ipq806x early initialization code, as supplied by the
 
vendor.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| RK3399_SPREAD_SPECTRUM_DDR || soc/rockchip/rk3399 || bool || Spread-spectrum DDR clock ||  
+
| SOC_AMD_COMMON_BLOCK || soc/amd/common/block || bool || ||  
Select Spread Spectrum Modulator (SSMOD) is a fully-digital circuit
+
SoC driver for AMD common IP code
used to modulate the frequency of the Silicon Creations’ Fractional
 
PLL in order to reduce EMI.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || CPU ||
+
| || || (comment) || || AMD SoC Common IP Code ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| RESET_ON_INVALID_RAMSTAGE_CACHE || cpu/intel/haswell || bool || Reset the system on S3 wake when ramstage cache invalid. ||  
+
| SOC_AMD_COMMON_BLOCK_S3 || soc/amd/common/block/s3 || bool || ||  
The haswell romstage code caches the loaded ramstage program
+
Select this option to add S3 related functions to the build.
in SMM space. On S3 wake the romstage will copy over a fresh
 
ramstage that was cached in the SMM space. This option determines
 
the action to take when the ramstage cache is invalid. If selected
 
the system will reset otherwise the ramstage will be reloaded from
 
cbfs.
 
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CPU_INTEL_FIRMWARE_INTERFACE_TABLE || cpu/intel/fit || None ||  ||  
+
| SOC_AMD_COMMON_BLOCK_PI || soc/amd/common/block/pi || bool ||  ||  
This option selects building a Firmware Interface Table (FIT).
+
This option builds functions that interface AMD's AGESA.
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CPU_INTEL_NUM_FIT_ENTRIES || cpu/intel/fit || int ||  ||  
+
| SOC_AMD_COMMON_BLOCK_PCI || soc/amd/common/block/pci || bool ||  ||  
This option selects the number of empty entries in the FIT table.
+
This option builds functions used to program PCI interrupt
 +
routing, both PIC and APIC modes.
  
 
||
 
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED || cpu/intel/turbo || None ||  ||  
+
| SOC_AMD_COMMON_BLOCK_CAR || soc/amd/common/block/cpu || bool ||  ||  
This option indicates that the turbo mode setting is not package
+
This option allows the SOC to use a standard AMD cache-as-ram (CAR)
scoped. i.e. enable_turbo() needs to be called on not just the bsp
+
implementation.  CAR setup is built into bootblock and teardown is
 +
in postcar.  The teardown procedure does not preserve the stack so
 +
it may not be appropriate for a romstage implementation without
 +
additional consideration. If this option is not used, the SOC must
 +
implement these functions separately.
  
 
||
 
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SET_VMX_LOCK_BIT || cpu/intel/common || bool || Set lock bit after configuring VMX ||  
+
| SOC_AMD_COMMON_BLOCK_PSP || soc/amd/common/block/psp || bool || ||  
Although the Intel manual says you must set the lock bit in addition
+
This option builds in the Platform Security Processor initialization
to the VMX bit in order for VMX to work, this isn't strictly true, so
+
functions.
we have the option to leave it unlocked and allow the OS (e.g. Linux)
 
to manage things itself. This is beneficial for testing purposes as
 
there is no need to reflash the firmware just to toggle the lock bit.
 
However, leaving the lock bit unset will break Windows' detection of
 
VMX support and built-in virtualization features like Hyper-V.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| GEODE_VSA_FILE || cpu/amd/geode_gx2 || bool || Add a VSA image ||  
+
| SOC_AMD_PSP_SELECTABLE_SMU_FW || soc/amd/common/block/psp || bool || ||  
Select this option if you have an AMD Geode GX2 vsa that you would
+
Some PSP implementations allow storing SMU firmware into cbfs and
like to add to your ROM.
+
calling the PSP to load the blobs at the proper time.
  
You will be able to specify the location and file name of the
+
The soc/<codename> should select this if its PSP supports the feature
image later.
+
and each mainboard can choose to select an appropriate fanless or
 +
fanned set of blobs.  Ask your AMD representative whether your APU
 +
is considered fanless.
  
 
||
 
||
|- bgcolor="#eeeeee"
 
| VSA_FILENAME || cpu/amd/geode_gx2 || string || AMD Geode GX2 VSA path and filename ||
 
The path and filename of the file to use as VSA.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| GEODE_VSA_FILE || cpu/amd/geode_lx || bool || Add a VSA image ||  
+
| CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE || soc/broadcom/cygnus || bool || Enable DDR auto self-refresh ||  
Select this option if you have an AMD Geode LX vsa that you would
+
Warning: M0 expects that auto self-refresh is enabled. Modify
like to add to your ROM.
+
with caution.
  
You will be able to specify the location and file name of the
 
image later.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VSA_FILENAME || cpu/amd/geode_lx || string || AMD Geode LX VSA path and filename ||  
+
| DEBUG_DRAM || soc/mediatek/mt8173 || bool || Output verbose DRAM related debug messages ||  
The path and filename of the file to use as VSA.
+
This option enables additional DRAM related debug messages.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| XIP_ROM_SIZE || cpu/amd/agesa || hex || ||  
+
| DEBUG_I2C || soc/mediatek/mt8173 || bool || Output verbose I2C related debug messages ||  
Overwride the default write through caching size as 1M Bytes.
+
This option enables I2C related debug messages.
On some AMD platforms, one socket supports 2 or more kinds of
 
processor family, compiling several CPU families agesa code
 
will increase the romstage size.
 
In order to execute romstage in place on the flash ROM,
 
more space is required to be set as write through caching.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_MRC_CACHE || cpu/amd/agesa || bool || Use cached memory configuration ||  
+
| DEBUG_PMIC || soc/mediatek/mt8173 || bool || Output verbose PMIC related debug messages ||  
Try to restore memory training results
+
This option enables PMIC related debug messages.
from non-volatile memory.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CPU_AMD_SOCKET_G34 || cpu/amd/agesa/family15 || bool || ||  
+
| DEBUG_PMIC_WRAP || soc/mediatek/mt8173 || bool || Output verbose PMIC WRAP related debug messages ||  
AMD G34 Socket
+
This option enables PMIC WRAP related debug messages.
 
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CPU_AMD_SOCKET_C32 || cpu/amd/agesa/family15 || bool ||  ||  
+
| CONSOLE_SERIAL_MVMAP2315_UART_ADDRESS || soc/marvell/mvmap2315 || hex ||  ||  
AMD C32 Socket
+
Map the UART to the respective MMIO address
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL || cpu/amd/agesa/family15 || bool || Redirect AGESA IDS_HDT_CONSOLE to serial console ||  
+
| TTYS0_BAUD || soc/marvell/mvmap2315 || int || ||  
This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console.
+
Baud rate for the UART
 
 
Warning: Only enable this option when debuging or tracing AMD AGESA code.
 
 
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FORCE_AM1_SOCKET_SUPPORT || cpu/amd/agesa/family16kb || bool ||  ||  
+
| IPQ_QFN_PART || soc/qualcomm/ipq40xx || bool ||  ||  
Force AGESA to ignore package type mismatch between CPU and northbridge
+
Is the SoC a QFN part (as opposed to a BGA part)
in memory code. This enables Socket AM1 support with current AGESA
 
version for Kabini platform.
 
Enable this option only if you have Socket AM1 board.
 
Note that the AGESA release shipped with coreboot does not officially
 
support the AM1 socket. Selecting this option might damage your hardware.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| XIP_ROM_SIZE || cpu/amd/pi || hex || ||  
+
| SBL_ELF || soc/qualcomm/ipq40xx || string || file name of the QCA SBL ELF ||  
Overwride the default write through caching size as 1M Bytes.
+
The path and filename of the binary blob containing
On some AMD platforms, one socket supports 2 or more kinds of
+
ipq40xx early initialization code, as supplied by the
processor family, compiling several CPU families agesa code
+
vendor.
will increase the romstage size.
 
In order to execute romstage in place on the flash ROM,
 
more space is required to be set as write through caching.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PARALLEL_MP || cpu/x86 || bool || ||  
+
| SBL_UTIL_PATH || soc/qualcomm/ipq40xx || string || Path for utils to combine SBL_ELF and bootblock ||  
This option uses common MP infrastructure for bringing up APs
+
Path for utils to combine SBL_ELF and bootblock
in parallel. It additionally provides a more flexible mechanism
 
for sequencing the steps of bringing up the APs.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PARALLEL_MP_AP_WORK || cpu/x86 || bool || ||  
+
| SBL_BLOB || soc/qualcomm/ipq806x || string || file name of the Qualcomm SBL blob ||  
Allow APs to do other work after initialization instead of going
+
The path and filename of the binary blob containing
to sleep.
+
ipq806x early initialization code, as supplied by the
 +
vendor.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| LAPIC_MONOTONIC_TIMER || cpu/x86 || bool || ||  
+
| RK3399_SPREAD_SPECTRUM_DDR || soc/rockchip/rk3399 || bool || Spread-spectrum DDR clock ||  
Expose monotonic time using the local APIC.
+
Select Spread Spectrum Modulator (SSMOD) is a fully-digital circuit
 +
used to modulate the frequency of the Silicon Creations’ Fractional
 +
PLL in order to reduce EMI.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| TSC_CONSTANT_RATE || cpu/x86 || bool || ||  
+
| || || (comment) || || CPU ||
This option asserts that the TSC ticks at a known constant rate.
+
|- bgcolor="#eeeeee"
Therefore, no TSC calibration is required.
+
| RESET_ON_INVALID_RAMSTAGE_CACHE || cpu/intel/haswell || bool || Reset the system on S3 wake when ramstage cache invalid. ||  
 +
The haswell romstage code caches the loaded ramstage program
 +
in SMM space. On S3 wake the romstage will copy over a fresh
 +
ramstage that was cached in the SMM space. This option determines
 +
the action to take when the ramstage cache is invalid. If selected
 +
the system will reset otherwise the ramstage will be reloaded from
 +
cbfs.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| TSC_MONOTONIC_TIMER || cpu/x86 || bool ||  ||  
+
| CPU_INTEL_FIRMWARE_INTERFACE_TABLE || cpu/intel/fit || None ||  ||  
Expose monotonic time using the TSC.
+
This option selects building a Firmware Interface Table (FIT).
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| TSC_SYNC_LFENCE || cpu/x86 || bool ||  ||  
+
| CPU_INTEL_NUM_FIT_ENTRIES || cpu/intel/fit || int ||  ||  
The CPU driver should select this if the CPU needs
+
This option selects the number of empty entries in the FIT table.
to execute an lfence instruction in order to synchronize
 
rdtsc. This is true for all modern AMD CPUs.
 
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| TSC_SYNC_MFENCE || cpu/x86 || bool ||  ||  
+
| CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED || cpu/intel/turbo || None ||  ||  
The CPU driver should select this if the CPU needs
+
This option indicates that the turbo mode setting is not package
to execute an mfence instruction in order to synchronize
+
scoped. i.e. enable_turbo() needs to be called on not just the bsp
rdtsc. This is true for all modern Intel CPUs.
 
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NO_FIXED_XIP_ROM_SIZE || cpu/x86 || bool || ||  
+
| SET_VMX_LOCK_BIT || cpu/intel/common || bool || Set lock bit after configuring VMX ||  
The XIP_ROM_SIZE Kconfig variable is used globally on x86
+
Although the Intel manual says you must set the lock bit in addition
with the assumption that all chipsets utilize this value.
+
to the VMX bit in order for VMX to work, this isn't strictly true, so
For the chipsets which do not use the variable it can lead
+
we have the option to leave it unlocked and allow the OS (e.g. Linux)
to unnecessary alignment constraints in cbfs for romstage.
+
to manage things itself. This is beneficial for testing purposes as
Therefore, allow those chipsets a path to not be burdened.
+
there is no need to reflash the firmware just to toggle the lock bit.
 +
However, leaving the lock bit unset will break Windows' detection of
 +
VMX support and built-in virtualization features like Hyper-V.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SMM_MODULE_HEAP_SIZE || cpu/x86 || hex || ||  
+
| GEODE_VSA_FILE || cpu/amd/geode_lx || bool || Add a VSA image ||  
This option determines the size of the heap within the SMM handler
+
Select this option if you have an AMD Geode LX vsa that you would
modules.
+
like to add to your ROM.
  
||
+
You will be able to specify the location and file name of the
|- bgcolor="#eeeeee"
+
image later.
| SERIALIZED_SMM_INITIALIZATION || cpu/x86 || bool ||  ||
 
On some CPUs, there is a race condition in SMM.
 
This can occur when both hyperthreads change SMM state
 
variables in parallel without coordination.
 
Setting this option serializes the SMM initialization
 
to avoid an ugly hang in the boot process at the cost
 
of a slightly longer boot time.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| X86_AMD_FIXED_MTRRS || cpu/x86 || bool || ||  
+
| VSA_FILENAME || cpu/amd/geode_lx || string || AMD Geode LX VSA path and filename ||  
This option informs the MTRR code to use the RdMem and WrMem fields
+
The path and filename of the file to use as VSA.
in the fixed MTRR MSRs.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PLATFORM_USES_FSP1_0 || cpu/x86 || bool ||  ||  
+
| XIP_ROM_SIZE || cpu/amd/agesa || hex ||  ||  
Selected for Intel processors/platform combinations that use the
+
Overwride the default write through caching size as 1M Bytes.
Intel Firmware Support Package (FSP) 1.0 for initialization.
+
On some AMD platforms, one socket supports 2 or more kinds of
 +
processor family, compiling several CPU families agesa code
 +
will increase the romstage size.
 +
In order to execute romstage in place on the flash ROM,
 +
more space is required to be set as write through caching.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING || cpu/x86 || bool || ||  
+
| ENABLE_MRC_CACHE || cpu/amd/agesa || bool || Use cached memory configuration ||  
On certain platforms a boot speed gain can be realized if mirroring
+
Try to restore memory training results
the payload data stored in non-volatile storage. On x86 systems the
+
from non-volatile memory.
payload would typically live in a memory-mapped SPI part. Copying
 
the SPI contents to RAM before performing the load can speed up
 
the boot process.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_SETS_MSRS || cpu/x86 || bool ||  ||  
+
| FORCE_AM1_SOCKET_SUPPORT || cpu/amd/agesa/family16kb || bool ||  ||  
The SoC requires different access methods for reading and writing
+
Force AGESA to ignore package type mismatch between CPU and northbridge
the MSRs. Use SoC specific routines to handle the MSR access.
+
in memory code. This enables Socket AM1 support with current AGESA
 +
version for Kabini platform.
 +
Enable this option only if you have Socket AM1 board.
 +
Note that the AGESA release shipped with coreboot does not officially
 +
support the AM1 socket. Selecting this option might damage your hardware.
  
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| XIP_ROM_SIZE || cpu/amd/pi || hex ||  ||
 +
Overwride the default write through caching size as 1M Bytes.
 +
On some AMD platforms, one socket supports 2 or more kinds of
 +
processor family, compiling several CPU families agesa code
 +
will increase the romstage size.
 +
In order to execute romstage in place on the flash ROM,
 +
more space is required to be set as write through caching.
 +
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NO_CAR_GLOBAL_MIGRATION || cpu || bool ||  ||  
+
| PARALLEL_MP || cpu/x86 || bool ||  ||  
This option is selected if there is no need to migrate CAR globals.
+
This option uses common MP infrastructure for bringing up APs
All stages which use CAR globals can directly access the variables
+
in parallel. It additionally provides a more flexible mechanism
from their linked addresses.
+
for sequencing the steps of bringing up the APs.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SMP || cpu || bool ||  ||  
+
| PARALLEL_MP_AP_WORK || cpu/x86 || bool ||  ||  
This option is used to enable certain functions to make coreboot
+
Allow APs to do other work after initialization instead of going
work correctly on symmetric multi processor (SMP) systems.
+
to sleep.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| AP_SIPI_VECTOR || cpu || hex ||  ||  
+
| LAPIC_MONOTONIC_TIMER || cpu/x86 || bool ||  ||  
This must equal address of ap_sipi_vector from bootblock build.
+
Expose monotonic time using the local APIC.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MMX || cpu || bool ||  ||  
+
| TSC_CONSTANT_RATE || cpu/x86 || bool ||  ||  
Select MMX in your socket or model Kconfig if your CPU has MMX
+
This option asserts that the TSC ticks at a known constant rate.
streaming SIMD instructions. ROMCC can build more efficient
+
Therefore, no TSC calibration is required.
code if it can spill to MMX registers.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SSE || cpu || bool ||  ||  
+
| TSC_MONOTONIC_TIMER || cpu/x86 || bool ||  ||  
Select SSE in your socket or model Kconfig if your CPU has SSE
+
Expose monotonic time using the TSC.
streaming SIMD instructions. ROMCC can build more efficient
 
code if it can spill to SSE (aka XMM) registers.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SSE2 || cpu || bool ||  ||  
+
| TSC_SYNC_LFENCE || cpu/x86 || bool ||  ||  
Select SSE2 in your socket or model Kconfig if your CPU has SSE2
+
The CPU driver should select this if the CPU needs
streaming SIMD instructions. Some parts of coreboot can be built
+
to execute an lfence instruction in order to synchronize
with more efficient code if SSE2 instructions are available.
+
rdtsc. This is true for all modern AMD CPUs.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| USES_MICROCODE_HEADER_FILES || cpu || bool ||  ||  
+
| TSC_SYNC_MFENCE || cpu/x86 || bool ||  ||  
This is selected by a board or chipset to set the default for the
+
The CPU driver should select this if the CPU needs
microcode source choice to a list of external microcode headers
+
to execute an mfence instruction in order to synchronize
 +
rdtsc. This is true for all modern Intel CPUs.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CPU_MICROCODE_CBFS_GENERATE || cpu || bool || Generate from tree ||  
+
| NO_FIXED_XIP_ROM_SIZE || cpu/x86 || bool || ||  
Select this option if you want microcode updates to be assembled when
+
The XIP_ROM_SIZE Kconfig variable is used globally on x86
building coreboot and included in the final image as a separate CBFS
+
with the assumption that all chipsets utilize this value.
file. Microcode will not be hard-coded into ramstage.
+
For the chipsets which do not use the variable it can lead
 
+
to unnecessary alignment constraints in cbfs for romstage.
The microcode file may be removed from the ROM image at a later
+
Therefore, allow those chipsets a path to not be burdened.
time with cbfstool, if desired.
 
 
 
If unsure, select this option.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CPU_MICROCODE_CBFS_EXTERNAL_HEADER || cpu || bool || Include external microcode header files ||  
+
| SMM_MODULE_HEAP_SIZE || cpu/x86 || hex || ||  
Select this option if you want to include external c header files
+
This option determines the size of the heap within the SMM handler
containing the CPU microcode. This will be included as a separate
+
modules.
file in CBFS.
 
 
 
A word of caution: only select this option if you are sure the
 
microcode that you have is newer than the microcode shipping with
 
coreboot.
 
 
 
The microcode file may be removed from the ROM image at a later
 
time with cbfstool, if desired.
 
 
 
If unsure, select "Generate from tree"
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CPU_MICROCODE_CBFS_NONE || cpu || bool || Do not include microcode updates ||  
+
| SERIALIZED_SMM_INITIALIZATION || cpu/x86 || bool || ||  
Select this option if you do not want CPU microcode included in CBFS.
+
On some CPUs, there is a race condition in SMM.
Note that for some CPUs, the microcode is hard-coded into the source
+
This can occur when both hyperthreads change SMM state
tree and is not loaded from CBFS. In this case, microcode will still
+
variables in parallel without coordination.
be updated. There is a push to move all microcode to CBFS, but this
+
Setting this option serializes the SMM initialization
change is not implemented for all CPUs.
+
to avoid an ugly hang in the boot process at the cost
 
+
of a slightly longer boot time.
This option currently applies to:
 
- Intel SandyBridge/IvyBridge
 
- VIA Nano
 
 
 
Microcode may be added to the ROM image at a later time with cbfstool,
 
if desired.
 
 
 
If unsure, select "Generate from tree"
 
 
 
The GOOD:
 
Microcode updates intend to solve issues that have been discovered
 
after CPU production. The expected effect is that systems work as
 
intended with the updated microcode, but we have also seen cases where
 
issues were solved by not applying microcode updates.
 
 
 
The BAD:
 
Note that some operating system include these same microcode patches,
 
so you may need to also disable microcode updates in your operating
 
system for this option to have an effect.
 
 
 
The UGLY:
 
A word of CAUTION: some CPUs depend on microcode updates to function
 
correctly. Not updating the microcode may leave the CPU operating at
 
less than optimal performance, or may cause outright hangups.
 
There are CPUs where coreboot cannot properly initialize the CPU
 
without microcode updates
 
For example, if running with the factory microcode, some Intel
 
SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs
 
will hang when changing the frequency.
 
 
 
Make sure you have a way of flashing the ROM externally before
 
selecting this option.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CPU_MICROCODE_MULTIPLE_FILES || cpu || bool ||  ||  
+
| X86_AMD_FIXED_MTRRS || cpu/x86 || bool ||  ||  
Select this option to install separate microcode container files into
+
This option informs the MTRR code to use the RdMem and WrMem fields
CBFS instead of using the traditional monolithic microcode file format.
+
in the fixed MTRR MSRs.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CPU_MICROCODE_HEADER_FILES || cpu || string || List of space separated microcode header files with the path ||  
+
| PLATFORM_USES_FSP1_0 || cpu/x86 || bool || ||  
A list of one or more microcode header files with path from the
+
Selected for Intel processors/platform combinations that use the
coreboot directory. These should be separated by spaces.
+
Intel Firmware Support Package (FSP) 1.0 for initialization.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CPU_UCODE_BINARIES || cpu || string || Microcode binary path and filename ||  
+
| MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING || cpu/x86 || bool || ||  
Some platforms have microcode in the blobs directory, and these can
+
On certain platforms a boot speed gain can be realized if mirroring
be hardcoded in the makefiles. For platforms with microcode
+
the payload data stored in non-volatile storage. On x86 systems the
binaries that aren't in the makefile, set this option to pull
+
payload would typically live in a memory-mapped SPI part. Copying
in the microcode.
+
the SPI contents to RAM before performing the load can speed up
 +
the boot process.
  
This should contain the full path of the file for one or more
+
||
microcode binary files to include, separated by spaces.
+
|- bgcolor="#eeeeee"
 
+
| SOC_SETS_MSRS || cpu/x86 || bool ||  ||
If unsure, leave this blank.
+
The SoC requires different access methods for reading and writing
 +
the MSRs.  Use SoC specific routines to handle the MSR access.
  
 
||
 
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || Northbridge ||
+
| NO_CAR_GLOBAL_MIGRATION || cpu || bool || ||  
|- bgcolor="#eeeeee"
+
This option is selected if there is no need to migrate CAR globals.
| I945_LVDS || northbridge/intel/i945 || string ||  ||
+
All stages which use CAR globals can directly access the variables
Selected by mainboards that use native graphics initialization
+
from their linked addresses.
for the LVDS port. A linear framebuffer is only supported for
 
LVDS.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| OVERRIDE_CLOCK_DISABLE || northbridge/intel/i945 || bool ||  ||  
+
| SMP || cpu || bool ||  ||  
Usually system firmware turns off system memory clock
+
This option is used to enable certain functions to make coreboot
signals to unused SO-DIMM slots to reduce EMI and power
+
work correctly on symmetric multi processor (SMP) systems.
consumption.
 
However, some boards do not like unused clock signals to
 
be disabled.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MAXIMUM_SUPPORTED_FREQUENCY || northbridge/intel/i945 || int ||  ||  
+
| AP_SIPI_VECTOR || cpu || hex ||  ||  
If non-zero, this designates the maximum DDR frequency
+
This must equal address of ap_sipi_vector from bootblock build.
the board supports, despite what the chipset should be
 
capable of.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CHECK_SLFRCS_ON_RESUME || northbridge/intel/i945 || int ||  ||  
+
| MMX || cpu || bool ||  ||  
On some boards it may be neccessary to hard reset early
+
Select MMX in your socket or model Kconfig if your CPU has MMX
during resume from S3 if the SLFRCS register indicates that
+
streaming SIMD instructions. ROMCC can build more efficient
a memory channel is not guaranteed to be in self-refresh.
+
code if it can spill to MMX registers.
On other boards the check always creates a false positive,
 
effectively making it impossible to resume.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| USE_NATIVE_RAMINIT || northbridge/intel/sandybridge || bool || Use native raminit ||  
+
| SSE || cpu || bool || ||  
Select if you want to use coreboot implementation of raminit rather than
+
Select SSE in your socket or model Kconfig if your CPU has SSE
System Agent/MRC.bin. You should answer Y.
+
streaming SIMD instructions. ROMCC can build more efficient
 +
code if it can spill to SSE (aka XMM) registers.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES || northbridge/intel/sandybridge || bool || Ignore vendor programmed fuses that limit max. DRAM frequency ||  
+
| SSE2 || cpu || bool || ||  
Ignore the mainboard's vendor programmed fuses that might limit the
+
Select SSE2 in your socket or model Kconfig if your CPU has SSE2
maximum DRAM frequency. By selecting this option the fuses will be
+
streaming SIMD instructions. Some parts of coreboot can be built
ignored and the only limits on DRAM frequency are set by RAM's SPD and
+
with more efficient code if SSE2 instructions are available.
hard fuses in southbridge's clockgen.
 
Disabled by default as it might causes system instability.
 
Handle with care!
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS || northbridge/intel/sandybridge || bool || Ignore XMP profile max DIMMs per channel ||  
+
| USES_MICROCODE_HEADER_FILES || cpu || bool || ||  
Ignore the max DIMMs per channel restriciton defined in XMP profiles.
+
This is selected by a board or chipset to set the default for the
Disabled by default as it might cause system instability.
+
microcode source choice to a list of external microcode headers
Handle with care!
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MMCONF_BASE_ADDRESS || northbridge/intel/sandybridge || hex || ||  
+
| CPU_MICROCODE_CBFS_GENERATE || cpu || bool || Generate from tree ||  
We can optimize the native case but the MRC blob requires it
+
Select this option if you want microcode updates to be assembled when
to be at 0xf0000000.
+
building coreboot and included in the final image as a separate CBFS
 +
file. Microcode will not be hard-coded into ramstage.
 +
 
 +
The microcode file may be removed from the ROM image at a later
 +
time with cbfstool, if desired.
  
||
+
If unsure, select this option.
|- bgcolor="#eeeeee"
 
| MRC_FILE || northbridge/intel/sandybridge || string || Intel System Agent path and filename ||
 
The path and filename of the file to use as System Agent
 
binary.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DCACHE_RAM_SIZE || northbridge/intel/haswell || hex || ||  
+
| CPU_MICROCODE_CBFS_EXTERNAL_HEADER || cpu || bool || Include external microcode header files ||  
The size of the cache-as-ram region required during bootblock
+
Select this option if you want to include external c header files
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
+
containing the CPU microcode. This will be included as a separate
must add up to a power of 2.
+
file in CBFS.
 +
 
 +
A word of caution: only select this option if you are sure the
 +
microcode that you have is newer than the microcode shipping with
 +
coreboot.
  
||
+
The microcode file may be removed from the ROM image at a later
|- bgcolor="#eeeeee"
+
time with cbfstool, if desired.
| DCACHE_RAM_MRC_VAR_SIZE || northbridge/intel/haswell || hex ||  ||
 
The amount of cache-as-ram region required by the reference code.
 
  
||
+
If unsure, select "Generate from tree"
|- bgcolor="#eeeeee"
 
| DCACHE_RAM_ROMSTAGE_STACK_SIZE || northbridge/intel/haswell || hex ||  ||
 
The amount of anticipated stack usage from the data cache
 
during pre-ram ROM stage execution.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HAVE_MRC || northbridge/intel/haswell || bool || Add a System Agent binary ||  
+
| CPU_MICROCODE_CBFS_NONE || cpu || bool || Do not include microcode updates ||  
Select this option to add a System Agent binary to
+
Select this option if you do not want CPU microcode included in CBFS.
the resulting coreboot image.
+
Note that for some CPUs, the microcode is hard-coded into the source
 +
tree and is not loaded from CBFS. In this case, microcode will still
 +
be updated. There is a push to move all microcode to CBFS, but this
 +
change is not implemented for all CPUs.
  
Note: Without this binary coreboot will not work
+
This option currently applies to:
 +
- Intel SandyBridge/IvyBridge
 +
- VIA Nano
  
||
+
Microcode may be added to the ROM image at a later time with cbfstool,
|- bgcolor="#eeeeee"
+
if desired.
| MRC_FILE || northbridge/intel/haswell || string || Intel System Agent path and filename ||
 
The path and filename of the file to use as System Agent
 
binary.
 
  
||
+
If unsure, select "Generate from tree"
|- bgcolor="#eeeeee"
 
| PRE_GRAPHICS_DELAY || northbridge/intel/haswell || int || Graphics initialization delay in ms ||
 
On some systems, coreboot boots so fast that connected monitors
 
(mostly TVs) won't be able to wake up fast enough to talk to the
 
VBIOS. On those systems we need to wait for a bit before executing
 
the VBIOS.
 
  
||
+
The GOOD:
|- bgcolor="#eeeeee"
+
Microcode updates intend to solve issues that have been discovered
| VGA_BIOS_ID || northbridge/intel/fsp_sandybridge || string ||  ||
+
after CPU production. The expected effect is that systems work as
This is the default PCI ID for the sandybridge/ivybridge graphics
+
intended with the updated microcode, but we have also seen cases where
devices.  This string names the vbios ROM in cbfs.  The following
+
issues were solved by not applying microcode updates.
PCI IDs will be remapped to load this ROM:
 
0x80860102, 0x8086010a, 0x80860112, 0x80860116
 
0x80860122, 0x80860126, 0x80860166
 
  
||
+
The BAD:
|- bgcolor="#eeeeee"
+
Note that some operating system include these same microcode patches,
| FSP_FILE || northbridge/intel/fsp_sandybridge/fsp || string ||  ||
+
so you may need to also disable microcode updates in your operating
The path and filename of the Intel FSP binary for this platform.
+
system for this option to have an effect.
  
||
+
The UGLY:
|- bgcolor="#eeeeee"
+
A word of CAUTION: some CPUs depend on microcode updates to function
| FSP_LOC || northbridge/intel/fsp_sandybridge/fsp || hex || Intel FSP Binary location in CBFS ||
+
correctly. Not updating the microcode may leave the CPU operating at
The location in CBFS that the FSP is located. This must match the
+
less than optimal performance, or may cause outright hangups.
value that is set in the FSP binary. If the FSP needs to be moved,
+
There are CPUs where coreboot cannot properly initialize the CPU
rebase the FSP with the Intel's BCT (tool).
+
without microcode updates
 +
For example, if running with the factory microcode, some Intel
 +
SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs
 +
will hang when changing the frequency.
  
The Ivy Bridge Processor/Panther Point FSP is built with a preferred
+
Make sure you have a way of flashing the ROM externally before
base address of 0xFFF80000
+
selecting this option.
  
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_MICROCODE_MULTIPLE_FILES || cpu || bool ||  ||
 +
Select this option to install separate microcode container files into
 +
CBFS instead of using the traditional monolithic microcode file format.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SDRAMPWR_4DIMM || northbridge/intel/i440bx || bool || ||  
+
| CPU_MICROCODE_HEADER_FILES || cpu || string || List of space separated microcode header files with the path ||  
This option affects how the SDRAMC register is programmed.
+
A list of one or more microcode header files with path from the
Memory clock signals will not be routed properly if this option
+
coreboot directory. These should be separated by spaces.
is set wrong.
 
 
 
If your board has 4 DIMM slots, you must use select this option, in
 
your Kconfig file of the board. On boards with 3 DIMM slots,
 
do _not_ select this option.
 
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SET_TSEG_1MB || northbridge/intel/fsp_rangeley || bool || 1 MB ||  
+
| CPU_UCODE_BINARIES || cpu || string || Microcode binary path and filename ||  
Set the TSEG area to 1 MB.
+
Some platforms have microcode in the blobs directory, and these can
 +
be hardcoded in the makefiles.  For platforms with microcode
 +
binaries that aren't in the makefile, set this option to pull
 +
in the microcode.
 +
 
 +
This should contain the full path of the file for one or more
 +
microcode binary files to include, separated by spaces.
 +
 
 +
If unsure, leave this blank.
  
 
||
 
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Northbridge ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SET_TSEG_2MB || northbridge/intel/fsp_rangeley || bool || 2 MB ||  
+
| I945_LVDS || northbridge/intel/i945 || string || ||  
Set the TSEG area to 2 MB.
+
Selected by mainboards that use native graphics initialization
 +
for the LVDS port. A linear framebuffer is only supported for
 +
LVDS.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SET_TSEG_4MB || northbridge/intel/fsp_rangeley || bool || 4 MB ||  
+
| OVERRIDE_CLOCK_DISABLE || northbridge/intel/i945 || bool || ||  
Set the TSEG area to 4 MB.
+
Usually system firmware turns off system memory clock
 +
signals to unused SO-DIMM slots to reduce EMI and power
 +
consumption.
 +
However, some boards do not like unused clock signals to
 +
be disabled.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SET_TSEG_8MB || northbridge/intel/fsp_rangeley || bool || 8 MB ||  
+
| MAXIMUM_SUPPORTED_FREQUENCY || northbridge/intel/i945 || int || ||  
Set the TSEG area to 8 MB.
+
If non-zero, this designates the maximum DDR frequency
 +
the board supports, despite what the chipset should be
 +
capable of.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_FILE || northbridge/intel/fsp_rangeley/fsp || string ||  ||  
+
| CHECK_SLFRCS_ON_RESUME || northbridge/intel/i945 || int ||  ||  
The path and filename of the Intel FSP binary for this platform.
+
On some boards it may be neccessary to hard reset early
 +
during resume from S3 if the SLFRCS register indicates that
 +
a memory channel is not guaranteed to be in self-refresh.
 +
On other boards the check always creates a false positive,
 +
effectively making it impossible to resume.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_LOC || northbridge/intel/fsp_rangeley/fsp || hex || ||  
+
| USE_NATIVE_RAMINIT || northbridge/intel/sandybridge || bool || Use native raminit ||  
The location in CBFS that the FSP is located. This must match the
+
Select if you want to use coreboot implementation of raminit rather than
value that is set in the FSP binary. If the FSP needs to be moved,
+
System Agent/MRC.bin. You should answer Y.
rebase the FSP with Intel's BCT (tool).
 
  
The Rangeley FSP is built with a preferred base address of 0xFFF80000
+
||
 +
|- bgcolor="#eeeeee"
 +
| NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES || northbridge/intel/sandybridge || bool || Ignore vendor programmed fuses that limit max. DRAM frequency ||
 +
Ignore the mainboard's vendor programmed fuses that might limit the
 +
maximum DRAM frequency. By selecting this option the fuses will be
 +
ignored and the only limits on DRAM frequency are set by RAM's SPD and
 +
hard fuses in southbridge's clockgen.
 +
Disabled by default as it might causes system instability.
 +
Handle with care!
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOTTOMIO_POSITION || northbridge/amd/pi || hex || Bottom of 32-bit IO space ||  
+
| NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS || northbridge/intel/sandybridge || bool || Ignore XMP profile max DIMMs per channel ||  
If PCI peripherals with big BARs are connected to the system
+
Ignore the max DIMMs per channel restriciton defined in XMP profiles.
the bottom of the IO must be decreased to allocate such
+
Disabled by default as it might cause system instability.
devices.
+
Handle with care!
 
 
Declare the beginning of the 128MB-aligned MMIO region. This
 
option is useful when PCI peripherals requesting large address
 
ranges are present.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VGA_BIOS_ID || northbridge/amd/pi/00630F01 || string ||  ||  
+
| MMCONF_BASE_ADDRESS || northbridge/intel/sandybridge || hex ||  ||  
The default VGA BIOS PCI vendor/device ID should be set to the
+
The MRC blob requires it to be at 0xf0000000.
result of the map_oprom_vendev() function in northbridge.c.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VGA_BIOS_ID || northbridge/amd/pi/00730F01 || string || ||  
+
| MRC_FILE || northbridge/intel/sandybridge || string || Intel System Agent path and filename ||  
The default VGA BIOS PCI vendor/device ID should be set to the
+
The path and filename of the file to use as System Agent
result of the map_oprom_vendev() function in northbridge.c.
+
binary.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VGA_BIOS_ID || northbridge/amd/pi/00660F01 || string ||  ||  
+
| DCACHE_RAM_SIZE || northbridge/intel/haswell || hex ||  ||  
The default VGA BIOS PCI vendor/device ID should be set to the
+
The size of the cache-as-ram region required during bootblock
result of the map_oprom_vendev() function in northbridge.c.
+
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
 +
must add up to a power of 2.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| REDIRECT_NBCIMX_TRACE_TO_SERIAL || northbridge/amd/cimx/rd890 || bool || Redirect AMD Northbridge CIMX Trace to serial console ||  
+
| DCACHE_RAM_MRC_VAR_SIZE || northbridge/intel/haswell || hex || ||  
This Option allows you to redirect the AMD Northbridge CIMX
+
The amount of cache-as-ram region required by the reference code.
Trace debug information to the serial console.
 
 
 
Warning: Only enable this option when debuging or tracing AMD CIMX code.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NO_MMCONF_SUPPORT || northbridge/amd/amdk8 || bool ||  ||  
+
| DCACHE_RAM_ROMSTAGE_STACK_SIZE || northbridge/intel/haswell || hex ||  ||  
If you want to remove this, you need to make sure any access to CPU
+
The amount of anticipated stack usage from the data cache
nodes 0:18.0, 0:19.0, ...  continue to use PCI IO config access.
+
during pre-ram ROM stage execution.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VGA_BIOS_ID || northbridge/amd/agesa/family16kb || string || ||  
+
| HAVE_MRC || northbridge/intel/haswell || bool || Add a System Agent binary ||  
The default VGA BIOS PCI vendor/device ID should be set to the
+
Select this option to add a System Agent binary to
result of the map_oprom_vendev() function in northbridge.c.
+
the resulting coreboot image.
 +
 
 +
Note: Without this binary coreboot will not work
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SVI_HIGH_FREQ || northbridge/amd/amdfam10 || bool || ||  
+
| MRC_FILE || northbridge/intel/haswell || string || Intel System Agent path and filename ||  
Select this for boards with a Voltage Regulator able to operate
+
The path and filename of the file to use as System Agent
at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.
+
binary.
  
 
||
 
||
|- bgcolor="#6699dd"
 
! align="left" | Menu: HyperTransport setup || || || ||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SVI_HIGH_FREQ || northbridge/amd/amdfam10 || bool || HyperTransport downlink width ||  
+
| PRE_GRAPHICS_DELAY || northbridge/intel/haswell || int || Graphics initialization delay in ms ||  
This option sets the maximum permissible HyperTransport
+
On some systems, coreboot boots so fast that connected monitors
downlink width.
+
(mostly TVs) won't be able to wake up fast enough to talk to the
 +
VBIOS. On those systems we need to wait for a bit before executing
 +
the VBIOS.
  
Use of this option will only limit the autodetected HT width.
+
||
It will not (and cannot) increase the width beyond the autodetected
+
|- bgcolor="#eeeeee"
limits.
+
| VGA_BIOS_ID || northbridge/intel/fsp_sandybridge || string ||  ||
 
+
This is the default PCI ID for the sandybridge/ivybridge graphics
This is primarily used to work around poorly designed or laid out HT
+
devices. This string names the vbios ROM in cbfs.  The following
traces on certain motherboards.
+
PCI IDs will be remapped to load this ROM:
 +
0x80860102, 0x8086010a, 0x80860112, 0x80860116
 +
0x80860122, 0x80860126, 0x80860166
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| LIMIT_HT_DOWN_WIDTH_16 || northbridge/amd/amdfam10 || bool || HyperTransport uplink width ||  
+
| FSP_FILE || northbridge/intel/fsp_sandybridge/fsp || string || ||  
This option sets the maximum permissible HyperTransport
+
The path and filename of the Intel FSP binary for this platform.
uplink width.
 
 
 
Use of this option will only limit the autodetected HT width.
 
It will not (and cannot) increase the width beyond the autodetected
 
limits.
 
 
 
This is primarily used to work around poorly designed or laid out HT
 
traces on certain motherboards.
 
  
 
||
 
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || Southbridge ||
+
| FSP_LOC || northbridge/intel/fsp_sandybridge/fsp || hex || Intel FSP Binary location in CBFS ||
 +
The location in CBFS that the FSP is located. This must match the
 +
value that is set in the FSP binary.  If the FSP needs to be moved,
 +
rebase the FSP with the Intel's BCT (tool).
 +
 
 +
The Ivy Bridge Processor/Panther Point FSP is built with a preferred
 +
base address of 0xFFF80000
 +
 
 +
||
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/ibexpeak || bool ||  ||  
+
| SDRAMPWR_4DIMM || northbridge/intel/i440bx || bool ||  ||  
If you set this option to y, the serial IRQ machine will be
+
This option affects how the SDRAMC register is programmed.
operated in continuous mode.
+
Memory clock signals will not be routed properly if this option
 +
is set wrong.
 +
 
 +
If your board has 4 DIMM slots, you must use select this option, in
 +
your Kconfig file of the board. On boards with 3 DIMM slots,
 +
do _not_ select this option.
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| INTEL_LYNXPOINT_LP || southbridge/intel/lynxpoint || bool || ||  
+
| SET_TSEG_1MB || northbridge/intel/fsp_rangeley || bool || 1 MB ||  
Set this option to y for Lynxpont LP (Haswell ULT).
+
Set the TSEG area to 1 MB.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/lynxpoint || bool || ||  
+
| SET_TSEG_2MB || northbridge/intel/fsp_rangeley || bool || 2 MB ||  
If you set this option to y, the serial IRQ machine will be
+
Set the TSEG area to 2 MB.
operated in continuous mode.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ME_MBP_CLEAR_LATE || southbridge/intel/lynxpoint || bool || Defer wait for ME MBP Cleared ||  
+
| SET_TSEG_4MB || northbridge/intel/fsp_rangeley || bool || 4 MB ||  
If you set this option to y, the Management Engine driver
+
Set the TSEG area to 4 MB.
will defer waiting for the MBP Cleared indicator until the
 
finalize step.  This can speed up boot time if the ME takes
 
a long time to indicate this status.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FINALIZE_USB_ROUTE_XHCI || southbridge/intel/lynxpoint || bool || Route all ports to XHCI controller in finalize step ||  
+
| SET_TSEG_8MB || northbridge/intel/fsp_rangeley || bool || 8 MB ||  
If you set this option to y, the USB ports will be routed
+
Set the TSEG area to 8 MB.
to the XHCI controller during the finalize SMM callback.
 
 
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/bd82x6x || bool ||  ||  
+
| FSP_FILE || northbridge/intel/fsp_rangeley/fsp || string ||  ||  
If you set this option to y, the serial IRQ machine will be
+
The path and filename of the Intel FSP binary for this platform.
operated in continuous mode.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| LOCK_SPI_FLASH_RO || southbridge/intel/bd82x6x || bool || Write-protect all flash sections ||  
+
| FSP_LOC || northbridge/intel/fsp_rangeley/fsp || hex || ||  
Select this if you want to write-protect the whole firmware flash
+
The location in CBFS that the FSP is located. This must match the
chip. The locking will take place during the chipset lockdown, which
+
value that is set in the FSP binary.  If the FSP needs to be moved,
is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set)
+
rebase the FSP with Intel's BCT (tool).
or has to be triggered later (e.g. by the payload or the OS).
 
  
NOTE: If you trigger the chipset lockdown unconditionally,
+
The Rangeley FSP is built with a preferred base address of 0xFFF80000
you won't be able to write to the flash chip using the
 
internal programmer any more.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| LOCK_SPI_FLASH_NO_ACCESS || southbridge/intel/bd82x6x || bool || Write-protect all flash sections and read-protect non-BIOS sections ||  
+
| BOTTOMIO_POSITION || northbridge/amd/pi || hex || Bottom of 32-bit IO space ||  
Select this if you want to protect the firmware flash against all
+
If PCI peripherals with big BARs are connected to the system
further accesses (with the exception of the memory mapped BIOS re-
+
the bottom of the IO must be decreased to allocate such
gion which is always readable). The locking will take place during
+
devices.
the chipset lockdown, which is either triggered by coreboot (when
 
INTEL_CHIPSET_LOCKDOWN is set) or has to be triggered later (e.g.
 
by the payload or the OS).
 
  
NOTE: If you trigger the chipset lockdown unconditionally,
+
Declare the beginning of the 128MB-aligned MMIO region.  This
you won't be able to write to the flash chip using the
+
option is useful when PCI peripherals requesting large address
internal programmer any more.
+
ranges are present.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/fsp_bd82x6x || bool ||  ||  
+
| VGA_BIOS_ID || northbridge/amd/pi/00630F01 || string ||  ||  
If you set this option to y, the serial IRQ machine will be
+
The default VGA BIOS PCI vendor/device ID should be set to the
operated in continuous mode.
+
result of the map_oprom_vendev() function in northbridge.c.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| INTEL_CHIPSET_LOCKDOWN || southbridge/intel/common || bool || Lock down chipset in coreboot ||  
+
| VGA_BIOS_ID || northbridge/amd/pi/00730F01 || string || ||  
Some registers within host bridge on particular chipsets should be
+
The default VGA BIOS PCI vendor/device ID should be set to the
locked down on each normal boot path (done by either coreboot or payload)
+
result of the map_oprom_vendev() function in northbridge.c.
and S3 resume (always done by coreboot). Select this to let coreboot
 
to do this on normal boot path.
 
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/fsp_rangeley || bool ||  ||  
+
| VGA_BIOS_ID || northbridge/amd/pi/00660F01 || string ||  ||  
If you set this option to y, the serial IRQ machine will be
+
The default VGA BIOS PCI vendor/device ID should be set to the
operated in continuous mode.
+
result of the map_oprom_vendev() function in northbridge.c.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| IFD_BIN_PATH || southbridge/intel/fsp_rangeley || string || ||  
+
| REDIRECT_NBCIMX_TRACE_TO_SERIAL || northbridge/amd/cimx/rd890 || bool || Redirect AMD Northbridge CIMX Trace to serial console ||  
The path and filename to the descriptor.bin file.
+
This Option allows you to redirect the AMD Northbridge CIMX
 +
Trace debug information to the serial console.
 +
 
 +
Warning: Only enable this option when debuging or tracing AMD CIMX code.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/fsp_i89xx || bool ||  ||  
+
| NO_MMCONF_SUPPORT || northbridge/amd/amdk8 || bool ||  ||  
If you set this option to y, the serial IRQ machine will be
+
If you want to remove this, you need to make sure any access to CPU
operated in continuous mode.
+
nodes 0:18.0, 0:19.0, ...  continue to use PCI IO config access.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HUDSON_XHCI_ENABLE || southbridge/amd/pi/hudson || bool || Enable Hudson XHCI Controller ||  
+
| VGA_BIOS_ID || northbridge/amd/agesa/family16kb || string || ||  
The XHCI controller must be enabled and the XHCI firmware
+
The default VGA BIOS PCI vendor/device ID should be set to the
must be added in order to have USB 3.0 support configured
+
result of the map_oprom_vendev() function in northbridge.c.
by coreboot. The OS will be responsible for enabling the XHCI
 
controller if the the XHCI firmware is available but the
 
XHCI controller is not enabled by coreboot.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HUDSON_XHCI_FWM || southbridge/amd/pi/hudson || bool || Add xhci firmware ||  
+
| SVI_HIGH_FREQ || northbridge/amd/amdfam10 || bool || ||  
Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0
+
Select this for boards with a Voltage Regulator able to operate
 +
at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.
  
 
||
 
||
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: HyperTransport setup || || || ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HUDSON_IMC_FWM || southbridge/amd/pi/hudson || bool || Add IMC firmware ||  
+
| SVI_HIGH_FREQ || northbridge/amd/amdfam10 || bool || HyperTransport downlink width ||  
Add Hudson 2/3/4 IMC Firmware to support the onboard fan control
+
This option sets the maximum permissible HyperTransport
 +
downlink width.
 +
 
 +
Use of this option will only limit the autodetected HT width.
 +
It will not (and cannot) increase the width beyond the autodetected
 +
limits.
 +
 
 +
This is primarily used to work around poorly designed or laid out HT
 +
traces on certain motherboards.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HUDSON_GEC_FWM || southbridge/amd/pi/hudson || bool || ||  
+
| LIMIT_HT_DOWN_WIDTH_16 || northbridge/amd/amdfam10 || bool || HyperTransport uplink width ||  
Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC.
+
This option sets the maximum permissible HyperTransport
Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
+
uplink width.
 +
 
 +
Use of this option will only limit the autodetected HT width.
 +
It will not (and cannot) increase the width beyond the autodetected
 +
limits.
 +
 
 +
This is primarily used to work around poorly designed or laid out HT
 +
traces on certain motherboards.
  
 
||
 
||
 +
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HUDSON_SATA_MODE || southbridge/amd/pi/hudson || int || SATA Mode ||  
+
| || || (comment) || || Southbridge ||
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
+
|- bgcolor="#eeeeee"
The default is NATIVE.
+
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/ibexpeak || bool || ||  
0: NATIVE mode does not require a ROM.
+
If you set this option to y, the serial IRQ machine will be
1: RAID mode must have the two ROM files.
+
operated in continuous mode.
2: AHCI may work with or without AHCI ROM. It depends on the payload support.
 
For example, seabios does not require the AHCI ROM.
 
3: LEGACY IDE
 
4: IDE to AHCI
 
5: AHCI7804: ROM Required, and AMD driver required in the OS.
 
6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || NATIVE ||
+
| INTEL_LYNXPOINT_LP || southbridge/intel/lynxpoint || bool || ||  
 +
Set this option to y for Lynxpont LP (Haswell ULT).
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || RAID ||
+
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/lynxpoint || bool || ||  
|- bgcolor="#eeeeee"
+
If you set this option to y, the serial IRQ machine will be
| || || (comment) || || AHCI ||
+
operated in continuous mode.
|- bgcolor="#eeeeee"
 
| || || (comment) || || LEGACY IDE ||
 
|- bgcolor="#eeeeee"
 
| || || (comment) || || IDE to AHCI ||
 
|- bgcolor="#eeeeee"
 
| || || (comment) || || AHCI7804 ||
 
|- bgcolor="#eeeeee"
 
| || || (comment) || || IDE to AHCI7804 ||
 
|- bgcolor="#eeeeee"
 
| RAID_ROM_ID || southbridge/amd/pi/hudson || string || RAID device PCI IDs ||  
 
1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| RAID_MISC_ROM_POSITION || southbridge/amd/pi/hudson || hex || RAID Misc ROM Position ||  
+
| ME_MBP_CLEAR_LATE || southbridge/intel/lynxpoint || bool || Defer wait for ME MBP Cleared ||  
The RAID ROM requires that the MISC ROM is located between the range
+
If you set this option to y, the Management Engine driver
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
+
will defer waiting for the MBP Cleared indicator until the
The CONFIG_ROM_SIZE must be larger than 0x100000.
+
finalize step. This can speed up boot time if the ME takes
 +
a long time to indicate this status.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HUDSON_LEGACY_FREE || southbridge/amd/pi/hudson || bool || System is legacy free ||  
+
| FINALIZE_USB_ROUTE_XHCI || southbridge/intel/lynxpoint || bool || Route all ports to XHCI controller in finalize step ||  
Select y if there is no keyboard controller in the system.
+
If you set this option to y, the USB ports will be routed
This sets variables in AGESA and ACPI.
+
to the XHCI controller during the finalize SMM callback.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| AZ_PIN || southbridge/amd/pi/hudson || hex ||  ||  
+
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/bd82x6x || bool ||  ||  
bit 1,0 - pin 0
+
If you set this option to y, the serial IRQ machine will be
bit 3,2 - pin 1
+
operated in continuous mode.
bit 5,4 - pin 2
 
bit 7,6 - pin 3
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| AMDFW_OUTSIDE_CBFS || southbridge/amd/pi/hudson || hex || ||  
+
| LOCK_SPI_FLASH_RO || southbridge/intel/bd82x6x || bool || Write-protect all flash sections ||  
The AMDFW (PSP) is typically locatable in cbfs.  Select this
+
Select this if you want to write-protect the whole firmware flash
option to manually attach the generated amdfw.rom at an
+
chip. The locking will take place during the chipset lockdown, which
offset of 0x20000 from the bottom of the coreboot ROM image.
+
is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set)
 +
or has to be triggered later (e.g. by the payload or the OS).
 +
 
 +
NOTE: If you trigger the chipset lockdown unconditionally,
 +
you won't be able to write to the flash chip using the
 +
internal programmer any more.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SERIRQ_CONTINUOUS_MODE || southbridge/amd/pi/hudson || bool || ||  
+
| LOCK_SPI_FLASH_NO_ACCESS || southbridge/intel/bd82x6x || bool || Write-protect all flash sections and read-protect non-BIOS sections ||  
Set this option to y for serial IRQ in continuous mode.
+
Select this if you want to protect the firmware flash against all
Otherwise it is in quiet mode.
+
further accesses (with the exception of the memory mapped BIOS re-
 +
gion which is always readable). The locking will take place during
 +
the chipset lockdown, which is either triggered by coreboot (when
 +
INTEL_CHIPSET_LOCKDOWN is set) or has to be triggered later (e.g.
 +
by the payload or the OS).
 +
 
 +
NOTE: If you trigger the chipset lockdown unconditionally,
 +
you won't be able to write to the flash chip using the
 +
internal programmer any more.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HUDSON_ACPI_IO_BASE || southbridge/amd/pi/hudson || hex ||  ||  
+
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/fsp_bd82x6x || bool ||  ||  
Base address for the ACPI registers.
+
If you set this option to y, the serial IRQ machine will be
This value must match the hardcoded value of AGESA.
+
operated in continuous mode.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HUDSON_UART || southbridge/amd/pi/hudson || bool || UART controller on Kern ||  
+
| INTEL_CHIPSET_LOCKDOWN || southbridge/intel/common || bool || Lock down chipset in coreboot ||  
There are two UART controllers in Kern.
+
Some registers within host bridge on particular chipsets should be
The UART registers are memory-mapped. UART
+
locked down on each normal boot path (done by either coreboot or payload)
controller 0 registers range from FEDC_6000h
+
and S3 resume (always done by coreboot). Select this to let coreboot
to FEDC_6FFFh. UART controller 1 registers
+
to do this on normal boot path.
range from FEDC_8000h to FEDC_8FFFh.
 
 
 
||
 
  
 
||
 
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SATA_CONTROLLER_MODE || southbridge/amd/cimx/sb700 || hex ||  ||  
+
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/fsp_rangeley || bool ||  ||  
0x0 = Native IDE mode.
+
If you set this option to y, the serial IRQ machine will be
0x1 = RAID mode.
+
operated in continuous mode.
0x2 = AHCI mode.
 
0x3 = Legacy IDE mode.
 
0x4 = IDE->AHCI mode.
 
0x5 = AHCI mode as 7804 ID (AMD driver).
 
0x6 = IDE->AHCI mode as 7804 ID (AMD driver).
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PCIB_ENABLE || southbridge/amd/cimx/sb700 || bool ||  ||  
+
| IFD_BIN_PATH || southbridge/intel/fsp_rangeley || string ||  ||  
n = Disable PCI Bridge Device 14 Function 4.
+
The path and filename to the descriptor.bin file.
y = Enable PCI Bridge Device 14 Function 4.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ACPI_SCI_IRQ || southbridge/amd/cimx/sb700 || hex ||  ||  
+
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/fsp_i89xx || bool ||  ||  
Set SCI IRQ to 9.
+
If you set this option to y, the serial IRQ machine will be
 +
operated in continuous mode.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| REDIRECT_SBCIMX_TRACE_TO_SERIAL || southbridge/amd/cimx/sb700 || bool || Redirect AMD Southbridge CIMX Trace to serial console ||  
+
| HUDSON_XHCI_ENABLE || southbridge/amd/pi/hudson || bool || Enable Hudson XHCI Controller ||  
This Option allows you to redirect the AMD Southbridge CIMX Trace
+
The XHCI controller must be enabled and the XHCI firmware
debug information to the serial console.
+
must be added in order to have USB 3.0 support configured
 
+
by coreboot. The OS will be responsible for enabling the XHCI
Warning: Only enable this option when debuging or tracing AMD CIMX code.
+
controller if the the XHCI firmware is available but the
 +
XHCI controller is not enabled by coreboot.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_IDE_COMBINED_MODE || southbridge/amd/cimx/sb800 || bool || Enable SATA IDE combined mode ||  
+
| HUDSON_XHCI_FWM || southbridge/amd/pi/hudson || bool || Add xhci firmware ||  
If Combined Mode is enabled. IDE controller is exposed and
+
Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0
SATA controller has control over Port0 through Port3,
 
IDE controller has control over Port4 and Port5.
 
 
 
If Combined Mode is disabled, IDE controller is hidden and
 
SATA controller has full control of all 6 Ports when operating in non-IDE mode.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| IDE_COMBINED_MODE || southbridge/amd/cimx/sb800 || hex || SATA Mode ||  
+
| HUDSON_IMC_FWM || southbridge/amd/pi/hudson || bool || Add IMC firmware ||  
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
+
Add Hudson 2/3/4 IMC Firmware to support the onboard fan control
The default is AHCI.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SB800_SATA_IDE || southbridge/amd/cimx/sb800 || bool || NATIVE ||  
+
| HUDSON_GEC_FWM || southbridge/amd/pi/hudson || bool || ||  
NATIVE does not require a ROM.
+
Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC.
 +
Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SB800_SATA_AHCI || southbridge/amd/cimx/sb800 || bool || AHCI ||  
+
| HUDSON_SATA_MODE || southbridge/amd/pi/hudson || int || SATA Mode ||  
AHCI is the default and may work with or without AHCI ROM. It depends on the payload support.
+
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
 +
The default is NATIVE.
 +
0: NATIVE mode does not require a ROM.
 +
1: RAID mode must have the two ROM files.
 +
2: AHCI may work with or without AHCI ROM. It depends on the payload support.
 
For example, seabios does not require the AHCI ROM.
 
For example, seabios does not require the AHCI ROM.
 +
3: LEGACY IDE
 +
4: IDE to AHCI
 +
5: AHCI7804: ROM Required, and AMD driver required in the OS.
 +
6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SB800_SATA_RAID || southbridge/amd/cimx/sb800 || bool || RAID ||  
+
| || || (comment) || || NATIVE ||
sb800 RAID mode must have the two required ROM files.
+
|- bgcolor="#eeeeee"
 
+
| || || (comment) || || RAID ||
||
+
|- bgcolor="#eeeeee"
 +
| || || (comment) || || AHCI ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || LEGACY IDE ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || IDE to AHCI ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || AHCI7804 ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || IDE to AHCI7804 ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| RAID_ROM_ID || southbridge/amd/cimx/sb800 || string || RAID device PCI IDs ||  
+
| RAID_ROM_ID || southbridge/amd/pi/hudson || string || RAID device PCI IDs ||  
1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode
+
1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| RAID_MISC_ROM_POSITION || southbridge/amd/cimx/sb800 || hex || RAID Misc ROM Position ||  
+
| RAID_MISC_ROM_POSITION || southbridge/amd/pi/hudson || hex || RAID Misc ROM Position ||  
 
The RAID ROM requires that the MISC ROM is located between the range
 
The RAID ROM requires that the MISC ROM is located between the range
 
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
 
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
The CONFIG_ROM_SIZE must larger than 0x100000.
+
The CONFIG_ROM_SIZE must be larger than 0x100000.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SB800_IMC_FWM || southbridge/amd/cimx/sb800 || bool || Add IMC firmware ||  
+
| HUDSON_LEGACY_FREE || southbridge/amd/pi/hudson || bool || System is legacy free ||  
Add SB800 / Hudson 1 IMC Firmware to support the onboard fan control.
+
Select y if there is no keyboard controller in the system.
 +
This sets variables in AGESA and ACPI.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SB800_FWM_AT_FFFA0000 || southbridge/amd/cimx/sb800 || bool || 0xFFFA0000 ||  
+
| AZ_PIN || southbridge/amd/pi/hudson || hex || ||  
The IMC and GEC ROMs requires a 'signature' located at one of several
+
bit 1,0 - pin 0
fixed locations in memory.  The location used shouldn't matter, just
+
bit 3,2 - pin 1
select an area that doesn't conflict with anything else.
+
bit 5,4 - pin 2
 +
bit 7,6 - pin 3
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SB800_FWM_AT_FFF20000 || southbridge/amd/cimx/sb800 || bool || 0xFFF20000 ||  
+
| AMDFW_OUTSIDE_CBFS || southbridge/amd/pi/hudson || hex || ||  
The IMC and GEC ROMs requires a 'signature' located at one of several
+
The AMDFW (PSP) is typically locatable in cbfsSelect this
fixed locations in memoryThe location used shouldn't matter, just
+
option to manually attach the generated amdfw.rom at an
select an area that doesn't conflict with anything else.
+
offset of 0x20000 from the bottom of the coreboot ROM image.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SB800_FWM_AT_FFE20000 || southbridge/amd/cimx/sb800 || bool || 0xFFE20000 ||  
+
| SERIRQ_CONTINUOUS_MODE || southbridge/amd/pi/hudson || bool || ||  
The IMC and GEC ROMs requires a 'signature' located at one of several
+
Set this option to y for serial IRQ in continuous mode.
fixed locations in memory. The location used shouldn't matter, just
+
Otherwise it is in quiet mode.
select an area that doesn't conflict with anything else.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SB800_FWM_AT_FFC20000 || southbridge/amd/cimx/sb800 || bool || 0xFFC20000 ||  
+
| HUDSON_ACPI_IO_BASE || southbridge/amd/pi/hudson || hex || ||  
The IMC and GEC ROMs requires a 'signature' located at one of several
+
Base address for the ACPI registers.
fixed locations in memory. The location used shouldn't matter, just
+
This value must match the hardcoded value of AGESA.
select an area that doesn't conflict with anything else.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SB800_FWM_AT_FF820000 || southbridge/amd/cimx/sb800 || bool || 0xFF820000 ||  
+
| HUDSON_UART || southbridge/amd/pi/hudson || bool || UART controller on Kern ||  
The IMC and GEC ROMs requires a 'signature' located at one of several
+
There are two UART controllers in Kern.
fixed locations in memory. The location used shouldn't matter, just
+
The UART registers are memory-mapped. UART
select an area that doesn't conflict with anything else.
+
controller 0 registers range from FEDC_6000h
 +
to FEDC_6FFFh. UART controller 1 registers
 +
range from FEDC_8000h to FEDC_8FFFh.
 +
 
 +
||
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EHCI_BAR || southbridge/amd/cimx/sb800 || hex || Fan Control ||  
+
| ENABLE_IDE_COMBINED_MODE || southbridge/amd/cimx/sb800 || bool || Enable SATA IDE combined mode ||  
Select the method of SB800 fan control to be used. None would be
+
If Combined Mode is enabled. IDE controller is exposed and
for either fixed maximum speed fans connected to the SB800 or for
+
SATA controller has control over Port0 through Port3,
an external chip controlling the fan speeds.  Manual control sets
+
IDE controller has control over Port4 and Port5.
up the SB800 fan control registers. IMC fan control uses the SB800
+
 
IMC to actively control the fan speeds.
+
If Combined Mode is disabled, IDE controller is hidden and
 +
SATA controller has full control of all 6 Ports when operating in non-IDE mode.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SB800_NO_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || None ||  
+
| IDE_COMBINED_MODE || southbridge/amd/cimx/sb800 || hex || SATA Mode ||  
No SB800 Fan control - Do not set up the SB800 fan control registers.
+
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
 +
The default is AHCI.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SB800_MANUAL_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || Manual ||  
+
| SB800_SATA_IDE || southbridge/amd/cimx/sb800 || bool || NATIVE ||  
Configure the SB800 fan control registers in devicetree.cb.
+
NATIVE does not require a ROM.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SB800_IMC_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || IMC Based ||  
+
| SB800_SATA_AHCI || southbridge/amd/cimx/sb800 || bool || AHCI ||  
Set up the SB800 to use the IMC based Fan controller. This requires
+
AHCI is the default and may work with or without AHCI ROM. It depends on the payload support.
the IMC ROM from AMD.  Configure the registers in devicetree.cb.
+
For example, seabios does not require the AHCI ROM.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SATA_CONTROLLER_MODE || southbridge/amd/cimx/sb900 || hex || ||  
+
| SB800_SATA_RAID || southbridge/amd/cimx/sb800 || bool || RAID ||  
0x0 = Native IDE mode.
+
sb800 RAID mode must have the two required ROM files.
0x1 = RAID mode.
 
0x2 = AHCI mode.
 
0x3 = Legacy IDE mode.
 
0x4 = IDE->AHCI mode.
 
0x5 = AHCI mode as 7804 ID (AMD driver).
 
0x6 = IDE->AHCI mode as 7804 ID (AMD driver).
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PCIB_ENABLE || southbridge/amd/cimx/sb900 || bool || ||  
+
| RAID_ROM_ID || southbridge/amd/cimx/sb800 || string || RAID device PCI IDs ||  
n = Disable PCI Bridge Device 14 Function 4.
+
1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode
y = Enable PCI Bridge Device 14 Function 4.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ACPI_SCI_IRQ || southbridge/amd/cimx/sb900 || hex || ||  
+
| RAID_MISC_ROM_POSITION || southbridge/amd/cimx/sb800 || hex || RAID Misc ROM Position ||  
Set SCI IRQ to 9.
+
The RAID ROM requires that the MISC ROM is located between the range
 +
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
 +
The CONFIG_ROM_SIZE must larger than 0x100000.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EXT_CONF_SUPPORT || southbridge/amd/sr5650 || bool || Enable PCI-E MMCONFIG support ||  
+
| SB800_IMC_FWM || southbridge/amd/cimx/sb800 || bool || Add IMC firmware ||  
Select to enable PCI-E MMCONFIG support on the SR5650.
+
Add SB800 / Hudson 1 IMC Firmware to support the onboard fan control.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EXT_CONF_SUPPORT || southbridge/amd/rs690 || bool || ||  
+
| SB800_FWM_AT_FFFA0000 || southbridge/amd/cimx/sb800 || bool || 0xFFFA0000 ||  
Select if RS690 should be setup to support MMCONF.
+
The IMC and GEC ROMs requires a 'signature' located at one of several
 +
fixed locations in memory.  The location used shouldn't matter, just
 +
select an area that doesn't conflict with anything else.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HUDSON_XHCI_ENABLE || southbridge/amd/agesa/hudson || bool || Enable Hudson XHCI Controller ||  
+
| SB800_FWM_AT_FFF20000 || southbridge/amd/cimx/sb800 || bool || 0xFFF20000 ||  
The XHCI controller must be enabled and the XHCI firmware
+
The IMC and GEC ROMs requires a 'signature' located at one of several
must be added in order to have USB 3.0 support configured
+
fixed locations in memory. The location used shouldn't matter, just
by coreboot. The OS will be responsible for enabling the XHCI
+
select an area that doesn't conflict with anything else.
controller if the the XHCI firmware is available but the
 
XHCI controller is not enabled by coreboot.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HUDSON_XHCI_FWM || southbridge/amd/agesa/hudson || bool || Add xhci firmware ||  
+
| SB800_FWM_AT_FFE20000 || southbridge/amd/cimx/sb800 || bool || 0xFFE20000 ||  
Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0
+
The IMC and GEC ROMs requires a 'signature' located at one of several
 +
fixed locations in memory.  The location used shouldn't matter, just
 +
select an area that doesn't conflict with anything else.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HUDSON_IMC_FWM || southbridge/amd/agesa/hudson || bool || Add imc firmware ||  
+
| SB800_FWM_AT_FFC20000 || southbridge/amd/cimx/sb800 || bool || 0xFFC20000 ||  
Add Hudson 2/3/4 IMC Firmware to support the onboard fan control
+
The IMC and GEC ROMs requires a 'signature' located at one of several
 +
fixed locations in memory.  The location used shouldn't matter, just
 +
select an area that doesn't conflict with anything else.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HUDSON_GEC_FWM || southbridge/amd/agesa/hudson || bool || ||  
+
| SB800_FWM_AT_FF820000 || southbridge/amd/cimx/sb800 || bool || 0xFF820000 ||  
Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC.
+
The IMC and GEC ROMs requires a 'signature' located at one of several
Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
+
fixed locations in memory. The location used shouldn't matter, just
 +
select an area that doesn't conflict with anything else.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HUDSON_SATA_MODE || southbridge/amd/agesa/hudson || int || SATA Mode ||  
+
| EHCI_BAR || southbridge/amd/cimx/sb800 || hex || Fan Control ||  
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
+
Select the method of SB800 fan control to be used. None would be
The default is NATIVE.
+
for either fixed maximum speed fans connected to the SB800 or for
0: NATIVE mode does not require a ROM.
+
an external chip controlling the fan speeds. Manual control sets
1: RAID mode must have the two ROM files.
+
up the SB800 fan control registers. IMC fan control uses the SB800
2: AHCI may work with or without AHCI ROM. It depends on the payload support.
+
IMC to actively control the fan speeds.
For example, seabios does not require the AHCI ROM.
 
3: LEGACY IDE
 
4: IDE to AHCI
 
5: AHCI7804: ROM Required, and AMD driver required in the OS.
 
6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || NATIVE ||
+
| SB800_NO_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || None ||  
 +
No SB800 Fan control - Do not set up the SB800 fan control registers.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || RAID ||
+
| SB800_MANUAL_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || Manual ||  
|- bgcolor="#eeeeee"
+
Configure the SB800 fan control registers in devicetree.cb.
| || || (comment) || || AHCI ||
 
|- bgcolor="#eeeeee"
 
| || || (comment) || || LEGACY IDE ||
 
|- bgcolor="#eeeeee"
 
| || || (comment) || || IDE to AHCI ||
 
|- bgcolor="#eeeeee"
 
| || || (comment) || || AHCI7804 ||
 
|- bgcolor="#eeeeee"
 
| || || (comment) || || IDE to AHCI7804 ||
 
|- bgcolor="#eeeeee"
 
| RAID_ROM_ID || southbridge/amd/agesa/hudson || string || RAID device PCI IDs ||  
 
1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| RAID_MISC_ROM_POSITION || southbridge/amd/agesa/hudson || hex || RAID Misc ROM Position ||  
+
| SB800_IMC_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || IMC Based ||  
The RAID ROM requires that the MISC ROM is located between the range
+
Set up the SB800 to use the IMC based Fan controller.  This requires
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
+
the IMC ROM from AMD.  Configure the registers in devicetree.cb.
The CONFIG_ROM_SIZE must be larger than 0x100000.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HUDSON_LEGACY_FREE || southbridge/amd/agesa/hudson || bool || System is legacy free ||  
+
| SATA_CONTROLLER_MODE || southbridge/amd/cimx/sb900 || hex || ||  
Select y if there is no keyboard controller in the system.
+
0x0 = Native IDE mode.
This sets variables in AGESA and ACPI.
+
0x1 = RAID mode.
 +
0x2 = AHCI mode.
 +
0x3 = Legacy IDE mode.
 +
0x4 = IDE->AHCI mode.
 +
0x5 = AHCI mode as 7804 ID (AMD driver).
 +
0x6 = IDE->AHCI mode as 7804 ID (AMD driver).
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| AZ_PIN || southbridge/amd/agesa/hudson || hex ||  ||  
+
| PCIB_ENABLE || southbridge/amd/cimx/sb900 || bool ||  ||  
bit 1,0 - pin 0
+
n = Disable PCI Bridge Device 14 Function 4.
bit 3,2 - pin 1
+
y = Enable PCI Bridge Device 14 Function 4.
bit 5,4 - pin 2
+
 
bit 7,6 - pin 3
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOUTHBRIDGE_AMD_SB700_33MHZ_SPI || southbridge/amd/sb700 || bool || Enable high speed SPI clock ||  
+
| ACPI_SCI_IRQ || southbridge/amd/cimx/sb900 || hex || ||  
When set, the SPI clock will run at 33MHz instead
+
Set SCI IRQ to 9.
of the compatibility mode 16.5MHz.  Note that not
 
all ROMs are capable of 33MHz operation, so you
 
will need to verify this option is appropriate for
 
the ROM you are using.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NO_EARLY_SMBUS || southbridge/amd/cs5536 || bool || ||  
+
| EXT_CONF_SUPPORT || southbridge/amd/sr5650 || bool || Enable PCI-E MMCONFIG support ||  
Skip the CS5536 early SMBUS initialization.
+
Select to enable PCI-E MMCONFIG support on the SR5650.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EHCI_BAR || southbridge/amd/sb600 || hex || SATA Mode ||  
+
| EXT_CONF_SUPPORT || southbridge/amd/rs690 || bool || ||  
Select the mode in which SATA should be driven. IDE or AHCI.
+
Select if RS690 should be setup to support MMCONF.
The default is IDE.
 
  
config SATA_MODE_IDE
 
bool "IDE"
 
 
config SATA_MODE_AHCI
 
bool "AHCI"
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || Super I/O ||
+
| HUDSON_XHCI_ENABLE || southbridge/amd/agesa/hudson || bool || Enable Hudson XHCI Controller ||  
|- bgcolor="#eeeeee"
+
The XHCI controller must be enabled and the XHCI firmware
| SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG || superio/ite/common || bool || ||  
+
must be added in order to have USB 3.0 support configured
Enable extended, 16-bit wide tacho counters.
+
by coreboot. The OS will be responsible for enabling the XHCI
 +
controller if the the XHCI firmware is available but the
 +
XHCI controller is not enabled by coreboot.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SUPERIO_ITE_ENV_CTRL_8BIT_PWM || superio/ite/common || bool || ||  
+
| HUDSON_XHCI_FWM || southbridge/amd/agesa/hudson || bool || Add xhci firmware ||  
PWM duty cycles are set in 8-bit registers (instead of 7 bit).
+
Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 || superio/ite/common || bool || ||  
+
| HUDSON_IMC_FWM || southbridge/amd/agesa/hudson || bool || Add imc firmware ||  
The second FAN controller has a separate frequency setting.
+
Add Hudson 2/3/4 IMC Firmware to support the onboard fan control
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || Embedded Controllers ||
+
| HUDSON_GEC_FWM || southbridge/amd/agesa/hudson || bool ||  ||  
|- bgcolor="#eeeeee"
+
Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC.
| EC_ACPI || ec/acpi || bool ||  ||  
+
Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
ACPI Embedded Controller interface. Mostly found in laptops.
 
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC || ec/google/chromeec || bool || ||  
+
| HUDSON_SATA_MODE || southbridge/amd/agesa/hudson || int || SATA Mode ||  
Google's Chrome EC
+
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
 +
The default is NATIVE.
 +
0: NATIVE mode does not require a ROM.
 +
1: RAID mode must have the two ROM files.
 +
2: AHCI may work with or without AHCI ROM. It depends on the payload support.
 +
For example, seabios does not require the AHCI ROM.
 +
3: LEGACY IDE
 +
4: IDE to AHCI
 +
5: AHCI7804: ROM Required, and AMD driver required in the OS.
 +
6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_ACPI_MEMMAP || ec/google/chromeec || bool || ||  
+
| || || (comment) || || NATIVE ||
When defined, ACPI accesses EC memmap data on ports 66h/62h. When
 
not defined, the memmap data is instead accessed on 900h-9ffh via
 
the LPC bus.
 
 
 
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_BOARDID || ec/google/chromeec || bool || ||  
+
| || || (comment) || || RAID ||
Provides common routine for reading boardid from Chrome EC.
 
 
 
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_I2C || ec/google/chromeec || bool || ||  
+
| || || (comment) || || AHCI ||
Google's Chrome EC via I2C bus.
 
 
 
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_I2C_PROTO3 || ec/google/chromeec || bool || ||  
+
| || || (comment) || || LEGACY IDE ||
Use only proto3 for i2c EC communication.
+
|- bgcolor="#eeeeee"
 +
| || || (comment) || || IDE to AHCI ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || AHCI7804 ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || IDE to AHCI7804 ||
 +
|- bgcolor="#eeeeee"
 +
| RAID_ROM_ID || southbridge/amd/agesa/hudson || string || RAID device PCI IDs ||  
 +
1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_LPC || ec/google/chromeec || bool || ||  
+
| RAID_MISC_ROM_POSITION || southbridge/amd/agesa/hudson || hex || RAID Misc ROM Position ||  
Google Chrome EC via LPC bus.
+
The RAID ROM requires that the MISC ROM is located between the range
 +
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
 +
The CONFIG_ROM_SIZE must be larger than 0x100000.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_MEC || ec/google/chromeec || bool || ||  
+
| HUDSON_LEGACY_FREE || southbridge/amd/agesa/hudson || bool || System is legacy free ||  
Microchip EC variant for LPC register access.
+
Select y if there is no keyboard controller in the system.
 +
This sets variables in AGESA and ACPI.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_PD || ec/google/chromeec || bool ||  ||  
+
| AZ_PIN || southbridge/amd/agesa/hudson || hex ||  ||  
Indicates that Google's Chrome USB PD chip is present.
+
bit 1,0 - pin 0
 
+
bit 3,2 - pin 1
 +
bit 5,4 - pin 2
 +
bit 7,6 - pin 3
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_SPI || ec/google/chromeec || bool || ||  
+
| SOUTHBRIDGE_AMD_SB700_33MHZ_SPI || southbridge/amd/sb700 || bool || Enable high speed SPI clock ||  
Google's Chrome EC via SPI bus.
+
When set, the SPI clock will run at 33MHz instead
 +
of the compatibility mode 16.5MHz.  Note that not
 +
all ROMs are capable of 33MHz operation, so you
 +
will need to verify this option is appropriate for
 +
the ROM you are using.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US || ec/google/chromeec || int ||  ||  
+
| NO_EARLY_SMBUS || southbridge/amd/cs5536 || bool ||  ||  
Force delay after asserting /CS to allow EC to wakeup.
+
Skip the CS5536 early SMBUS initialization.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_BOARDNAME || ec/google/chromeec || string || Chrome EC board name for EC ||  
+
| EHCI_BAR || southbridge/amd/sb600 || hex || SATA Mode ||  
The board name used in the Chrome EC code base to build
+
Select the mode in which SATA should be driven. IDE or AHCI.
the EC firmware. If set, the coreboot build with also
+
The default is IDE.
build the EC firmware and add it to the image.
 
  
||
+
config SATA_MODE_IDE
|- bgcolor="#eeeeee"
+
bool "IDE"
| EC_GOOGLE_CHROMEEC_PD_BOARDNAME || ec/google/chromeec || string || Chrome EC board name for PD ||
 
The board name used in the Chrome EC code base to build
 
the PD firmware.  If set, the coreboot build with also
 
build the EC firmware and add it to the image.
 
  
 +
config SATA_MODE_AHCI
 +
bool "AHCI"
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_RTC || ec/google/chromeec || bool || Enable Chrome OS EC RTC ||  
+
| || || (comment) || || Super I/O ||
Enable support for the real-time clock on the Chrome OS EC. This
+
|- bgcolor="#eeeeee"
uses the EC_CMD_RTC_GET_VALUE command to read the current time.
+
| SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG || superio/ite/common || bool || ||  
 +
Enable extended, 16-bit wide tacho counters.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_FIRMWARE_NONE || ec/google/chromeec || bool || No EC firmware is included ||  
+
| SUPERIO_ITE_ENV_CTRL_8BIT_PWM || superio/ite/common || bool || ||  
Disable building and including any EC firmware in the image.
+
PWM duty cycles are set in 8-bit registers (instead of 7 bit).
  
config EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL
+
||
bool "External EC firmware is included"
+
|- bgcolor="#eeeeee"
help
+
| SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 || superio/ite/common || bool ||  ||
Include EC firmware binary in the image from an external source.
+
The second FAN controller has a separate frequency setting.
It is expected to be built externally.
 
  
config EC_GOOGLE_CHROMEEC_FIRMWARE_BUILTIN
+
||
bool "Builtin EC firmware is included"
+
|- bgcolor="#eeeeee"
help
+
| || || (comment) || || Embedded Controllers ||
Build and include EC firmware binary in the image.
+
|- bgcolor="#eeeeee"
 +
| EC_ACPI || ec/acpi || bool ||  ||
 +
ACPI Embedded Controller interface. Mostly found in laptops.
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_FIRMWARE_FILE || ec/google/chromeec || string || Chrome EC firmware path and filename ||  
+
| EC_GOOGLE_CHROMEEC || ec/google/chromeec || bool || ||  
The path and filename of the EC firmware file to use.
+
Google's Chrome EC
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_PD_FIRMWARE_NONE || ec/google/chromeec || bool || No PD firmware is included ||  
+
| EC_GOOGLE_CHROMEEC_ACPI_MEMMAP || ec/google/chromeec || bool || ||  
Disable building and including any PD firmware in the image.
+
When defined, ACPI accesses EC memmap data on ports 66h/62h. When
 +
not defined, the memmap data is instead accessed on 900h-9ffh via
 +
the LPC bus.
  
config EC_GOOGLE_CHROMEEC_PD_FIRMWARE_EXTERNAL
+
||
bool "External PD firmware is included"
+
|- bgcolor="#eeeeee"
help
+
| EC_GOOGLE_CHROMEEC_BOARDID || ec/google/chromeec || bool ||  ||
Include PD firmware binary in the image from an external source.
+
Provides common routine for reading boardid from Chrome EC.
It is expected to be built externally.
 
 
 
config EC_GOOGLE_CHROMEEC_PD_FIRMWARE_BUILTIN
 
bool "Builtin PD firmware is included"
 
help
 
Build and include PD firmware binary in the image.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_PD_FIRMWARE_FILE || ec/google/chromeec || string || Chrome EC firmware path and filename for PD ||  
+
| EC_GOOGLE_CHROMEEC_I2C || ec/google/chromeec || bool || ||  
The path and filename of the PD firmware file to use.
+
Google's Chrome EC via I2C bus.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_SWITCHES || ec/google/chromeec || bool ||  ||  
+
| EC_GOOGLE_CHROMEEC_I2C_PROTO3 || ec/google/chromeec || bool ||  ||  
Enable support for Chrome OS mode switches provided by the Chrome OS
+
Use only proto3 for i2c EC communication.
EC.
 
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EC_QUANTA_IT8518 || ec/quanta/it8518 || bool ||  ||  
+
| EC_GOOGLE_CHROMEEC_LPC || ec/google/chromeec || bool ||  ||  
Interface to QUANTA IT8518 Embedded Controller.
+
Google Chrome EC via LPC bus.
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EC_QUANTA_ENE_KB3940Q || ec/quanta/ene_kb3940q || bool ||  ||  
+
| EC_GOOGLE_CHROMEEC_MEC || ec/google/chromeec || bool ||  ||  
Interface to QUANTA ENE KB3940Q Embedded Controller.
+
Microchip EC variant for LPC register access.
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EC_HP_KBC1126 || ec/hp/kbc1126 || bool ||  ||  
+
| EC_GOOGLE_CHROMEEC_PD || ec/google/chromeec || bool ||  ||  
Interface to SMSC KBC1126 embedded controller in HP laptops.
+
Indicates that Google's Chrome USB PD chip is present.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || Please select the following otherwise your laptop cannot be powered on. ||
+
| EC_GOOGLE_CHROMEEC_SPI || ec/google/chromeec || bool || ||  
|- bgcolor="#eeeeee"
+
Google's Chrome EC via SPI bus.
| KBC1126_FIRMWARE || ec/hp/kbc1126 || bool || Add firmware images for KBC1126 EC ||  
 
Select this option to add the two firmware blobs for KBC1126.
 
You need these two blobs to power on your machine.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| KBC1126_FW1 || ec/hp/kbc1126 || string || KBC1126 firmware #1 path and filename ||  
+
| EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US || ec/google/chromeec || int || ||  
The path and filename of the file to use as KBC1126 firmware #1.
+
Force delay after asserting /CS to allow EC to wakeup.
You can use util/kbc1126/kbc1126_ec_dump to dump it from the
 
vendor firmware.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| KBC1126_FW2 || ec/hp/kbc1126 || string || KBC1126 filename #2 path and filename ||  
+
| EC_GOOGLE_CHROMEEC_BOARDNAME || ec/google/chromeec || string || Chrome EC board name for EC ||  
The path and filename of the file to use as KBC1126 firmware #2.
+
The board name used in the Chrome EC code base to build
You can use util/kbc1126/kbc1126_ec_dump to dump it from the
+
the EC firmware. If set, the coreboot build with also
vendor firmware.
+
build the EC firmware and add it to the image.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| H8_BEEP_ON_DEATH || ec/lenovo/h8 || bool || Beep on fatal error ||  
+
| EC_GOOGLE_CHROMEEC_PD_BOARDNAME || ec/google/chromeec || string || Chrome EC board name for PD ||  
Beep when encountered a fatal error.
+
The board name used in the Chrome EC code base to build
 +
the PD firmware.  If set, the coreboot build with also
 +
build the EC firmware and add it to the image.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| H8_FLASH_LEDS_ON_DEATH || ec/lenovo/h8 || bool || Flash LEDs on fatal error ||  
+
| EC_GOOGLE_CHROMEEC_RTC || ec/google/chromeec || bool || Enable Chrome OS EC RTC ||  
Flash all LEDs when encountered a fatal error.
+
Enable support for the real-time clock on the Chrome OS EC. This
 +
uses the EC_CMD_RTC_GET_VALUE command to read the current time.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EC_RODA_IT8518 || ec/roda/it8518 || bool || ||  
+
| EC_GOOGLE_CHROMEEC_FIRMWARE_NONE || ec/google/chromeec || bool || No EC firmware is included ||  
Interface to IT8518 embedded controller in Roda notebooks.
+
Disable building and including any EC firmware in the image.
 +
 
 +
config EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL
 +
bool "External EC firmware is included"
 +
help
 +
Include EC firmware binary in the image from an external source.
 +
It is expected to be built externally.
 +
 
 +
config EC_GOOGLE_CHROMEEC_FIRMWARE_BUILTIN
 +
bool "Builtin EC firmware is included"
 +
help
 +
Build and include EC firmware binary in the image.
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EC_SMSC_MEC1308 || ec/smsc/mec1308 || bool || ||  
+
| EC_GOOGLE_CHROMEEC_FIRMWARE_FILE || ec/google/chromeec || string || Chrome EC firmware path and filename ||  
Shared memory mailbox interface to SMSC MEC1308 Embedded Controller.
+
The path and filename of the EC firmware file to use.
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EC_PURISM_LIBREM || ec/purism/librem || bool || ||  
+
| EC_GOOGLE_CHROMEEC_PD_FIRMWARE_NONE || ec/google/chromeec || bool || No PD firmware is included ||  
Purism Librem EC
+
Disable building and including any PD firmware in the image.
 +
 
 +
config EC_GOOGLE_CHROMEEC_PD_FIRMWARE_EXTERNAL
 +
bool "External PD firmware is included"
 +
help
 +
Include PD firmware binary in the image from an external source.
 +
It is expected to be built externally.
 +
 
 +
config EC_GOOGLE_CHROMEEC_PD_FIRMWARE_BUILTIN
 +
bool "Builtin PD firmware is included"
 +
help
 +
Build and include PD firmware binary in the image.
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EC_COMPAL_ENE932 || ec/compal/ene932 || bool ||  ||  
+
| EC_GOOGLE_CHROMEEC_PD_FIRMWARE_FILE || ec/google/chromeec || string || Chrome EC firmware path and filename for PD ||
Interface to COMPAL ENE932 Embedded Controller.
+
The path and filename of the PD firmware file to use.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_SWITCHES || ec/google/chromeec || bool ||  ||  
 +
Enable support for Chrome OS mode switches provided by the Chrome OS
 +
EC.
  
 
||
 
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EC_KONTRON_IT8516E || ec/kontron/it8516e || bool ||  ||  
+
| EC_QUANTA_IT8518 || ec/quanta/it8518 || bool ||  ||  
Kontron uses an ITE IT8516E on the KTQM77. Its firmware might
+
Interface to QUANTA IT8518 Embedded Controller.
come from Fintek (mentioned as Finte*c* somewhere in their Linux
 
driver).
 
The KTQM77 is an embedded board and the IT8516E seems to be
 
only used for fan control and GPIO.
 
  
 
||
 
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || Intel FSP ||
+
| EC_QUANTA_ENE_KB3940Q || ec/quanta/ene_kb3940q || bool || ||  
|- bgcolor="#eeeeee"
+
Interface to QUANTA ENE KB3940Q Embedded Controller.
| HAVE_FSP_BIN || drivers/intel/fsp1_0 || bool || Use Intel Firmware Support Package ||  
 
Select this option to add an Intel FSP binary to
 
the resulting coreboot image.
 
 
 
Note: Without this binary, coreboot builds relying on the FSP
 
will not boot
 
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_FILE || drivers/intel/fsp1_0 || string || Intel FSP binary path and filename ||  
+
| EC_HP_KBC1126 || ec/hp/kbc1126 || bool || ||  
The path and filename of the Intel FSP binary for this platform.
+
Interface to SMSC KBC1126 embedded controller in HP laptops.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_LOC || drivers/intel/fsp1_0 || hex || Intel FSP Binary location in CBFS ||  
+
| || || (comment) || || Please select the following otherwise your laptop cannot be powered on. ||
The location in CBFS that the FSP is located. This must match the
+
|- bgcolor="#eeeeee"
value that is set in the FSP binary.  If the FSP needs to be moved,
+
| KBC1126_FIRMWARE || ec/hp/kbc1126 || bool || Add firmware images for KBC1126 EC ||  
rebase the FSP with Intel's BCT (tool).
+
Select this option to add the two firmware blobs for KBC1126.
 +
You need these two blobs to power on your machine.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_FSP_FAST_BOOT || drivers/intel/fsp1_0 || bool || Enable Fast Boot ||  
+
| KBC1126_FW1 || ec/hp/kbc1126 || string || KBC1126 firmware #1 path and filename ||  
Enabling this feature will force the MRC data to be cached in NV
+
The path and filename of the file to use as KBC1126 firmware #1.
storage to be used for speeding up boot time on future reboots
+
You can use util/kbc1126/kbc1126_ec_dump to dump it from the
and/or power cycles.
+
vendor firmware.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_MRC_CACHE || drivers/intel/fsp1_0 || bool || ||  
+
| KBC1126_FW2 || ec/hp/kbc1126 || string || KBC1126 filename #2 path and filename ||  
Enabling this feature will cause MRC data to be cached in NV storage.
+
The path and filename of the file to use as KBC1126 firmware #2.
This can either be used for fast boot, or just because the FSP wants
+
You can use util/kbc1126/kbc1126_ec_dump to dump it from the
it to be saved.
+
vendor firmware.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MRC_CACHE_FMAP || drivers/intel/fsp1_0 || bool || Use MRC Cache in FMAP ||  
+
| H8_BEEP_ON_DEATH || ec/lenovo/h8 || bool || Beep on fatal error ||  
Use the region "RW_MRC_CACHE" in FMAP instead of "mrc.cache" in CBFS.
+
Beep when encountered a fatal error.
You must define a region in your FMAP named "RW_MRC_CACHE".
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MRC_CACHE_SIZE || drivers/intel/fsp1_0 || hex || Fast Boot Data Cache Size ||  
+
| H8_FLASH_LEDS_ON_DEATH || ec/lenovo/h8 || bool || Flash LEDs on fatal error ||  
This is the amount of space in NV storage that is reserved for the
+
Flash all LEDs when encountered a fatal error.
fast boot data cache storage.
 
 
 
WARNING: Because this area will be erased and re-written, the size
 
should be a full sector of the flash ROM chip and nothing else should
 
be included in CBFS in any sector that the fast boot cache data is in.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VIRTUAL_ROM_SIZE || drivers/intel/fsp1_0 || hex || Virtual ROM Size ||  
+
| H8_SUPPORT_BT_ON_WIFI || ec/lenovo/h8 || bool || Support bluetooth on wifi cards ||  
This is used to calculate the offset of the MRC data cache in NV
+
Disable BDC detection and assume bluetooth is installed. Required for
Storage for fast boot.  If in doubt, leave this set to the default
+
bluetooth on wifi cards, as it's not possible to detect it in coreboot.
which sets the virtual size equal to the ROM size.
 
 
 
Example: Cougar Canyon 2 has two 8 MB SPI ROMs.  When the SPI ROMs are
 
loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB.  When
 
the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM
 
size is 16 MB.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CACHE_ROM_SIZE_OVERRIDE || drivers/intel/fsp1_0 || hex || Cache ROM Size ||  
+
| EC_RODA_IT8518 || ec/roda/it8518 || bool || ||  
This is the size of the cachable area that is passed into the FSP in
+
Interface to IT8518 embedded controller in Roda notebooks.
the early initialization.  Typically this should be the size of the CBFS
 
area, but the size must be a power of 2 whereas the CBFS size does not
 
have this limitation.
 
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| USE_GENERIC_FSP_CAR_INC || drivers/intel/fsp1_0 || bool ||  ||  
+
| EC_SMSC_MEC1308 || ec/smsc/mec1308 || bool ||  ||  
The chipset can select this to use a generic cache_as_ram.inc file
+
Shared memory mailbox interface to SMSC MEC1308 Embedded Controller.
that should be good for all FSP based platforms.
 
  
 
||
 
||
|- bgcolor="#eeeeee"
 
| FSP_USES_UPD || drivers/intel/fsp1_0 || bool ||  ||
 
If this FSP uses UPD/VPD data regions, select this in the chipset Kconfig.
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HAVE_INTEL_FIRMWARE || southbridge/intel/common/firmware || bool ||  ||  
+
| EC_PURISM_LIBREM || ec/purism/librem || bool ||  ||  
Chipset uses the Intel Firmware Descriptor to describe the
+
Purism Librem EC
layout of the SPI ROM chip.
 
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || Intel Firmware ||
+
| EC_COMPAL_ENE932 || ec/compal/ene932 || bool || ||  
 +
Interface to COMPAL ENE932 Embedded Controller.
 +
 
 +
||
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HAVE_IFD_BIN || southbridge/intel/common/firmware || bool || Add Intel descriptor.bin file ||  
+
| EC_KONTRON_IT8516E || ec/kontron/it8516e || bool || ||  
The descriptor binary
+
Kontron uses an ITE IT8516E on the KTQM77. Its firmware might
 +
come from Fintek (mentioned as Finte*c* somewhere in their Linux
 +
driver).
 +
The KTQM77 is an embedded board and the IT8516E seems to be
 +
only used for fan control and GPIO.
  
 
||
 
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Intel FSP ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EM100 || southbridge/intel/common/firmware || bool || Configure IFD for EM100 usage ||  
+
| HAVE_FSP_BIN || drivers/intel/fsp1_0 || bool || Use Intel Firmware Support Package ||  
Set SPI frequency to 20MHz and disable Dual Output Fast Read Support
+
Select this option to add an Intel FSP binary to
 +
the resulting coreboot image.
 +
 
 +
Note: Without this binary, coreboot builds relying on the FSP
 +
will not boot
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HAVE_ME_BIN || southbridge/intel/common/firmware || bool || Add Intel ME/TXE firmware ||  
+
| FSP_FILE || drivers/intel/fsp1_0 || string || Intel FSP binary path and filename ||  
The Intel processor in the selected system requires a special firmware
+
The path and filename of the Intel FSP binary for this platform.
for an integrated controller.  This might be called the Management
 
Engine (ME), the Trusted Execution Engine (TXE) or something else
 
depending on the chip. This firmware might or might not be available
 
in coreboot's 3rdparty/blobs repository. If it is not and if you don't
 
have access to the firmware from elsewhere, you can still build
 
coreboot without it. In this case however, you'll have to make sure
 
that you don't overwrite your ME/TXE firmware on your flash ROM.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CHECK_ME || southbridge/intel/common/firmware || bool || Verify the integrity of the supplied ME/TXE firmware ||  
+
| FSP_LOC || drivers/intel/fsp1_0 || hex || Intel FSP Binary location in CBFS ||  
Verify the integrity of the supplied Intel ME/TXE firmware before
+
The location in CBFS that the FSP is located. This must match the
proceeding with the build, in order to prevent an accidental loading
+
value that is set in the FSP binary.  If the FSP needs to be moved,
of a corrupted ME/TXE image.
+
rebase the FSP with Intel's BCT (tool).
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| USE_ME_CLEANER || southbridge/intel/common/firmware || bool || Strip down the Intel ME/TXE firmware ||  
+
| ENABLE_FSP_FAST_BOOT || drivers/intel/fsp1_0 || bool || Enable Fast Boot ||  
Use me_cleaner to remove all the non-fundamental code from the Intel
+
Enabling this feature will force the MRC data to be cached in NV
ME/TXE firmware.
+
storage to be used for speeding up boot time on future reboots
The resulting Intel ME/TXE firmware will have only the code
+
and/or power cycles.
responsible for the very basic hardware initialization, leaving the
 
ME/TXE subsystem essentially in a disabled state.
 
  
Don't flash a modified ME/TXE firmware and a new coreboot image at the
+
||
same time, test them in two different steps.
+
|- bgcolor="#eeeeee"
 +
| ENABLE_MRC_CACHE || drivers/intel/fsp1_0 || bool ||  ||
 +
Enabling this feature will cause MRC data to be cached in NV storage.
 +
This can either be used for fast boot, or just because the FSP wants
 +
it to be saved.
  
WARNING: this tool isn't based on any official Intel documentation but
+
||
only on reverse engineering and trial & error.
+
|- bgcolor="#eeeeee"
 
+
| MRC_CACHE_FMAP || drivers/intel/fsp1_0 || bool || Use MRC Cache in FMAP ||
See the project's page
+
Use the region "RW_MRC_CACHE" in FMAP instead of "mrc.cache" in CBFS.
https://github.com/corna/me_cleaner
+
You must define a region in your FMAP named "RW_MRC_CACHE".
or the wiki
 
https://github.com/corna/me_cleaner/wiki/How-to-apply-me_cleaner
 
https://github.com/corna/me_cleaner/wiki/How-does-it-work%3F
 
https://github.com/corna/me_cleaner/wiki/me_cleaner-status
 
for more info about this tool
 
 
 
If unsure, say N.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || Please test the modified ME/TXE firmware and coreboot in two steps ||
+
| MRC_CACHE_SIZE || drivers/intel/fsp1_0 || hex || Fast Boot Data Cache Size ||  
|- bgcolor="#eeeeee"
+
This is the amount of space in NV storage that is reserved for the
| HAVE_GBE_BIN || southbridge/intel/common/firmware || bool || Add gigabit ethernet firmware ||  
+
fast boot data cache storage.
The integrated gigabit ethernet controller needs a firmware file.
+
 
Select this if you are going to use the PCH integrated controller
+
WARNING: Because this area will be erased and re-written, the size
and have the firmware.
+
should be a full sector of the flash ROM chip and nothing else should
 +
be included in CBFS in any sector that the fast boot cache data is in.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HAVE_EC_BIN || southbridge/intel/common/firmware || bool || Add EC firmware ||  
+
| VIRTUAL_ROM_SIZE || drivers/intel/fsp1_0 || hex || Virtual ROM Size ||  
The embedded controller needs a firmware file.
+
This is used to calculate the offset of the MRC data cache in NV
 +
Storage for fast boot.  If in doubt, leave this set to the default
 +
which sets the virtual size equal to the ROM size.
  
Select this if you are going to use the PCH integrated controller
+
Example: Cougar Canyon 2 has two 8 MB SPI ROMs.  When the SPI ROMs are
and have the EC firmware. EC firmware will be added to final image
+
loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB.  When
through ifdtool.
+
the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM
 +
size is 16 MB.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BUILD_WITH_FAKE_IFD || southbridge/intel/common/firmware || bool || Build with a fake IFD ||  
+
| CACHE_ROM_SIZE_OVERRIDE || drivers/intel/fsp1_0 || hex || Cache ROM Size ||  
If you don't have an Intel Firmware Descriptor (descriptor.bin) for your
+
This is the size of the cachable area that is passed into the FSP in
board, you can select this option and coreboot will build without it.
+
the early initialization. Typically this should be the size of the CBFS
The resulting coreboot.rom will not contain all parts required
+
area, but the size must be a power of 2 whereas the CBFS size does not
to get coreboot running on your board. You can however write only the
+
have this limitation.
BIOS section to your board's flash ROM and keep the other sections
 
untouched. Unfortunately the current version of flashrom doesn't
 
support this yet. But there is a patch pending [1].
 
  
WARNING: Never write a complete coreboot.rom to your flash ROM if it
+
||
was built with a fake IFD. It just won't work.
+
|- bgcolor="#eeeeee"
 
+
| USE_GENERIC_FSP_CAR_INC || drivers/intel/fsp1_0 || bool ||  ||
[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
+
The chipset can select this to use a generic cache_as_ram.inc file
 +
that should be good for all FSP based platforms.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| IFD_BIOS_SECTION || southbridge/intel/common/firmware || string || BIOS Region Starting:Ending addresses within the ROM ||  
+
| FSP_USES_UPD || drivers/intel/fsp1_0 || bool || ||  
The BIOS region is typically the size of the CBFS area, and is located
+
If this FSP uses UPD/VPD data regions, select this in the chipset Kconfig.
at the end of the ROM space.
 
 
 
For an 8MB ROM with a 3MB CBFS area, this would look like:
 
0x00500000:0x007fffff
 
 
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| IFD_ME_SECTION || southbridge/intel/common/firmware || string || ME/TXE Region Starting:Ending addresses within the ROM ||  
+
| HAVE_INTEL_FIRMWARE || southbridge/intel/common/firmware || bool || ||  
The ME/TXE region typically starts at around 0x1000 and often fills the
+
Chipset uses the Intel Firmware Descriptor to describe the
ROM space not used by CBFS.
+
layout of the SPI ROM chip.
 
 
For an 8MB ROM with a 3MB CBFS area, this might look like:
 
0x00001000:0x004fffff
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| IFD_GBE_SECTION || southbridge/intel/common/firmware || string || GBE Region Starting:Ending addresses within the ROM ||  
+
| || || (comment) || || Intel Firmware ||
The Gigabit Ethernet ROM region is used when an Intel NIC is built into
+
|- bgcolor="#eeeeee"
the Southbridge/SOC and the platform uses this device instead of an external
+
| HAVE_IFD_BIN || southbridge/intel/common/firmware || bool || Add Intel descriptor.bin file ||  
PCIe NIC.  It will be located between the ME/TXE and the BIOS region.
+
The descriptor binary
 
 
Leave this empty if you're unsure.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| IFD_PLATFORM_SECTION || southbridge/intel/common/firmware || string || Platform Region Starting:Ending addresses within the Rom ||  
+
| EM100 || southbridge/intel/common/firmware || bool || Configure IFD for EM100 usage ||  
The Platform region is used for platform specific data.
+
Set SPI frequency to 20MHz and disable Dual Output Fast Read Support
It will be located between the ME/TXE and the BIOS region.
 
 
 
Leave this empty if you're unsure.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| LOCK_MANAGEMENT_ENGINE || southbridge/intel/common/firmware || bool || Lock ME/TXE section ||  
+
| HAVE_ME_BIN || southbridge/intel/common/firmware || bool || Add Intel ME/TXE firmware ||  
The Intel Firmware Descriptor supports preventing write accesses
+
The Intel processor in the selected system requires a special firmware
from the host to the ME or TXE section in the firmware
+
for an integrated controller.  This might be called the Management
descriptor. If the section is locked, it can only be overwritten
+
Engine (ME), the Trusted Execution Engine (TXE) or something else
with an external SPI flash programmer. You will want this if you
+
depending on the chip. This firmware might or might not be available
want to increase security of your ROM image once you are sure
+
in coreboot's 3rdparty/blobs repository. If it is not and if you don't
that the ME/TXE firmware is no longer going to change.
+
have access to the firmware from elsewhere, you can still build
 
+
coreboot without it. In this case however, you'll have to make sure
If unsure, say N.
+
that you don't overwrite your ME/TXE firmware on your flash ROM.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CBFS_SIZE || southbridge/intel/common/firmware || hex || ||  
+
| CHECK_ME || southbridge/intel/common/firmware || bool || Verify the integrity of the supplied ME/TXE firmware ||  
Reduce CBFS size to give room to the IFD blobs.
+
Verify the integrity of the supplied Intel ME/TXE firmware before
 +
proceeding with the build, in order to prevent an accidental loading
 +
of a corrupted ME/TXE image.
  
 
||
 
||
|- bgcolor="#6699dd"
 
! align="left" | Menu: AMD Platform Initialization || || || ||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| None || vendorcode/amd || None || AGESA source ||  
+
| USE_ME_CLEANER || southbridge/intel/common/firmware || bool || Strip down the Intel ME/TXE firmware ||  
Select the method for including the AMD Platform Initialization
+
Use me_cleaner to remove all the non-fundamental code from the Intel
code into coreboot. Platform Initialization code is required for
+
ME/TXE firmware.
all AMD processors.
+
The resulting Intel ME/TXE firmware will have only the code
 +
responsible for the very basic hardware initialization, leaving the
 +
ME/TXE subsystem essentially in a disabled state.
  
||
+
Don't flash a modified ME/TXE firmware and a new coreboot image at the
|- bgcolor="#eeeeee"
+
same time, test them in two different steps.
| CPU_AMD_AGESA_BINARY_PI || vendorcode/amd || bool || binary PI ||
 
Use a binary PI package.  Generally, these will be stored in the
 
"3rdparty/blobs" directory.  For some processors, these must be obtained
 
directly from AMD Embedded Processors Group
 
(http://www.amdcom/embedded).
 
  
||
+
WARNING: this tool isn't based on any official Intel documentation but
|- bgcolor="#eeeeee"
+
only on reverse engineering and trial & error.
| CPU_AMD_AGESA_OPENSOURCE || vendorcode/amd || bool || open-source AGESA ||
 
Build the PI package ("AGESA") from source code in the "vendorcode"
 
directory.
 
  
||
+
See the project's page
|- bgcolor="#eeeeee"
+
https://github.com/corna/me_cleaner
| AGESA_BINARY_PI_VENDORCODE_PATH || vendorcode/amd/pi || string || AGESA PI directory path ||
+
or the wiki
Specify where to find the AGESA header files
+
https://github.com/corna/me_cleaner/wiki/How-to-apply-me_cleaner
for AMD platform initialization.
+
https://github.com/corna/me_cleaner/wiki/How-does-it-work%3F
 +
https://github.com/corna/me_cleaner/wiki/me_cleaner-status
 +
for more info about this tool
  
||
+
If unsure, say N.
|- bgcolor="#eeeeee"
 
| AGESA_BINARY_PI_FILE || vendorcode/amd/pi || string || AGESA PI binary file name ||
 
Specify the binary file to use for AMD platform initialization.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| AGESA_BINARY_PI_LOCATION || vendorcode/amd/pi || hex || AGESA PI binary address in ROM ||  
+
| || || (comment) || || Please test the modified ME/TXE firmware and coreboot in two steps ||
Specify the ROM address at which to store the binary Platform
 
Initialization code.
 
 
 
||
 
 
 
|- bgcolor="#6699dd"
 
! align="left" | Menu: ChromeOS || || || ||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CHROMEOS || vendorcode/google/chromeos || bool || Build for ChromeOS ||  
+
| HAVE_GBE_BIN || southbridge/intel/common/firmware || bool || Add gigabit ethernet firmware ||  
Enable ChromeOS specific features like the GPIO sub table in
+
The integrated gigabit ethernet controller needs a firmware file.
the coreboot table. NOTE: Enabling this option on an unsupported
+
Select this if you are going to use the PCH integrated controller
board will most likely break your build.
+
and have the firmware.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NO_TPM_RESUME || vendorcode/google/chromeos || bool || ||  
+
| HAVE_EC_BIN || southbridge/intel/common/firmware || bool || Add EC firmware ||  
On some boards the TPM stays powered up in S3. On those
+
The embedded controller needs a firmware file.
boards, booting Windows will break if the TPM resume command
 
is sent during an S3 resume.
 
  
||
+
Select this if you are going to use the PCH integrated controller
|- bgcolor="#eeeeee"
+
and have the EC firmware. EC firmware will be added to final image
| HAVE_REGULATORY_DOMAIN || vendorcode/google/chromeos || bool || Add regulatory domain methods ||
+
through ifdtool.
This option is needed to add ACPI regulatory domain methods