Difference between revisions of "Coreboot Options"

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(update options to 5205)
 
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Until a while ago, coreboot was using a custom, "home-made" config system. For some time you can look at the [[Coreboot Options(old)|old list of options]].
{{#externalredirect: https://coreboot.org/status/kconfig-options.html }}
 
The new config system is kconfig (a.k.a. "[[Build HOWTO|make menuconfig]]"), the well-known system as also used by the Linux kernel, busybox and a various other projects.
 
This is an automatically generated list of '''coreboot compile-time options'''.
 
Last update: 2010/03/13 22:12:25. (r5205)
{| border="0" style="font-size: smaller"
|- bgcolor="#6699dd"
! align="left" | Option
! align="left" | Source
! align="left" | Format
! align="left" | Short Description
! align="left" | Description
|- bgcolor="#6699dd"
! align="left" | Menu: General setup || || || ||
|- bgcolor="#eeeeee"
| EXPERT || toplevel || bool || Expert mode ||
This allows you to select certain advanced configuration options.
 
Warning: Only enable this option if you really know what you are
doing! You have been warned!
 
||
|- bgcolor="#eeeeee"
| LOCALVERSION || toplevel || string || Local version string ||
Append an extra string to the end of the coreboot version.
 
This can be useful if, for instance, you want to append the
respective board's hostname or some other identifying string to
the coreboot version number, so that you can easily distinguish
boot logs of different boards from each other.
 
||
|- bgcolor="#eeeeee"
| CBFS_PREFIX || toplevel || string || CBFS prefix to use ||
Select the prefix to all files put into the image. It's "fallback"
by default, "normal" is a common alternative.
 
||
 
|- bgcolor="#6699dd"
! align="left" | Menu: Mainboard || || || ||
|- bgcolor="#eeeeee"
| BOARD_ROMSIZE_KB_4096 || mainboard || bool || ROM chip size ||
Select the size of the ROM chip you intend to flash coreboot on.
 
The build system will take care of creating a coreboot.rom file
of the matching size.
 
||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_128 || mainboard || bool || 128 KB ||
Choose this option if you have a 128 KB ROM chip.
 
||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_256 || mainboard || bool || 256 KB ||
Choose this option if you have a 256 KB ROM chip.
 
||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_512 || mainboard || bool || 512 KB ||
Choose this option if you have a 512 KB ROM chip.
 
||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_1024 || mainboard || bool || 1024 KB (1 MB) ||
Choose this option if you have a 1024 KB (1 MB) ROM chip.
 
||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_2048 || mainboard || bool || 2048 KB (2 MB) ||
Choose this option if you have a 2048 KB (2 MB) ROM chip.
 
||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_4096 || mainboard || bool || 4096 KB (4 MB) ||
Choose this option if you have a 4096 KB (4 MB) ROM chip.
 
||
 
|- bgcolor="#eeeeee"
| UPDATE_IMAGE || arch/i386 || bool || Update existing coreboot.rom image ||
If this option is activate, no new coreboot.rom file
is created. Instead it is expected that there already
is a suitable file for further processing.
The bootblock will not be modified.
 
||
|- bgcolor="#6699dd"
! align="left" | Menu: Chipset || || || ||
|- bgcolor="#eeeeee"
| || || (comment) || || CPU ||
|- bgcolor="#eeeeee"
| SMP || cpu || bool ||  ||
This option is used to enable certain functions to make coreboot
work correctly on symmetric multi processor (SMP) systems.
 
||
|- bgcolor="#eeeeee"
| MMX || cpu || bool ||  ||
Select MMX in your socket or model Kconfig if your CPU has MMX
streaming SIMD instructions. ROMCC can build more efficient
code if it can spill to MMX registers.
 
||
|- bgcolor="#eeeeee"
| SSE || cpu || bool ||  ||
Select SSE in your socket or model Kconfig if your CPU has SSE
streaming SIMD instructions. ROMCC can build more efficient
code if it can spill to SSE (aka XMM) registers.
 
||
|- bgcolor="#eeeeee"
| SSE2 || cpu || bool ||  ||
Select SSE2 in your socket or model Kconfig if your CPU has SSE2
streaming SIMD instructions. Some parts of coreboot can be built
with more efficient code if SSE2 instructions are available.
 
||
|- bgcolor="#eeeeee"
| VAR_MTRR_HOLE || cpu || bool ||  ||
Unset this if you don't want the MTRR code to use
subtractive MTRRs
 
||
||
|- bgcolor="#eeeeee"
| || || (comment) || || Northbridge ||
|- bgcolor="#6699dd"
! align="left" | Menu: HyperTransport setup || || || ||
|- bgcolor="#eeeeee"
| CBFS_PREFIX || toplevel || string || HyperTransport frequency ||
This option sets the maximum permissible HyperTransport link
frequency.
 
Use of this option will only limit the autodetected HT frequency.
It will not (and cannot) increase the frequency beyond the
autodetected limits.
 
This is primarily used to work around poorly designed or laid out
HT traces on certain motherboards.
 
||
|- bgcolor="#eeeeee"
| LIMIT_HT_SPEED_AUTO || toplevel || bool || HyperTransport downlink width ||
This option sets the maximum permissible HyperTransport
downlink width.
 
Use of this option will only limit the autodetected HT width.
It will not (and cannot) increase the width beyond the autodetected
limits.
 
This is primarily used to work around poorly designed or laid out HT
traces on certain motherboards.
 
||
|- bgcolor="#eeeeee"
| LIMIT_HT_DOWN_WIDTH_16 || toplevel || bool || HyperTransport uplink width ||
This option sets the maximum permissible HyperTransport
uplink width.
 
Use of this option will only limit the autodetected HT width.
It will not (and cannot) increase the width beyond the autodetected
limits.
 
This is primarily used to work around poorly designed or laid out HT
traces on certain motherboards.
 
||
 
|- bgcolor="#eeeeee"
| SDRAMPWR_4DIMM || northbridge/intel/i440bx || bool ||  ||
This option affects how the SDRAMC register is programmed.
Memory clock signals will not be routed properly if this option
is set wrong.
 
If your board has 4 DIMM slots, you must use select this option, in
your Kconfig file of the board. On boards with 3 DIMM slots,
do _not_ select this option.
 
 
||
||
|- bgcolor="#eeeeee"
| || || (comment) || || Southbridge ||
|- bgcolor="#6699dd"
! align="left" | Menu: AMD Geode GX1 video support || || || ||
 
|- bgcolor="#eeeeee"
| || || (comment) || || Super I/O ||
|- bgcolor="#eeeeee"
| || || (comment) || || Devices ||
|- bgcolor="#eeeeee"
| VGA_BRIDGE_SETUP || devices || bool || Setup bridges on path to VGA adapter ||
Allow bridges to set up legacy decoding ranges for VGA. Don't disable
this unless you're sure you don't want the briges setup for VGA.
 
||
|- bgcolor="#eeeeee"
| VGA_ROM_RUN || devices || bool || Run VGA option ROMs ||
Execute VGA option ROMs, if found. This is required to enable
PCI/AGP/PCI-E video cards.
 
||
|- bgcolor="#eeeeee"
| PCI_ROM_RUN || devices || bool || Run non-VGA option ROMs ||
Execute non-VGA PCI option ROMs, if found.
 
Examples include IDE/SATA controller option ROMs and option ROMs
for network cards (NICs).
 
||
|- bgcolor="#eeeeee"
| PCI_OPTION_ROM_RUN_REALMODE || devices || bool || Native mode ||
If you select this option, PCI option ROMs will be executed
natively on the CPU in real mode. No CPU emulation is involved,
so this is the fastest, but also the least secure option.
(only works on x86/x64 systems)
 
||
|- bgcolor="#eeeeee"
| PCI_OPTION_ROM_RUN_YABEL || devices || bool || Secure mode ||
If you select this option, the x86emu CPU emulator will be used to
execute PCI option ROMs.
 
This option prevents option ROMs from doing dirty tricks with the
system (such as installing SMM modules or hypervisors), but it is
also significantly slower than the native option ROM initialization
method.
 
This is the default choice for non-x86 systems.
 
||
|- bgcolor="#eeeeee"
| YABEL_PCI_ACCESS_OTHER_DEVICES || devices || bool || Allow option ROMs to access other devices ||
Per default, YABEL only allows option ROMs to access the PCI device
that they are associated with. However, this causes trouble for some
onboard graphics chips whose option ROM needs to reconfigure the
north bridge.
 
||
|- bgcolor="#eeeeee"
| YABEL_VIRTMEM_LOCATION || devices || hex || Location of YABEL's virtual memory ||
YABEL requires 1MB memory for its CPU emulation. This memory is
normally located at 16MB.
 
||
|- bgcolor="#eeeeee"
| YABEL_DIRECTHW || devices || bool || Direct hardware access ||
YABEL consists of two parts: It uses x86emu for the CPU emulation and
additionally provides a PC system emulation that filters bad device
and memory access (such as PCI config space access to other devices
than the initialized one).
 
When choosing this option, x86emu will pass through all hardware
accesses to memory and I/O devices to the underlying memory and I/O
addresses. While this option prevents option ROMs from doing dirty
tricks with the CPU (such as installing SMM modules or hypervisors),
they can still access all devices in the system.
Enable this option for a good compromise between security and speed.
 
||
 
|- bgcolor="#6699dd"
! align="left" | Menu: Console options || || || ||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL8250 || console || bool || Serial port console output ||
Send coreboot debug output to a serial port console.
 
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM1 || console || bool || COM1/ttyS0, I/O port 0x3f8 ||
Serial console on COM1/ttyS0 at I/O port 0x3f8.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM2 || console || bool || COM2/ttyS1, I/O port 0x2f8 ||
Serial console on COM2/ttyS1 at I/O port 0x2f8.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM3 || console || bool || COM3/ttyS2, I/O port 0x3e8 ||
Serial console on COM3/ttyS2 at I/O port 0x3e8.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM4 || console || bool || COM4/ttyS3, I/O port 0x2e8 ||
Serial console on COM4/ttyS3 at I/O port 0x2e8.
 
||
|- bgcolor="#eeeeee"
| TTYS0_BASE || console || hex ||  ||
Map the COM port names to the respective I/O port.
 
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_115200 || console || bool || 115200 ||
Set serial port Baud rate to 115200.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_57600 || console || bool || 57600 ||
Set serial port Baud rate to 57600.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_38400 || console || bool || 38400 ||
Set serial port Baud rate to 38400.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_19200 || console || bool || 19200 ||
Set serial port Baud rate to 19200.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_9600 || console || bool || 9600 ||
Set serial port Baud rate to 9600.
 
||
|- bgcolor="#eeeeee"
| TTYS0_BAUD || console || int ||  ||
Map the Baud rates to an integer.
 
||
|- bgcolor="#eeeeee"
| SERIAL_POST || console || bool || Show POST codes on the serial port console ||
If enabled, coreboot will additionally print POST codes (which are
usually displayed using a so-called "POST card" ISA/PCI/PCI-E
device) on the serial console.
 
||
|- bgcolor="#eeeeee"
| USBDEBUG_DIRECT || console || bool || USB 2.0 EHCI debug dongle support ||
This option allows you to use a so-called USB EHCI Debug device
to retrieve the coreboot debug messages (instead, or in addition
to, a serial port).
 
This feature is NOT supported on all chipsets in coreboot!
 
It also requires a USB2 controller which supports the EHCI
Debug Port capability. Controllers which are known to work:
 
* 10b9:5239 ALi Corporation USB 2.0 (USB PCI card)
* 8086:24cd Intel ICH4/ICH4-M
* 8086:24dd Intel ICH5
* 8086:265c Intel ICH6
* 8086:268c Intel 631xESB/632xESB/3100
* 8086:27cc Intel ICH7
* 8086:2836 Intel ICH8
* 8086:283a Intel ICH8
* 8086:293a Intel ICH9
* 10de:0088 NVIDIA MCP2A
* 10de:005b NVIDIA CK804
* 10de:026e NVIDIA MCP51
* 10de:036d NVIDIA MCP55
* 10de:03f2 NVIDIA MCP61
* 1002:4386 ATI/AMD SB600
* 1106:3104 VIA VX800
 
See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list.
 
||
|- bgcolor="#eeeeee"
| CONSOLE_VGA_ONBOARD_AT_FIRST || console || bool || Use onboard VGA as primary video device ||
If not selected, the last adapter found will be used.
 
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_8 || console || bool || 8: SPEW ||
Way too many details.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_7 || console || bool || 7: DEBUG ||
Debug-level messages.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_6 || console || bool || 6: INFO ||
Informational messages.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_5 || console || bool || 5: NOTICE ||
Normal but significant conditions.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_4 || console || bool || 4: WARNING ||
Warning conditions.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_3 || console || bool || 3: ERR ||
Error conditions.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_2 || console || bool || 2: CRIT ||
Critical conditions.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_1 || console || bool || 1: ALERT ||
Action must be taken immediately.
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_0 || console || bool || 0: EMERG ||
System is unusable.
 
||
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL || console || int ||  ||
Map the log level config names to an integer.
 
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_8 || console || bool || 8: SPEW ||
Way too many details.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_7 || console || bool || 7: DEBUG ||
Debug-level messages.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_6 || console || bool || 6: INFO ||
Informational messages.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_5 || console || bool || 5: NOTICE ||
Normal but significant conditions.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_4 || console || bool || 4: WARNING ||
Warning conditions.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_3 || console || bool || 3: ERR ||
Error conditions.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_2 || console || bool || 2: CRIT ||
Critical conditions.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_1 || console || bool || 1: ALERT ||
Action must be taken immediately.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_0 || console || bool || 0: EMERG ||
System is unusable.
 
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL || console || int ||  ||
Map the log level config names to an integer.
 
||
 
|- bgcolor="#eeeeee"
| HAVE_HARD_RESET || toplevel || bool ||  ||
This variable specifies whether a given board has a hard_reset
function, no matter if it's provided by board code or chipset code.
 
||
|- bgcolor="#eeeeee"
| BOARD_HAS_HARD_RESET || toplevel || bool ||  ||
This variable specifies whether a given board has a reset.c
file containing a hard_reset() function.
 
||
|- bgcolor="#eeeeee"
| BOARD_HAS_FADT || toplevel || bool ||  ||
This variable specifies whether a given board has a board-local
FADT in fadt.c. Long-term, those should be moved to appropriate
chipset components (eg. southbridge)
 
||
|- bgcolor="#eeeeee"
| HAVE_BUS_CONFIG || toplevel || bool ||  ||
This variable specifies whether a given board has a get_bus_conf.c
file containing bus configuration data.
 
||
|- bgcolor="#eeeeee"
| HAVE_OPTION_TABLE || toplevel || bool ||  ||
This variable specifies whether a given board has a cmos.layout
file containing NVRAM/CMOS bit definitions.
It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig.
 
||
|- bgcolor="#eeeeee"
| VGA || toplevel || bool ||  ||
Build board-specific VGA code.
 
||
|- bgcolor="#eeeeee"
| GFXUMA || toplevel || bool ||  ||
Enable Unified Memory Architecture for graphics.
 
||
|- bgcolor="#eeeeee"
| HAVE_LOW_TABLES || toplevel || bool ||  ||
This Option is unused in the code.  Since two boards try to set it to
'n', they may be broken.  We either need to make the option useful or
get rid of it.  The broken boards are:
asus/m2v-mx_se
supermicro/h8dme
 
||
|- bgcolor="#eeeeee"
| HAVE_HIGH_TABLES || toplevel || bool ||  ||
This variable specifies whether a given northbridge has high table
support.
It is set in northbridge/*/Kconfig.
Whether or not the high tables are actually written by coreboot is
configurable by the user via WRITE_HIGH_TABLES.
 
||
|- bgcolor="#eeeeee"
| HAVE_ACPI_TABLES || toplevel || bool ||  ||
This variable specifies whether a given board has ACPI table support.
It is usually set in mainboard/*/Kconfig.
Whether or not the ACPI tables are actually generated by coreboot
is configurable by the user via GENERATE_ACPI_TABLES.
 
||
|- bgcolor="#eeeeee"
| HAVE_MP_TABLE || toplevel || bool ||  ||
This variable specifies whether a given board has MP table support.
It is usually set in mainboard/*/Kconfig.
Whether or not the MP table is actually generated by coreboot
is configurable by the user via GENERATE_MP_TABLE.
 
||
|- bgcolor="#eeeeee"
| HAVE_PIRQ_TABLE || toplevel || bool ||  ||
This variable specifies whether a given board has PIRQ table support.
It is usually set in mainboard/*/Kconfig.
Whether or not the PIRQ table is actually generated by coreboot
is configurable by the user via GENERATE_PIRQ_TABLE.
 
||
|- bgcolor="#6699dd"
! align="left" | Menu: System tables || || || ||
|- bgcolor="#eeeeee"
| GENERATE_ACPI_TABLES || toplevel || bool || Generate ACPI tables ||
Generate ACPI tables for this board.
 
If unsure, say Y.
 
||
|- bgcolor="#eeeeee"
| GENERATE_MP_TABLE || toplevel || bool || Generate an MP table ||
Generate an MP table (conforming to the Intel MultiProcessor
specification 1.4) for this board.
 
If unsure, say Y.
 
||
|- bgcolor="#eeeeee"
| GENERATE_PIRQ_TABLE || toplevel || bool || Generate a PIRQ table ||
Generate a PIRQ table for this board.
 
If unsure, say Y.
 
||
 
|- bgcolor="#6699dd"
! align="left" | Menu: Payload || || || ||
|- bgcolor="#eeeeee"
| PAYLOAD_NONE || toplevel || bool || None ||
Select this option if you want to create an "empty" coreboot
ROM image for a certain mainboard, i.e. a coreboot ROM image
which does not yet contain a payload.
 
For such an image to be useful, you have to use 'cbfstool'
to add a payload to the ROM image later.
 
||
|- bgcolor="#eeeeee"
| PAYLOAD_ELF || toplevel || bool || An ELF executable payload ||
Select this option if you have a payload image (an ELF file)
which coreboot should run as soon as the basic hardware
initialization is completed.
 
You will be able to specify the location and file name of the
payload image later.
 
||
|- bgcolor="#eeeeee"
| FALLBACK_PAYLOAD_FILE || toplevel || string || Payload path and filename ||
The path and filename of the ELF executable file to use as payload.
 
||
|- bgcolor="#eeeeee"
| COMPRESSED_PAYLOAD_LZMA || toplevel || bool || Use LZMA compression for payloads ||
In order to reduce the size payloads take up in the ROM chip
coreboot can compress them using the LZMA algorithm.
 
||
 
|- bgcolor="#6699dd"
! align="left" | Menu: VGA BIOS || || || ||
|- bgcolor="#eeeeee"
| VGA_BIOS || toplevel || bool || Add a VGA BIOS image ||
Select this option if you have a VGA BIOS image that you would
like to add to your ROM.
 
You will be able to specify the location and file name of the
image later.
 
||
|- bgcolor="#eeeeee"
| FALLBACK_VGA_BIOS_FILE || toplevel || string || VGA BIOS path and filename ||
The path and filename of the file to use as VGA BIOS.
 
||
|- bgcolor="#eeeeee"
| FALLBACK_VGA_BIOS_ID || toplevel || string || VGA device PCI IDs ||
The comma-separated PCI vendor and device ID that would associate
your VGA BIOS to your video card.
 
Example: 1106,3230
 
In the above example 1106 is the PCI vendor ID (in hex, but without
the "0x" prefix) and 3230 specifies the PCI device ID of the
video card (also in hex, without "0x" prefix).
 
||
|- bgcolor="#eeeeee"
| INTEL_MBI || toplevel || bool || Add an MBI image ||
Select this option if you have an Intel MBI image that you would
like to add to your ROM.
 
You will be able to specify the location and file name of the
image later.
 
||
|- bgcolor="#eeeeee"
| FALLBACK_MBI_FILE || toplevel || string || Intel MBI path and filename ||
The path and filename of the file to use as VGA BIOS.
 
||
 
|- bgcolor="#6699dd"
! align="left" | Menu: Bootsplash || || || ||
|- bgcolor="#eeeeee"
| BOOTSPLASH || toplevel || bool || Show graphical bootsplash ||
This option shows a graphical bootsplash screen. The grapics are
loaded from the CBFS file bootsplash.jpg.
 
||
|- bgcolor="#eeeeee"
| FALLBACK_BOOTSPLASH_FILE || toplevel || string || Bootsplash path and filename ||
The path and filename of the file to use as graphical bootsplash
screen. The file format has to be jpg.
 
||
|- bgcolor="#eeeeee"
| FRAMEBUFFER_VESA_MODE || toplevel || hex || VESA framebuffer video mode ||
This option sets the resolution used for the coreboot framebuffer and
bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
some day make this a "choice".
 
||
|- bgcolor="#eeeeee"
| COREBOOT_KEEP_FRAMEBUFFER || toplevel || bool || Keep VESA framebuffer ||
This option keeps the framebuffer mode set after coreboot finishes
execution. If this option is enabled, coreboot will pass a
framebuffer entry in its coreboot table and the payload will need a
framebuffer driver. If this option is disabled, coreboot will switch
back to text mode before handing control to a payload.
 
||
 
|- bgcolor="#6699dd"
! align="left" | Menu: Debugging || || || ||
|- bgcolor="#eeeeee"
| GDB_STUB || toplevel || bool || GDB debugging support ||
If enabled, you will be able to set breakpoints for gdb debugging.
See src/arch/i386/lib/c_start.S for details.
 
||
|- bgcolor="#eeeeee"
| DEBUG_RAM_SETUP || toplevel || bool || Output verbose RAM init debug messages ||
This option enables additional RAM init related debug messages.
It is recommended to enable this when debugging issues on your
board which might be RAM init related.
 
Note: This option will increase the size of the coreboot image.
 
If unsure, say N.
 
||
|- bgcolor="#eeeeee"
| DEBUG_SMBUS || toplevel || bool || Output verbose SMBus debug messages ||
This option enables additional SMBus (and SPD) debug messages.
 
Note: This option will increase the size of the coreboot image.
 
If unsure, say N.
 
||
|- bgcolor="#eeeeee"
| DEBUG_SMI || toplevel || bool || Output verbose SMI debug messages ||
This option enables additional SMI related debug messages.
 
Note: This option will increase the size of the coreboot image.
 
If unsure, say N.
 
||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG || toplevel || bool || Output verbose x86emu debug messages ||
This option enables additional x86emu related debug messages.
 
Note: This option will increase the size of the coreboot image.
 
If unsure, say N.
 
||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_JMP || toplevel || bool || Trace JMP/RETF ||
Print information about JMP and RETF opcodes from x86emu.
 
Note: This option will increase the size of the coreboot image.
 
If unsure, say N.
 
||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_TRACE || toplevel || bool || Trace all opcodes ||
Print _all_ opcodes that are executed by x86emu.
 
WARNING: This will produce a LOT of output and take a long time.
 
Note: This option will increase the size of the coreboot image.
 
If unsure, say N.
 
||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_PNP || toplevel || bool || Log Plug&Play accesses ||
Print Plug And Play accesses made by option ROMs.
 
Note: This option will increase the size of the coreboot image.
 
If unsure, say N.
 
||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_DISK || toplevel || bool || Log Disk I/O ||
Print Disk I/O related messages.
 
Note: This option will increase the size of the coreboot image.
 
If unsure, say N.
 
||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_PMM || toplevel || bool || Log PMM ||
Print messages related to POST Memory Manager (PMM).
 
Note: This option will increase the size of the coreboot image.
 
If unsure, say N.
 
 
||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_VBE || toplevel || bool || Debug VESA BIOS Extensions ||
Print messages related to VESA BIOS Extension (VBE) functions.
 
Note: This option will increase the size of the coreboot image.
 
If unsure, say N.
 
||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_INT10 || toplevel || bool || Redirect INT10 output to console ||
Let INT10 (i.e. character output) calls print messages to debug output.
 
Note: This option will increase the size of the coreboot image.
 
If unsure, say N.
 
||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_INTERRUPTS || toplevel || bool || Log intXX calls ||
Print messages related to interrupt handling.
 
Note: This option will increase the size of the coreboot image.
 
If unsure, say N.
 
||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_CHECK_VMEM_ACCESS || toplevel || bool || Log special memory accesses ||
Print messages related to accesses to certain areas of the virtual
memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
 
Note: This option will increase the size of the coreboot image.
 
If unsure, say N.
 
||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_MEM || toplevel || bool || Log all memory accesses ||
Print memory accesses made by option ROM.
Note: This also includes accesses to fetch instructions.
 
Note: This option will increase the size of the coreboot image.
 
If unsure, say N.
 
||
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_IO || toplevel || bool || Log IO accesses ||
Print I/O accesses made by option ROM.
 
Note: This option will increase the size of the coreboot image.
 
If unsure, say N.
 
||
 
|}

Latest revision as of 20:02, 9 June 2018

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