Difference between revisions of "Coreboot Options"

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This is an automatically generated list of '''coreboot compile-time options'''.
 
This is an automatically generated list of '''coreboot compile-time options'''.
  
Last update: 2011/10/14 00:44:39. (runknown)
+
Last update: 4.3-1760-g168eb6a
 
{| border="0" style="font-size: smaller"
 
{| border="0" style="font-size: smaller"
 
|- bgcolor="#6699dd"
 
|- bgcolor="#6699dd"
Line 11: Line 11:
 
|- bgcolor="#6699dd"
 
|- bgcolor="#6699dd"
 
! align="left" | Menu: General setup || || || ||
 
! align="left" | Menu: General setup || || || ||
|- bgcolor="#eeeeee"
 
| EXPERT || toplevel || bool || Expert mode ||
 
This allows you to select certain advanced configuration options.
 
 
Warning: Only enable this option if you really know what you are
 
doing! You have been warned!
 
 
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| LOCALVERSION || toplevel || string || Local version string ||  
 
| LOCALVERSION || toplevel || string || Local version string ||  
Line 36: Line 28:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CBFS_PREFIX || toplevel || string || Compiler ||  
+
| COMMON_CBFS_SPI_WRAPPER || toplevel || bool ||  ||
 +
Use common wrapper to interface CBFS to SPI bootrom.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MULTIPLE_CBFS_INSTANCES || toplevel || bool || Multiple CBFS instances in the bootrom ||
 +
Account for the firmware image containing more than one CBFS
 +
instance. Locations of instances are known at build time and are
 +
communicated between coreboot stages to make sure the next stage is
 +
loaded from the appropriate instance.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MULTIPLE_CBFS_INSTANCES || toplevel || bool || Compiler to use ||  
 
This option allows you to select the compiler used for building
 
This option allows you to select the compiler used for building
 
coreboot.
 
coreboot.
 +
You must build the coreboot crosscompiler for the board that you
 +
have selected.
 +
 +
To build all the GCC crosscompilers (takes a LONG time), run:
 +
make crossgcc
 +
 +
For help on individual architectures, run the command:
 +
make help_toolchain
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SCANBUILD_ENABLE || toplevel || bool || Build with scan-build for static analysis ||  
+
| COMPILER_GCC || toplevel || bool || GCC ||  
Changes the build process to scan-build is used.
+
Use the GNU Compiler Collection (GCC) to build coreboot.
Requires scan-build in path.
+
 
 +
For details see http://gcc.gnu.org.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SCANBUILD_REPORT_LOCATION || toplevel || string || Directory to put scan-build report in ||  
+
| COMPILER_LLVM_CLANG || toplevel || bool || LLVM/clang (TESTING ONLY - Not currently working) ||  
Where the scan-build report should be stored
+
Use LLVM/clang to build coreboot.  To use this, you must build the
 +
coreboot version of the clang compiler.  Run the command
 +
make clang
 +
Note that this option is not currently working correctly and should
 +
really only be selected if you're trying to work on getting clang
 +
operational.
 +
 
 +
For details see http://clang.llvm.org.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CCACHE || toplevel || bool || ccache ||  
+
| ANY_TOOLCHAIN || toplevel || bool || Allow building with any toolchain ||
 +
Many toolchains break when building coreboot since it uses quite
 +
unusual linker features. Unless developers explicitely request it,
 +
we'll have to assume that they use their distro compiler by mistake.
 +
Make sure that using patched compilers is a conscious decision.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CCACHE || toplevel || bool || Use ccache to speed up (re)compilation ||  
 
Enables the use of ccache for faster builds.
 
Enables the use of ccache for faster builds.
Requires ccache in path.
+
 
 +
Requires the ccache utility in your system $PATH.
 +
 
 +
For details see https://ccache.samba.org.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FMD_GENPARSER || toplevel || bool || Generate flashmap descriptor parser using flex and bison ||
 +
Enable this option if you are working on the flashmap descriptor
 +
parser and made changes to fmd_scanner.l or fmd_parser.y.
 +
 
 +
Otherwise, say N to use the provided pregenerated scanner/parser.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| SCONFIG_GENPARSER || toplevel || bool || Generate SCONFIG parser using flex and bison ||  
 
| SCONFIG_GENPARSER || toplevel || bool || Generate SCONFIG parser using flex and bison ||  
Enable this option if you are working on the sconfig
+
Enable this option if you are working on the sconfig device tree
device tree parser and made changes to sconfig.l and
+
parser and made changes to sconfig.l or sconfig.y.
sconfig.y.
+
 
Otherwise, say N.
+
Otherwise, say N to use the provided pregenerated scanner/parser.
  
 
||
 
||
Line 69: Line 109:
 
| USE_OPTION_TABLE || toplevel || bool || Use CMOS for configuration values ||  
 
| USE_OPTION_TABLE || toplevel || bool || Use CMOS for configuration values ||  
 
Enable this option if coreboot shall read options from the "CMOS"
 
Enable this option if coreboot shall read options from the "CMOS"
NVRAM instead of using hard coded values.
+
NVRAM instead of using hard-coded values.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| STATIC_OPTION_TABLE || toplevel || bool || Load default configuration values into CMOS on each boot ||
 +
Enable this option to reset "CMOS" NVRAM values to default on
 +
every boot.  Use this if you want the NVRAM configuration to
 +
never be modified from its default values.
  
 
||
 
||
Line 76: Line 123:
 
Compress ramstage to save memory in the flash image. Note
 
Compress ramstage to save memory in the flash image. Note
 
that decompression might slow down booting if the boot flash
 
that decompression might slow down booting if the boot flash
is connected through a slow Link (i.e. SPI)
+
is connected through a slow link (i.e. SPI).
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| INCLUDE_CONFIG_FILE || toplevel || bool || Include the coreboot config file into the ROM image ||  
+
| COMPRESS_PRERAM_STAGES || toplevel || bool || Compress romstage and verstage with LZ4 ||
Include in CBFS the coreboot config file that was used to compile the ROM image
+
Compress romstage and (if it exists) verstage with LZ4 to save flash
 +
space and speed up boot, since the time for reading the image from SPI
 +
(and in the vboot case verifying it) is usually much greater than the
 +
time spent decompressing. Doesn't work for XIP stages (assume all
 +
ARCH_X86 for now) for obvious reasons.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| INCLUDE_CONFIG_FILE || toplevel || bool || Include the coreboot .config file into the ROM image ||  
 +
Include the .config file that was used to compile coreboot
 +
in the (CBFS) ROM image. This is useful if you want to know which
 +
options were used to build a specific coreboot.rom image.
 +
 
 +
Saying Y here will increase the image size by 2-3KB.
 +
 
 +
You can use the following command to easily list the options:
 +
 
 +
grep -a CONFIG_ coreboot.rom
 +
 
 +
Alternatively, you can also use cbfstool to print the image
 +
contents (including the raw 'config' item we're looking for).
 +
 
 +
Example:
 +
 
 +
$ cbfstool coreboot.rom print
 +
coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
 +
offset 0x0
 +
Alignment: 64 bytes
 +
 
 +
Name                          Offset    Type        Size
 +
cmos_layout.bin                0x0        cmos layout  1159
 +
fallback/romstage              0x4c0      stage        339756
 +
fallback/ramstage              0x53440    stage        186664
 +
fallback/payload              0x80dc0    payload      51526
 +
config                        0x8d740    raw          3324
 +
(empty)                        0x8e480    null        3610440
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NO_XIP_EARLY_STAGES || toplevel || bool ||  ||
 +
Identify if early stages are eXecute-In-Place(XIP).
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| COLLECT_TIMESTAMPS || toplevel || bool || Create a table of timestamps collected during boot ||
 +
Make coreboot create a table of timer-ID/timer-value pairs to
 +
allow measuring time spent at different phases of the boot process.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USE_BLOBS || toplevel || bool || Allow use of binary-only repository ||
 +
This draws in the blobs repository, which contains binary files that
 +
might be required for some chipsets or boards.
 +
This flag ensures that a "Free" option remains available for users.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| COVERAGE || toplevel || bool || Code coverage support ||
 +
Add code coverage support for coreboot. This will store code
 +
coverage information in CBMEM for extraction from user space.
 +
If unsure, say N.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RELOCATABLE_MODULES || toplevel || bool ||  ||
 +
If RELOCATABLE_MODULES is selected then support is enabled for
 +
building relocatable modules in the RAM stage. Those modules can be
 +
loaded anywhere and all the relocations are handled automatically.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RELOCATABLE_RAMSTAGE || toplevel || bool || Build the ramstage to be relocatable in 32-bit address space. ||
 +
The reloctable ramstage support allows for the ramstage to be built
 +
as a relocatable module. The stage loader can identify a place
 +
out of the OS way so that copying memory is unnecessary during an S3
 +
wake. When selecting this option the romstage is responsible for
 +
determing a stack location to use for loading the ramstage.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM || toplevel || bool || Cache the relocated ramstage outside of cbmem. ||
 +
The relocated ramstage is saved in an area specified by the
 +
by the board and/or chipset.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NO_STAGE_CACHE || toplevel || bool ||  ||
 +
Do not save any component in stage cache for resume path. On resume,
 +
all components would be read back from CBFS again.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SKIP_MAX_REBOOT_CNT_CLEAR || toplevel || bool || Do not clear reboot count after successful boot ||
 +
Do not clear the reboot count immediately after successful boot.
 +
Set to allow the payload to control normal/fallback image recovery.
 +
Note that it is the responsibility of the payload to reset the
 +
normal boot bit to 1 after each successsful boot.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| UPDATE_IMAGE || toplevel || bool || Update existing coreboot.rom image ||
 +
If this option is enabled, no new coreboot.rom file
 +
is created. Instead it is expected that there already
 +
is a suitable file for further processing.
 +
The bootblock will not be modified.
 +
 
 +
If unsure, select 'N'
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| GENERIC_GPIO_LIB || toplevel || bool ||  ||
 +
If enabled, compile the generic GPIO library. A "generic" GPIO
 +
implies configurability usually found on SoCs, particularly the
 +
ability to control internal pull resistors.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOARD_ID_AUTO || toplevel || bool ||  ||
 +
Mainboards that can read a board ID from the hardware straps
 +
(ie. GPIO) select this configuration option.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOARD_ID_MANUAL || toplevel || bool ||  ||
 +
If you want to maintain a board ID, but the hardware does not
 +
have straps to automatically determine the ID, you can say Y
 +
here and add a file named 'board_id' to CBFS. If you don't know
 +
what this is about, say N.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOARD_ID_STRING || toplevel || string || Board ID ||
 +
This string is placed in the 'board_id' CBFS file for indicating
 +
board type.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RAM_CODE_SUPPORT || toplevel || bool ||  ||
 +
If enabled, coreboot discovers RAM configuration (value obtained by
 +
reading board straps) and stores it in coreboot table.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOTSPLASH_IMAGE || toplevel || bool || Add a bootsplash image ||
 +
Select this option if you have a bootsplash image that you would
 +
like to add to your ROM.
 +
 
 +
This will only add the image to the ROM. To actually run it check
 +
options under 'Display' section.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOTSPLASH_FILE || toplevel || string || Bootsplash path and filename ||
 +
The path and filename of the file to use as graphical bootsplash
 +
screen. The file format has to be jpg.
  
 
||
 
||
Line 88: Line 289:
 
! align="left" | Menu: Mainboard || || || ||
 
! align="left" | Menu: Mainboard || || || ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOARD_LENOVO_X60 || mainboard/lenovo || bool || ThinkPad X60 / X60s ||  
+
| UART_FOR_CONSOLE || mainboard/intel/mohonpeak || int || ||  
The following X60 series ThinkPad machines have been verified to
+
The Mohon Peak board uses COM2 (2f8) for the serial console.
work correctly:
+
  
ThinkPad X60s (Model 1702, 1703)
+
||
ThinkPad X60 (Model 1709)
+
|- bgcolor="#eeeeee"
 +
| PAYLOAD_CONFIGFILE || mainboard/intel/mohonpeak || string || ||
 +
The Avoton/Rangeley chip does not allow devices to write into the 0xe000
 +
segment.  This means that USB/SATA devices will not work in SeaBIOS unless
 +
we put the SeaBIOS buffer area down in the 0x9000 segment.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOARD_LENOVO_T60 || mainboard/lenovo || bool || ThinkPad T60 / T60p ||  
+
| UART_FOR_CONSOLE || mainboard/intel/littleplains || int || ||  
The following T60 series ThinkPad machines have been verified to
+
The Little Plains board uses COM2 (2f8) for the serial console.
work correctly:
+
  
Thinkpad T60p (Model 2007)
+
||
 +
|- bgcolor="#eeeeee"
 +
| PAYLOAD_CONFIGFILE || mainboard/intel/littleplains || string ||  ||
 +
The Avoton/Rangeley chip does not allow devices to write into the 0xe000
 +
segment.  This means that USB/SATA devices will not work in SeaBIOS unless
 +
we put the SeaBIOS buffer area down in the 0x9000 segment.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| GALILEO_GEN2 || mainboard/intel/galileo || bool || Board generation: GEN1 (n) or GEN2 (y) ||
 +
The coreboot binary will configure only one generation of the Galileo
 +
board since coreboot can not determine the board generation at
 +
runtime.  Select which generation of the Galileo that coreboot
 +
should initialize.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_FILE || mainboard/intel/strago || string ||  ||
 +
The C0 version of the video bios gets computed from this name
 +
so that they can both be added.  Only the correct one for the
 +
system will be run.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_ID || mainboard/intel/strago || string ||  ||
 +
The VGA_BIOS_ID for the C0 version of the video bios is hardcoded
 +
in soc/intel/braswell/Makefile.inc as 8086,22b1
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_DP3_DAUGHTER_CARD_IN_J120 || mainboard/amd/lamar || bool || Use J120 as an additional graphics port ||
 +
The PCI Express slot at J120 can be configured as an additional
 +
DisplayPort connector using an adapter card from AMD or as a normal
 +
PCI Express (x4) slot.
 +
 
 +
By default, the connector is configured as a PCI Express (x4) slot.
 +
 
 +
Select this option to enable the slot for use with one of AMD's
 +
passive graphics port expander cards (only available from AMD).
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_PART_NUMBER || mainboard/google/nyan_blaze || string || BCT boot media ||
 +
Which boot media to configure the BCT for.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NYAN_BLAZE_BCT_CFG_SPI || mainboard/google/nyan_blaze || bool || SPI ||
 +
Configure the BCT for booting from SPI.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NYAN_BLAZE_BCT_CFG_EMMC || mainboard/google/nyan_blaze || bool || eMMC ||
 +
Configure the BCT for booting from eMMC.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOT_MEDIA_SPI_BUS || mainboard/google/nyan_blaze || int || SPI bus with boot media ROM ||
 +
Which SPI bus the boot media is connected to.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOT_MEDIA_SPI_CHIP_SELECT || mainboard/google/nyan_blaze || int || Chip select for SPI boot media ||
 +
Which chip select to use for boot media.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DISPLAY_SPD_DATA || mainboard/google/cyan || bool || Display Memory Serial Presence Detect Data ||
 +
When enabled displays the memory configuration data.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_FILE || mainboard/google/cyan || string ||  ||
 +
The C0 version of the video bios gets computed from this name
 +
so that they can both be added.  Only the correct one for the
 +
system will be run.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_ID || mainboard/google/cyan || string ||  ||
 +
The VGA_BIOS_ID for the C0 version of the video bios is hardcoded
 +
in soc/intel/braswell/Makefile.inc as 8086,22b1
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_PART_NUMBER || mainboard/google/rush_ryu || string || BCT boot media ||
 +
Which boot media to configure the BCT for.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RUSH_RYU_BCT_CFG_SPI || mainboard/google/rush_ryu || bool || SPI ||
 +
Configure the BCT for booting from SPI.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RUSH_RYU_BCT_CFG_EMMC || mainboard/google/rush_ryu || bool || eMMC ||
 +
Configure the BCT for booting from eMMC.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOT_MEDIA_SPI_BUS || mainboard/google/rush_ryu || int || SPI bus with boot media ROM ||
 +
Which SPI bus the boot media is connected to.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOT_MEDIA_SPI_CHIP_SELECT || mainboard/google/rush_ryu || int || Chip select for SPI boot media ||
 +
Which chip select to use for boot media.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DRAM_SIZE_MB || mainboard/google/smaug || int || BCT boot media ||
 +
Which boot media to configure the BCT for.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SMAUG_BCT_CFG_SPI || mainboard/google/smaug || bool || SPI ||
 +
Configure the BCT for booting from SPI.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SMAUG_BCT_CFG_EMMC || mainboard/google/smaug || bool || eMMC ||
 +
Configure the BCT for booting from eMMC.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOT_MEDIA_SPI_BUS || mainboard/google/smaug || int || SPI bus with boot media ROM ||
 +
Which SPI bus the boot media is connected to.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOT_MEDIA_SPI_CHIP_SELECT || mainboard/google/smaug || int || Chip select for SPI boot media ||
 +
Which chip select to use for boot media.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DRAM_SIZE_MB || mainboard/google/rush || int || BCT boot media ||
 +
Which boot media to configure the BCT for.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RUSH_BCT_CFG_SPI || mainboard/google/rush || bool || SPI ||
 +
Configure the BCT for booting from SPI.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RUSH_BCT_CFG_EMMC || mainboard/google/rush || bool || eMMC ||
 +
Configure the BCT for booting from eMMC.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOT_MEDIA_SPI_BUS || mainboard/google/rush || int || SPI bus with boot media ROM ||
 +
Which SPI bus the boot media is connected to.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOT_MEDIA_SPI_CHIP_SELECT || mainboard/google/rush || int || Chip select for SPI boot media ||
 +
Which chip select to use for boot media.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_PART_NUMBER || mainboard/google/nyan_big || string || BCT boot media ||
 +
Which boot media to configure the BCT for.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NYAN_BIG_BCT_CFG_SPI || mainboard/google/nyan_big || bool || SPI ||
 +
Configure the BCT for booting from SPI.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NYAN_BIG_BCT_CFG_EMMC || mainboard/google/nyan_big || bool || eMMC ||
 +
Configure the BCT for booting from eMMC.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOT_MEDIA_SPI_BUS || mainboard/google/nyan_big || int || SPI bus with boot media ROM ||
 +
Which SPI bus the boot media is connected to.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOT_MEDIA_SPI_CHIP_SELECT || mainboard/google/nyan_big || int || Chip select for SPI boot media ||
 +
Which chip select to use for boot media.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DRAM_SIZE_MB || mainboard/google/foster || int || BCT boot media ||
 +
Which boot media to configure the BCT for.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FOSTER_BCT_CFG_SPI || mainboard/google/foster || bool || SPI ||
 +
Configure the BCT for booting from SPI.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FOSTER_BCT_CFG_EMMC || mainboard/google/foster || bool || eMMC ||
 +
Configure the BCT for booting from eMMC.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOT_MEDIA_SPI_BUS || mainboard/google/foster || int || SPI bus with boot media ROM ||
 +
Which SPI bus the boot media is connected to.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOT_MEDIA_SPI_CHIP_SELECT || mainboard/google/foster || int || Chip select for SPI boot media ||
 +
Which chip select to use for boot media.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_PART_NUMBER || mainboard/google/nyan || string || BCT boot media ||
 +
Which boot media to configure the BCT for.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NYAN_BCT_CFG_SPI || mainboard/google/nyan || bool || SPI ||
 +
Configure the BCT for booting from SPI.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NYAN_BCT_CFG_EMMC || mainboard/google/nyan || bool || eMMC ||
 +
Configure the BCT for booting from eMMC.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOT_MEDIA_SPI_BUS || mainboard/google/nyan || int || SPI bus with boot media ROM ||
 +
Which SPI bus the boot media is connected to.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOT_MEDIA_SPI_CHIP_SELECT || mainboard/google/nyan || int || Chip select for SPI boot media ||
 +
Which chip select to use for boot media.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| UART_FOR_CONSOLE || mainboard/adi/rcc-dff || int ||  ||
 +
The Mohon Peak board uses COM2 (2f8) for the serial console.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PAYLOAD_CONFIGFILE || mainboard/adi/rcc-dff || string ||  ||
 +
The Avoton/Rangeley chip does not allow devices to write into the 0xe000
 +
segment.  This means that USB/SATA devices will not work in SeaBIOS unless
 +
we put the SeaBIOS buffer area down in the 0x9000 segment.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOARD_ASUS_F2A85_M_DDR3_VOLT_135 || mainboard/asus/f2a85-m || bool || 1.35V ||
 +
Set DRR3 memory voltage to 1.35V
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOARD_ASUS_F2A85_M_DDR3_VOLT_150 || mainboard/asus/f2a85-m || bool || 1.50V ||
 +
Set DRR3 memory voltage to 1.50V
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOARD_ASUS_F2A85_M_DDR3_VOLT_165 || mainboard/asus/f2a85-m || bool || 1.65V ||
 +
Set DRR3 memory voltage to 1.65V
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_135 || mainboard/asus/f2a85-m_le || bool || 1.35V ||
 +
Set DRR3 memory voltage to 1.35V
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_150 || mainboard/asus/f2a85-m_le || bool || 1.50V ||
 +
Set DRR3 memory voltage to 1.50V
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_165 || mainboard/asus/f2a85-m_le || bool || 1.65V ||
 +
Set DRR3 memory voltage to 1.65V
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DRIVERS_PS2_KEYBOARD || mainboard/purism/librem13 || None ||  ||
 +
Default PS/2 Keyboard to enabled on this board.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DRIVERS_UART_8250IO || mainboard/purism/librem13 || None ||  ||
 +
This platform does not have any way to get standard
 +
serial output so disable it by default.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NO_POST || mainboard/purism/librem13 || int ||  ||
 +
This platform does not have any way to see POST codes
 +
so disable them by default.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || was acquired by ADLINK ||
 +
|- bgcolor="#eeeeee"
 +
| ONBOARD_UARTS_RS485 || mainboard/lippert/spacerunner-lx || bool || Switch on-board serial ports to RS485 ||
 +
If selected, both on-board serial ports will operate in RS485 mode
 +
instead of RS232.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ONBOARD_IDE_SLAVE || mainboard/lippert/spacerunner-lx || bool || Make on-board SSD act as Slave ||
 +
If selected, the on-board SSD will act as IDE Slave instead of Master.
  
 
||
 
||
Line 140: Line 640:
  
 
||
 
||
|- bgcolor="#eeeeee"
+
|- bgcolor="#6699dd"
| ONBOARD_UARTS_RS485 || mainboard/lippert/spacerunner-lx || bool || Switch on-board serial ports to RS485 ||  
+
! align="left" | Menu: On-Chip Device Power Down Control || || || ||
If selected, both on-board serial ports will operate in RS485 mode
+
instead of RS232.
+
  
||
+
|- bgcolor="#6699dd"
 +
! align="left" | Menu: Watchdog Timer setting || || || ||
 +
 
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: IDE controller setting || || || ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ONBOARD_IDE_SLAVE || mainboard/lippert/spacerunner-lx || bool || Make on-board SSD act as Slave ||  
+
| IDE_STANDARD_COMPATIBLE || mainboard/dmp/vortex86ex || bool || Standard IDE Compatible ||  
If selected, the on-board SSD will act as IDE Slave instead of Master.
+
Built-in IDE controller PCI vendor/device ID is 17F3:1012, which
 +
is not recognized by some OSes.
 +
 
 +
This option can change IDE controller PCI vendor/device ID to
 +
other value for software compatibility.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SIO_PORT || mainboard/supermicro/h8qgi || hex || ||  
+
| IDE_COMPATIBLE_SELECTION || mainboard/dmp/vortex86ex || hex || IDE Compatible Selection ||  
though UARTs are on the NUVOTON BMC, port 0x164E
+
IDE controller PCI vendor/device ID value setting.
PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E
+
 
 +
Higher 16-bit is vendor ID, lower 16-bit is device ID.
  
 
||
 
||
 +
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: GPIO setting || || || ||
 +
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: UART setting || || || ||
 +
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: LPT setting || || || ||
 +
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || see under vendor LiPPERT ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOARD_ROMSIZE_KB_16384 || mainboard || bool || ROM chip size ||  
+
| BOARD_ROMSIZE_KB_65536 || mainboard || bool || ROM chip size ||  
 
Select the size of the ROM chip you intend to flash coreboot on.
 
Select the size of the ROM chip you intend to flash coreboot on.
  
 
The build system will take care of creating a coreboot.rom file
 
The build system will take care of creating a coreboot.rom file
 
of the matching size.
 
of the matching size.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| COREBOOT_ROMSIZE_KB_64 || mainboard || bool || 64 KB ||
 +
Choose this option if you have a 64 KB ROM chip.
  
 
||
 
||
Line 198: Line 722:
 
| COREBOOT_ROMSIZE_KB_8192 || mainboard || bool || 8192 KB (8 MB) ||  
 
| COREBOOT_ROMSIZE_KB_8192 || mainboard || bool || 8192 KB (8 MB) ||  
 
Choose this option if you have a 8192 KB (8 MB) ROM chip.
 
Choose this option if you have a 8192 KB (8 MB) ROM chip.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| COREBOOT_ROMSIZE_KB_12288 || mainboard || bool || 12288 KB (12 MB) ||
 +
Choose this option if you have a 12288 KB (12 MB) ROM chip.
  
 
||
 
||
Line 203: Line 732:
 
| COREBOOT_ROMSIZE_KB_16384 || mainboard || bool || 16384 KB (16 MB) ||  
 
| COREBOOT_ROMSIZE_KB_16384 || mainboard || bool || 16384 KB (16 MB) ||  
 
Choose this option if you have a 16384 KB (16 MB) ROM chip.
 
Choose this option if you have a 16384 KB (16 MB) ROM chip.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| COREBOOT_ROMSIZE_KB_32768 || mainboard || bool || 32768 KB (32 MB) ||
 +
Choose this option if you have a 32768 KB (32 MB) ROM chip.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| COREBOOT_ROMSIZE_KB_65536 || mainboard || bool || 65536 KB (64 MB) ||
 +
Choose this option if you have a 65536 KB (64 MB) ROM chip.
  
 
||
 
||
Line 217: Line 756:
  
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| CBFS_SIZE || toplevel || hex || Size of CBFS filesystem in ROM ||
 +
This is the part of the ROM actually managed by CBFS, located at the
 +
end of the ROM (passed through cbfstool -o) on x86 and at at the start
 +
of the ROM (passed through cbfstool -s) everywhere else. It defaults
 +
to span the whole ROM on all but Intel systems that use an Intel Firmware
 +
Descriptor.  It can be overridden to make coreboot live alongside other
 +
components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
 +
binaries.
  
|- bgcolor="#6699dd"
+
||
! align="left" | Menu: Architecture (x86) || || || ||
+
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| UPDATE_IMAGE || arch/x86 || bool || Update existing coreboot.rom image ||  
+
| FMDFILE || toplevel || string || fmap description file in fmd format ||  
If this option is enabled, no new coreboot.rom file
+
The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
is created. Instead it is expected that there already
+
but in some cases more complex setups are required.
is a suitable file for further processing.
+
When an fmd is specified, it overrides the default format.
The bootblock will not be modified.
+
  
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_HAS_TPM2 || toplevel || bool ||  ||
 +
There is a TPM device installed on the mainboard, and it is
 +
compliant with version 2 TCG TPM specification. Could be connected
 +
over LPC, SPI or I2C.
  
 +
||
 +
 +
|- bgcolor="#eeeeee"
 +
| CBFS_AUTOGEN_ATTRIBUTES || toplevel || bool ||  ||
 +
If this option is selected, every file in cbfs which has a constraint
 +
regarding position or alignment will get an additional file attribute
 +
which describes this constraint.
 +
 +
||
 
|- bgcolor="#6699dd"
 
|- bgcolor="#6699dd"
 
! align="left" | Menu: Chipset || || || ||
 
! align="left" | Menu: Chipset || || || ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || SoC ||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_DO_DSI_INIT || soc/nvidia/tegra210 || bool || Use dsi graphics interface ||
 +
Initialize dsi display
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_DO_SOR_INIT || soc/nvidia/tegra210 || bool || Use dp graphics interface ||
 +
Initialize dp display
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_SERIAL_TEGRA210_UARTA || soc/nvidia/tegra210 || bool || UARTA ||
 +
Serial console on UART A.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_SERIAL_TEGRA210_UARTB || soc/nvidia/tegra210 || bool || UARTB ||
 +
Serial console on UART B.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_SERIAL_TEGRA210_UARTC || soc/nvidia/tegra210 || bool || UARTC ||
 +
Serial console on UART C.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_SERIAL_TEGRA210_UARTD || soc/nvidia/tegra210 || bool || UARTD ||
 +
Serial console on UART D.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_SERIAL_TEGRA210_UARTE || soc/nvidia/tegra210 || bool || UARTE ||
 +
Serial console on UART E.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_SERIAL_TEGRA210_UART_ADDRESS || soc/nvidia/tegra210 || hex ||  ||
 +
Map the UART names to the respective MMIO addres.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOTROM_SDRAM_INIT || soc/nvidia/tegra210 || bool || SoC BootROM does SDRAM init with full BCT ||
 +
Use during Foster LPDDR4 bringup.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TRUSTZONE_CARVEOUT_SIZE_MB || soc/nvidia/tegra210 || hex || Size of Trust Zone region ||
 +
Size of Trust Zone area in MiB to reserve in memory map.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TTB_SIZE_MB || soc/nvidia/tegra210 || hex || Size of TTB ||
 +
Maximum size of Translation Table Buffer in MiB.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SEC_COMPONENT_SIZE_MB || soc/nvidia/tegra210 || hex || Size of resident EL3 components ||
 +
Maximum size of resident EL3 components in MiB including BL31 and
 +
Secure OS.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_MTC || soc/nvidia/tegra210 || bool || Add external Memory controller Training Code binary ||
 +
Select this option to add emc training firmware
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MTC_FILE || soc/nvidia/tegra210 || string || tegra mtc firmware filename ||
 +
The filename of the mtc firmware
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MTC_DIRECTORY || soc/nvidia/tegra210 || string || Directory where MTC firmware file is located ||
 +
Path to directory where MTC firmware file is located.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MTC_ADDRESS || soc/nvidia/tegra210 || hex ||  ||
 +
The DRAM location where MTC firmware to be loaded in. This location
 +
needs to be consistent with the location defined in tegra_mtc.ld
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_DO_DSI_INIT || soc/nvidia/tegra132 || bool || Use dsi graphics interface ||
 +
Initialize dsi display
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_DO_SOR_INIT || soc/nvidia/tegra132 || bool || Use dp graphics interface ||
 +
Initialize dp display
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MTS_DIRECTORY || soc/nvidia/tegra132 || string || Directory where MTS microcode files are located ||
 +
Path to directory where MTS microcode files are located.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TRUSTZONE_CARVEOUT_SIZE_MB || soc/nvidia/tegra132 || hex || Size of Trust Zone region ||
 +
Size of Trust Zone area in MiB to reserve in memory map.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOTROM_SDRAM_INIT || soc/nvidia/tegra132 || bool || SoC BootROM does SDRAM init with full BCT ||
 +
Use during Ryu LPDDR3 bringup
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_FSP_BAYTRAIL || soc/intel/fsp_baytrail || bool ||  ||
 +
Bay Trail I part support using the Intel FSP.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SMM_TSEG_SIZE || soc/intel/fsp_baytrail || hex ||  ||
 +
This is set by the FSP
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_ID || soc/intel/fsp_baytrail || string ||  ||
 +
This is the default PCI ID for the Bay Trail graphics
 +
devices.  This string names the vbios ROM in cbfs.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_BUILTIN_COM1 || soc/intel/fsp_baytrail || bool || Enable built-in legacy Serial Port ||
 +
The Baytrail SOC has one legacy serial port. Choose this option to
 +
configure the pads and enable it. This serial port can be used for
 +
the debug console.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_BAYTRAIL_GFX_INIT || soc/intel/fsp_baytrail || bool ||  ||
 +
Enabling this option will activate graphics init code. With this init,
 +
the graphic power gate registers will be initialized before
 +
VBIOS is executed.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_FILE || soc/intel/fsp_baytrail/fsp || string ||  ||
 +
The path and filename of the Intel FSP binary for this platform.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_LOC || soc/intel/fsp_baytrail/fsp || hex ||  ||
 +
The location in CBFS that the FSP is located. This must match the
 +
value that is set in the FSP binary.  If the FSP needs to be moved,
 +
rebase the FSP with Intel's BCT (tool).
 +
 +
The Bay Trail FSP is built with a preferred base address of
 +
0xFFFC0000.
 +
 +
||
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_CMC || soc/intel/sch || bool || Add a CMC state machine binary ||
 +
Select this option to add a CMC state machine binary to
 +
the resulting coreboot image.
 +
 +
Note: Without this binary coreboot will not work
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CMC_FILE || soc/intel/sch || string || Intel CMC path and filename ||
 +
The path and filename of the file to use as CMC state machine
 +
binary.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_BRASWELL || soc/intel/braswell || bool ||  ||
 +
Braswell M/D part support.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_RAM_SIZE || soc/intel/braswell || hex || Temporary RAM Size ||
 +
The size of the cache-as-ram region required during bootblock
 +
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
 +
must add up to a power of 2.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_RAM_ROMSTAGE_STACK_SIZE || soc/intel/braswell || hex ||  ||
 +
The amount of anticipated stack usage from the data cache
 +
during pre-ram rom stage execution.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RESET_ON_INVALID_RAMSTAGE_CACHE || soc/intel/braswell || bool || Reset the system on S3 wake when ramstage cache invalid. ||
 +
The haswell romstage code caches the loaded ramstage program
 +
in SMM space. On S3 wake the romstage will copy over a fresh
 +
ramstage that was cached in the SMM space. This option determines
 +
the action to take when the ramstage cache is invalid. If selected
 +
the system will reset otherwise the ramstage will be reloaded from
 +
cbfs.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_BUILTIN_COM1 || soc/intel/braswell || bool || Enable builtin COM1 Serial Port ||
 +
The PMC has a legacy COM1 serial port. Choose this option to
 +
configure the pads and enable it. This serial port can be used for
 +
the debug console.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_APOLLOLAKE || soc/intel/apollolake || bool ||  ||
 +
Intel Apollolake support
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TPM_ON_FAST_SPI || soc/intel/apollolake || bool ||  ||
 +
TPM part is conntected on Fast SPI interface, but the LPC MMIO
 +
TPM transactions are decoded and serialized over the SPI interface.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_RAM_SIZE || soc/intel/apollolake || hex || Length in bytes of cache-as-RAM ||
 +
The size of the cache-as-ram region required during bootblock
 +
and/or romstage.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_BSP_STACK_SIZE || soc/intel/apollolake || hex ||  ||
 +
The amount of anticipated stack usage in CAR by bootblock and
 +
other stages.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ROMSTAGE_ADDR || soc/intel/apollolake || hex ||  ||
 +
The base address (in CAR) where romstage should be linked
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VERSTAGE_ADDR || soc/intel/apollolake || hex ||  ||
 +
The base address (in CAR) where verstage should be linked
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_M_ADDR || soc/intel/apollolake || hex ||  ||
 +
The address FSP-M will be relocated to during build time
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NEED_LBP2 || soc/intel/apollolake || bool || Write contents for logical boot partition 2. ||
 +
Write the contents from a file into the logical boot partition 2
 +
region defined by LBP2_FMAP_NAME.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| LBP2_FMAP_NAME || soc/intel/apollolake || string || Name of FMAP region to put logical boot partition 2 ||
 +
Name of FMAP region to write logical boot partition 2 data.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| LBP2_FILE_NAME || soc/intel/apollolake || string || Path of file to write to logical boot partition 2 region ||
 +
Name of file to store in the logical boot partition 2 region.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NEED_IFWI || soc/intel/apollolake || bool || Write content into IFWI region ||
 +
Write the content from a file into IFWI region defined by
 +
IFWI_FMAP_NAME.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| IFWI_FMAP_NAME || soc/intel/apollolake || string || Name of FMAP region to pull IFWI into ||
 +
Name of FMAP region to write IFWI.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| IFWI_FILE_NAME || soc/intel/apollolake || string || Path of file to write to IFWI region ||
 +
Name of file to store in the IFWI region.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NHLT_DMIC_2CH_16B || soc/intel/apollolake || bool ||  ||
 +
Include DSP firmware settings for 2 channel 16B DMIC array.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NHLT_MAX98357 || soc/intel/apollolake || bool ||  ||
 +
Include DSP firmware settings for headset codec.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NHLT_DA7219 || soc/intel/apollolake || bool ||  ||
 +
Include DSP firmware settings for headset codec.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_BAYTRAIL || soc/intel/baytrail || bool ||  ||
 +
Bay Trail M/D part support.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_MRC || soc/intel/baytrail || bool || Add a Memory Reference Code binary ||
 +
Select this option to add a blob containing
 +
memory reference code.
 +
Note: Without this binary coreboot will not work
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MRC_FILE || soc/intel/baytrail || string || Intel memory refeference code path and filename ||
 +
The path and filename of the file to use as System Agent
 +
binary. Note that this points to the sandybridge binary file
 +
which is will not work, but it serves its purpose to do builds.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_RAM_SIZE || soc/intel/baytrail || hex ||  ||
 +
The size of the cache-as-ram region required during bootblock
 +
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
 +
must add up to a power of 2.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_RAM_MRC_VAR_SIZE || soc/intel/baytrail || hex ||  ||
 +
The amount of cache-as-ram region required by the reference code.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_RAM_ROMSTAGE_STACK_SIZE || soc/intel/baytrail || hex ||  ||
 +
The amount of anticipated stack usage from the data cache
 +
during pre-RAM ROM stage execution.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RESET_ON_INVALID_RAMSTAGE_CACHE || soc/intel/baytrail || bool || Reset the system on S3 wake when ramstage cache invalid. ||
 +
The baytrail romstage code caches the loaded ramstage program
 +
in SMM space. On S3 wake the romstage will copy over a fresh
 +
ramstage that was cached in the SMM space. This option determines
 +
the action to take when the ramstage cache is invalid. If selected
 +
the system will reset otherwise the ramstage will be reloaded from
 +
cbfs.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_BUILTIN_COM1 || soc/intel/baytrail || bool || Enable builtin COM1 Serial Port ||
 +
The PMC has a legacy COM1 serial port. Choose this option to
 +
configure the pads and enable it. This serial port can be used for
 +
the debug console.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_REFCODE_BLOB || soc/intel/baytrail || bool || An external reference code blob should be put into cbfs. ||
 +
The reference code blob will be placed into cbfs.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| REFCODE_BLOB_FILE || soc/intel/baytrail || string || Path and filename to reference code blob. ||
 +
The path and filename to the file to be added to cbfs.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_QUARK || soc/intel/quark || bool ||  ||
 +
Intel Quark support
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_BUILTIN_HSUART0 || soc/intel/quark || bool || Enable built-in HSUART0 ||
 +
The Quark SoC has two HSUART. Choose this option to configure the pads
 +
and enable HSUART0, which can be used for the debug console.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_BUILTIN_HSUART1 || soc/intel/quark || bool || Enable built-in HSUART1 ||
 +
The Quark SoC has two HSUART. Choose this option to configure the pads
 +
and enable HSUART1, which can be used for the debug console.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TTYS0_BASE || soc/intel/quark || hex || HSUART Base Address ||
 +
Memory mapped MMIO of HSUART.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_DEBUG_LED || soc/intel/quark || bool ||  ||
 +
Enable the use of the SD LED for early debugging before serial output
 +
is available.  Setting this LED indicates that control has reached the
 +
desired check point.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_DEBUG_LED_ESRAM || soc/intel/quark || bool || SD LED indicates ESRAM initialized ||
 +
Indicate that ESRAM has been successfully initialized.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_DEBUG_LED_FINDFSP || soc/intel/quark || bool || SD LED indicates fsp.bin file was found ||
 +
Indicate that fsp.bin was found.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_DEBUG_LED_TEMPRAMINIT || soc/intel/quark || bool || SD LED indicates TempRamInit was successful ||
 +
Indicate that TempRamInit was successful.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CBFS_SIZE || soc/intel/quark || hex ||  ||
 +
Specify the size of the coreboot file system in the read-only (recovery)
 +
portion of the flash part.  On Quark systems the firmware image stores
 +
more than just coreboot, including:
 +
- The chipset microcode (RMU) binary file located at 0xFFF00000
 +
- Intel Trusted Execution Engine firmware
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ADD_FSP_RAW_BIN || soc/intel/quark || bool || Add the Intel FSP binary to the flash image without relocation ||
 +
Select this option to add an Intel FSP binary to
 +
the resulting coreboot image.
 +
 +
Note: Without this binary, coreboot builds relying on the FSP
 +
will not boot
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_FILE || soc/intel/quark || string || Intel FSP binary path and filename ||
 +
The path and filename of the Intel FSP binary for this platform.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_IMAGE_ID_STRING || soc/intel/quark || string || 8 byte platform string identifying the FSP platform ||
 +
8 ASCII character byte signature string that will help match the FSP
 +
binary to a supported hardware configuration.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_LOC || soc/intel/quark || hex ||  ||
 +
The location in CBFS that the FSP is located. This must match the
 +
value that is set in the FSP binary.  If the FSP needs to be moved,
 +
rebase the FSP with Intel's BCT (tool).
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_ESRAM_LOC || soc/intel/quark || hex ||  ||
 +
The location in ESRAM where a copy of the FSP binary is placed.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RELOCATE_FSP_INTO_DRAM || soc/intel/quark || bool || Relocate FSP into DRAM ||
 +
Relocate the FSP binary into DRAM before the call to SiliconInit.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ADD_RMU_FILE || soc/intel/quark || bool || Should the RMU binary be added to the flash image? ||
 +
The RMU file is required to get the chip out of reset.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RMU_FILE || soc/intel/quark || string ||  ||
 +
The path and filename of the Intel Quark RMU binary.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RMU_LOC || soc/intel/quark || hex ||  ||
 +
The location in CBFS that the RMU is located. It must match the
 +
strap-determined base address.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON || soc/intel/common || bool ||  ||
 +
common code for Intel SOCs
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_LPSS_I2C || soc/intel/common || bool ||  ||
 +
This driver supports the Intel Low Power Subsystem (LPSS) I2C
 +
controllers that are based on Synopsys DesignWare IP.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ || soc/intel/common || int ||  ||
 +
The clock speed that the I2C controller is running at, in MHz.
 +
No default is set here as this is an SOC-specific value and must
 +
be provided by the SOC when it selects this driver.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_SETS_MTRRS || soc/intel/common || bool ||  ||
 +
The SoC needs uses different access methods for reading and writing
 +
the MTRRs.  Use SoC specific routines to handle the MTRR access.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MMA || soc/intel/common || bool || enable MMA (Memory Margin Analysis) support ||
 +
Set this option to y to enable MMA (Memory Margin Analysis) support
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ADD_VBT_DATA_FILE || soc/intel/common || bool || Add a Video Bios Table (VBT) binary to CBFS ||
 +
Add a VBT file data file to CBFS. The VBT describes the integrated
 +
GPU and connections, and is needed by FSP in order to initialize the
 +
display.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VBT_FILE || soc/intel/common || string || VBT binary path and filename ||
 +
The path and filename of the VBT binary.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_FSP_BROADWELL_DE || soc/intel/fsp_broadwell_de || bool ||  ||
 +
Broadwell-DE support using the Intel FSP.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| INTEGRATED_UART || soc/intel/fsp_broadwell_de || bool || Integrated UART ports ||
 +
Use Broadwell-DE Integrated UART ports @3F8h and 2F8h.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DRIVERS_UART_8250IO || soc/intel/fsp_broadwell_de || bool || Serial port on SuperIO (Broadwell-DE's UART ports unselected) ||
 +
Select to choose SuperIO's serial port for console output.
 +
CANNOT select if intend to use SoC integrated serial ports.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_FILE || soc/intel/fsp_broadwell_de/fsp || string ||  ||
 +
The path and filename of the Intel FSP binary for this platform.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_LOC || soc/intel/fsp_broadwell_de/fsp || hex ||  ||
 +
The location in CBFS that the FSP is located. This must match the
 +
value that is set in the FSP binary.  If the FSP needs to be moved,
 +
rebase the FSP with Intel's BCT (tool).
 +
 +
The Broadwell-DE FSP is built with a preferred base address of
 +
0xffeb0000.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_MEMORY_DOWN || soc/intel/fsp_broadwell_de/fsp || bool || Enable Memory Down ||
 +
Load SPD data from ROM instead of trying to read from SMBus.
 +
 +
If the platform has DIMM sockets, say N. If memory is down, say Y and
 +
supply the appropriate SPD data for each Channel/DIMM.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT || soc/intel/fsp_broadwell_de/fsp || bool || Channel 0, DIMM 0 Present ||
 +
Select Y if Channel 0, DIMM 0 is present.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_MEMORY_DOWN_CH0DIMM0_SPD_FILE || soc/intel/fsp_broadwell_de/fsp || string || Channel 0, DIMM 0 SPD File ||
 +
Path to the file which contains the SPD data for Channel 0, DIMM 0.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT || soc/intel/fsp_broadwell_de/fsp || bool || Channel 0, DIMM 1 Present ||
 +
Select Y if Channel 0, DIMM 1 is present.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_MEMORY_DOWN_CH0DIMM1_SPD_FILE || soc/intel/fsp_broadwell_de/fsp || string || Channel 0, DIMM 1 SPD File ||
 +
Path to the file which contains the SPD data for Channel 0, DIMM 1.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT || soc/intel/fsp_broadwell_de/fsp || bool || Channel 1, DIMM 0 Present ||
 +
Select Y if Channel 1, DIMM 0 is present.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_MEMORY_DOWN_CH1DIMM0_SPD_FILE || soc/intel/fsp_broadwell_de/fsp || string || Channel 1, DIMM 0 SPD File ||
 +
Path to the file which contains the SPD data for Channel 1, DIMM 0.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT || soc/intel/fsp_broadwell_de/fsp || bool || Channel 1, DIMM 1 Present ||
 +
Select Y if Channel 1, DIMM 1 is present.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_MEMORY_DOWN_CH1DIMM1_SPD_FILE || soc/intel/fsp_broadwell_de/fsp || string || Channel 1, DIMM 1 SPD File ||
 +
Path to the file which contains the SPD data for Channel 1, DIMM 1.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_HYPERTHREADING || soc/intel/fsp_broadwell_de/fsp || bool || Enable Hyper-Threading ||
 +
Enable Intel(r) Hyper-Threading Technology for the Broadwell-DE SoC.
 +
 +
||
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_BROADWELL || soc/intel/broadwell || bool ||  ||
 +
Intel Broadwell and Haswell ULT support.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_RAM_SIZE || soc/intel/broadwell || hex ||  ||
 +
The size of the cache-as-ram region required during bootblock
 +
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
 +
must add up to a power of 2.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_RAM_MRC_VAR_SIZE || soc/intel/broadwell || hex ||  ||
 +
The amount of cache-as-ram region required by the reference code.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_RAM_ROMSTAGE_STACK_SIZE || soc/intel/broadwell || hex ||  ||
 +
The amount of anticipated stack usage from the data cache
 +
during pre-ram rom stage execution.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_MRC || soc/intel/broadwell || bool || Add a Memory Reference Code binary ||
 +
Select this option to add a Memory Reference Code binary to
 +
the resulting coreboot image.
 +
 +
Note: Without this binary coreboot will not work
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MRC_FILE || soc/intel/broadwell || string || Intel Memory Reference Code path and filename ||
 +
The filename of the file to use as Memory Reference Code binary.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PRE_GRAPHICS_DELAY || soc/intel/broadwell || int || Graphics initialization delay in ms ||
 +
On some systems, coreboot boots so fast that connected monitors
 +
(mostly TVs) won't be able to wake up fast enough to talk to the
 +
VBIOS. On those systems we need to wait for a bit before executing
 +
the VBIOS.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RESET_ON_INVALID_RAMSTAGE_CACHE || soc/intel/broadwell || bool || Reset the system on S3 wake when ramstage cache invalid. ||
 +
The romstage code caches the loaded ramstage program in SMM space.
 +
On S3 wake the romstage will copy over a fresh ramstage that was
 +
cached in the SMM space. This option determines the action to take
 +
when the ramstage cache is invalid. If selected the system will
 +
reset otherwise the ramstage will be reloaded from cbfs.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SERIRQ_CONTINUOUS_MODE || soc/intel/broadwell || bool ||  ||
 +
If you set this option to y, the serial IRQ machine will be
 +
operated in continuous mode.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_REFCODE_BLOB || soc/intel/broadwell || bool || An external reference code blob should be put into cbfs. ||
 +
The reference code blob will be placed into cbfs.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| REFCODE_BLOB_FILE || soc/intel/broadwell || string || Path and filename to reference code blob. ||
 +
The path and filename to the file to be added to cbfs.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_SKYLAKE || soc/intel/skylake || bool ||  ||
 +
Intel Skylake support
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_RAM_SIZE || soc/intel/skylake || hex || Length in bytes of cache-as-RAM ||
 +
The size of the cache-as-ram region required during bootblock
 +
and/or romstage.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EXCLUDE_NATIVE_SD_INTERFACE || soc/intel/skylake || bool ||  ||
 +
If you set this option to n, will not use native SD controller.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MONOTONIC_TIMER_MSR || soc/intel/skylake || hex ||  ||
 +
Provide a monotonic timer using the 24MHz MSR counter.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PRE_GRAPHICS_DELAY || soc/intel/skylake || int || Graphics initialization delay in ms ||
 +
On some systems, coreboot boots so fast that connected monitors
 +
(mostly TVs) won't be able to wake up fast enough to talk to the
 +
VBIOS. On those systems we need to wait for a bit before executing
 +
the VBIOS.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SERIRQ_CONTINUOUS_MODE || soc/intel/skylake || bool ||  ||
 +
If you set this option to y, the serial IRQ machine will be
 +
operated in continuous mode.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NHLT_DMIC_2CH || soc/intel/skylake || bool ||  ||
 +
Include DSP firmware settings for 2 channel DMIC array.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NHLT_DMIC_4CH || soc/intel/skylake || bool ||  ||
 +
Include DSP firmware settings for 4 channel DMIC array.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NHLT_NAU88L25 || soc/intel/skylake || bool ||  ||
 +
Include DSP firmware settings for nau88l25 headset codec.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NHLT_MAX98357 || soc/intel/skylake || bool ||  ||
 +
Include DSP firmware settings for max98357 amplifier.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NHLT_SSM4567 || soc/intel/skylake || bool ||  ||
 +
Include DSP firmware settings for ssm4567 smart amplifier.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SKIP_FSP_CAR || soc/intel/skylake || bool || Skip cache as RAM setup in FSP ||
 +
Skip Cache as RAM setup in FSP.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE || soc/broadcom/cygnus || bool || Enable DDR auto self-refresh ||
 +
Warning: M0 expects that auto self-refresh is enabled. Modify
 +
with caution.
 +
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_DRAM || soc/mediatek/mt8173 || bool || Output verbose DRAM related debug message ||
 +
This option enables additional DRAM related debug messages.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_I2C || soc/mediatek/mt8173 || bool || Output verbose I2C related debug message ||
 +
This option enables I2C related debug message.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_PMIC || soc/mediatek/mt8173 || bool || Output verbose PMIC related debug message ||
 +
This option enables PMIC related debug message.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_PMIC_WRAP || soc/mediatek/mt8173 || bool || Output verbose PMIC WRAP related debug message ||
 +
This option enables PMIC WRAP related debug message.
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOTBLOCK_CPU_INIT || soc/marvell/armada38x || string ||  ||
 +
CPU/SoC-specific bootblock code. This is useful if the
 +
bootblock must load microcode or copy data from ROM before
 +
searching for the bootblock.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| IPQ_QFN_PART || soc/qualcomm/ipq40xx || bool ||  ||
 +
Is the SoC a QFN part (as opposed to a BGA part)
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SBL_ELF || soc/qualcomm/ipq40xx || string || file name of the QCA SBL ELF ||
 +
The path and filename of the binary blob containing
 +
ipq40xx early initialization code, as supplied by the
 +
vendor.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SBL_UTIL_PATH || soc/qualcomm/ipq40xx || string || Path for utils to combine SBL_ELF and bootblock ||
 +
Path for utils to combine SBL_ELF and bootblock
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SBL_BLOB || soc/qualcomm/ipq806x || string || file name of the Qualcomm SBL blob ||
 +
The path and filename of the binary blob containing
 +
ipq806x early initialization code, as supplied by the
 +
vendor.
 +
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| || || (comment) || || CPU ||
 
| || || (comment) || || CPU ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| UPDATE_CPU_MICROCODE || cpu/amd/model_10xxx || bool || Update CPU microcode ||  
+
| RESET_ON_INVALID_RAMSTAGE_CACHE || cpu/intel/haswell || bool || Reset the system on S3 wake when ramstage cache invalid. ||  
Select this to apply patches to the CPU microcode provided by
+
The haswell romstage code caches the loaded ramstage program
AMD without source, and distributed with coreboot, to address
+
in SMM space. On S3 wake the romstage will copy over a fresh
issues in the CPU post production.
+
ramstage that was cached in the SMM space. This option determines
 +
the action to take when the ramstage cache is invalid. If selected
 +
the system will reset otherwise the ramstage will be reloaded from
 +
cbfs.
  
Microcode updates distributed with coreboot are not necessarily
+
||
the latest version available from AMD. Updates are only applied
+
|- bgcolor="#eeeeee"
if they are newer than the microcode already in your CPU.
+
| CPU_INTEL_FIRMWARE_INTERFACE_TABLE || cpu/intel/fit || None ||  ||
 +
This option selects building a Firmware Interface Table (FIT).
  
Unselect this to let Fam10h CPUs run with microcode as shipped
+
||
from factory. No binary microcode patches will be included in the
+
|- bgcolor="#eeeeee"
coreboot image in that case, which can help with creating an image
+
| CPU_INTEL_NUM_FIT_ENTRIES || cpu/intel/fit || int ||  ||
for which complete source code is available, which in turn might
+
This option selects the number of empty entries in the FIT table.
simplify license compliance.
+
  
Microcode updates intend to solve issues that have been discovered
+
||
after CPU production. The common case is that systems work as
+
||
intended with updated microcode, but we have also seen cases where
+
|- bgcolor="#eeeeee"
issues were solved by not applying the microcode updates.
+
| CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED || cpu/intel/turbo || None ||  ||
 +
This option indicates that the turbo mode setting is not package
 +
scoped. i.e. enable_turbo() needs to be called on not just the bsp
  
Note that some operating system include these same microcode
+
||
patches, so you may need to also disable microcode updates in
+
your operating system in order for this option to matter.
+
  
 
||
 
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| GEODE_VSA_FILE || cpu/amd/model_gx2 || bool || Add a VSA image ||  
+
| GEODE_VSA_FILE || cpu/amd/geode_gx2 || bool || Add a VSA image ||  
 
Select this option if you have an AMD Geode GX2 vsa that you would
 
Select this option if you have an AMD Geode GX2 vsa that you would
 
like to add to your ROM.
 
like to add to your ROM.
Line 270: Line 1,611:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VSA_FILENAME || cpu/amd/model_gx2 || string || AMD Geode GX2 VSA path and filename ||  
+
| VSA_FILENAME || cpu/amd/geode_gx2 || string || AMD Geode GX2 VSA path and filename ||  
 
The path and filename of the file to use as VSA.
 
The path and filename of the file to use as VSA.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| GEODE_VSA_FILE || cpu/amd/model_lx || bool || Add a VSA image ||  
+
| GEODE_VSA_FILE || cpu/amd/geode_lx || bool || Add a VSA image ||  
 
Select this option if you have an AMD Geode LX vsa that you would
 
Select this option if you have an AMD Geode LX vsa that you would
 
like to add to your ROM.
 
like to add to your ROM.
Line 284: Line 1,625:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VSA_FILENAME || cpu/amd/model_lx || string || AMD Geode LX VSA path and filename ||  
+
| VSA_FILENAME || cpu/amd/geode_lx || string || AMD Geode LX VSA path and filename ||  
 
The path and filename of the file to use as VSA.
 
The path and filename of the file to use as VSA.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| XIP_ROM_SIZE || cpu/amd/agesa || hex ||  ||
 +
Overwride the default write through caching size as 1M Bytes.
 +
On some AMD platforms, one socket supports 2 or more kinds of
 +
processor family, compiling several CPU families agesa code
 +
will increase the romstage size.
 +
In order to execute romstage in place on the flash ROM,
 +
more space is required to be set as write through caching.
  
 
||
 
||
Line 294: Line 1,645:
 
Warning: Only enable this option when debuging or tracing AMD AGESA code.
 
Warning: Only enable this option when debuging or tracing AMD AGESA code.
  
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_AMD_SOCKET_G34 || cpu/amd/agesa/family15 || bool ||  ||
 +
AMD G34 Socket
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_AMD_SOCKET_C32 || cpu/amd/agesa/family15 || bool ||  ||
 +
AMD C32 Socket
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_AMD_SOCKET_AM3R2 || cpu/amd/agesa/family15 || bool ||  ||
 +
AMD AM3r2 Socket
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL || cpu/amd/agesa/family15 || bool || Redirect AGESA IDS_HDT_CONSOLE to serial console ||
 +
This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console.
 +
 +
Warning: Only enable this option when debuging or tracing AMD AGESA code.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FORCE_AM1_SOCKET_SUPPORT || cpu/amd/agesa/family16kb || bool ||  ||
 +
Force AGESA to ignore package type mismatch between CPU and northbridge
 +
in memory code. This enables Socket AM1 support with current AGESA
 +
version for Kabini platform.
 +
Enable this option only if you have Socket AM1 board.
 +
Note that the AGESA release shipped with coreboot does not officially
 +
support the AM1 socket. Selecting this option might damage your hardware.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| XIP_ROM_SIZE || cpu/amd/pi || hex ||  ||
 +
Overwride the default write through caching size as 1M Bytes.
 +
On some AMD platforms, one socket supports 2 or more kinds of
 +
processor family, compiling several CPU families agesa code
 +
will increase the romstage size.
 +
In order to execute romstage in place on the flash ROM,
 +
more space is required to be set as write through caching.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PARALLEL_MP || cpu/x86 || bool ||  ||
 +
This option uses common MP infrastructure for bringing up APs
 +
in parallel. It additionally provides a more flexible mechanism
 +
for sequencing the steps of bringing up the APs.
 +
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| LAPIC_MONOTONIC_TIMER || cpu/x86 || bool ||  ||
 +
Expose monotonic time using the local apic.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TSC_CONSTANT_RATE || cpu/x86 || bool ||  ||
 +
This option asserts that the TSC ticks at a known constant rate.
 +
Therefore, no TSC calibration is required.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TSC_MONOTONIC_TIMER || cpu/x86 || bool ||  ||
 +
Expose monotonic time using the TSC.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TSC_SYNC_LFENCE || cpu/x86 || bool ||  ||
 +
The CPU driver should select this if the CPU needs
 +
to execute an lfence instruction in order to synchronize
 +
rdtsc. This is true for all modern AMD CPUs.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TSC_SYNC_MFENCE || cpu/x86 || bool ||  ||
 +
The CPU driver should select this if the CPU needs
 +
to execute an mfence instruction in order to synchronize
 +
rdtsc. This is true for all modern Intel CPUs.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NO_FIXED_XIP_ROM_SIZE || cpu/x86 || bool ||  ||
 +
The XIP_ROM_SIZE Kconfig variable is used globally on x86
 +
with the assumption that all chipsets utilize this value.
 +
For the chipsets which do not use the variable it can lead
 +
to unnecessary alignment constraints in cbfs for romstage.
 +
Therefore, allow those chipsets a path to not be burdened.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SMM_MODULE_HEAP_SIZE || cpu/x86 || hex ||  ||
 +
This option determines the size of the heap within the SMM handler
 +
modules.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SERIALIZED_SMM_INITIALIZATION || cpu/x86 || bool ||  ||
 +
On some CPUs, there is a race condition in SMM.
 +
This can occur when both hyperthreads change SMM state
 +
variables in parallel without coordination.
 +
Setting this option serializes the SMM initialization
 +
to avoid an ugly hang in the boot process at the cost
 +
of a slightly longer boot time.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| X86_AMD_FIXED_MTRRS || cpu/x86 || bool ||  ||
 +
This option informs the MTRR code to use the RdMem and WrMem fields
 +
in the fixed MTRR MSRs.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PLATFORM_USES_FSP1_0 || cpu/x86 || bool ||  ||
 +
Selected for Intel processors/platform combinations that use the
 +
Intel Firmware Support Package (FSP) 1.0 for initialization.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING || cpu/x86 || bool ||  ||
 +
On certain platforms a boot speed gain can be realized if mirroring
 +
the payload data stored in non-volatile storage. On x86 systems the
 +
payload would typically live in a memory-mapped SPI part. Copying
 +
the SPI contents to RAM before performing the load can speed up
 +
the boot process.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOT_MEDIA_SPI_BUS || cpu/x86 || int ||  ||
 +
Most x86 systems which boot from SPI flash boot using bus 0.
 +
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
Line 299: Line 1,782:
 
This option is used to enable certain functions to make coreboot
 
This option is used to enable certain functions to make coreboot
 
work correctly on symmetric multi processor (SMP) systems.
 
work correctly on symmetric multi processor (SMP) systems.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AP_SIPI_VECTOR || cpu || hex ||  ||
 +
This must equal address of ap_sipi_vector from bootblock build.
  
 
||
 
||
Line 323: Line 1,811:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VAR_MTRR_HOLE || cpu || bool ||  ||  
+
| USES_MICROCODE_HEADER_FILES || cpu || bool ||  ||  
Unset this if you don't want the MTRR code to use
+
This is selected by a board or chipset to set the default for the
subtractive MTRRs
+
microcode source choice to a list of external microcode headers
  
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_MICROCODE_CBFS_GENERATE || cpu || bool || Generate from tree ||
 +
Select this option if you want microcode updates to be assembled when
 +
building coreboot and included in the final image as a separate CBFS
 +
file. Microcode will not be hard-coded into ramstage.
 +
 +
The microcode file may be removed from the ROM image at a later
 +
time with cbfstool, if desired.
 +
 +
If unsure, select this option.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_MICROCODE_CBFS_EXTERNAL_HEADER || cpu || bool || Include external microcode header files ||
 +
Select this option if you want to include external c header files
 +
containing the CPU microcode. This will be included as a separate
 +
file in CBFS.
 +
 +
A word of caution: only select this option if you are sure the
 +
microcode that you have is newer than the microcode shipping with
 +
coreboot.
 +
 +
The microcode file may be removed from the ROM image at a later
 +
time with cbfstool, if desired.
 +
 +
If unsure, select "Generate from tree"
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_MICROCODE_CBFS_NONE || cpu || bool || Do not include microcode updates ||
 +
Select this option if you do not want CPU microcode included in CBFS.
 +
Note that for some CPUs, the microcode is hard-coded into the source
 +
tree and is not loaded from CBFS. In this case, microcode will still
 +
be updated. There is a push to move all microcode to CBFS, but this
 +
change is not implemented for all CPUs.
 +
 +
This option currently applies to:
 +
- Intel SandyBridge/IvyBridge
 +
- VIA Nano
 +
 +
Microcode may be added to the ROM image at a later time with cbfstool,
 +
if desired.
 +
 +
If unsure, select "Generate from tree"
 +
 +
The GOOD:
 +
Microcode updates intend to solve issues that have been discovered
 +
after CPU production. The expected effect is that systems work as
 +
intended with the updated microcode, but we have also seen cases where
 +
issues were solved by not applying microcode updates.
 +
 +
The BAD:
 +
Note that some operating system include these same microcode patches,
 +
so you may need to also disable microcode updates in your operating
 +
system for this option to have an effect.
 +
 +
The UGLY:
 +
A word of CAUTION: some CPUs depend on microcode updates to function
 +
correctly. Not updating the microcode may leave the CPU operating at
 +
less than optimal performance, or may cause outright hangups.
 +
There are CPUs where coreboot cannot properly initialize the CPU
 +
without microcode updates
 +
For example, if running with the factory microcode, some Intel
 +
SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs
 +
will hang when changing the frequency.
 +
 +
Make sure you have a way of flashing the ROM externally before
 +
selecting this option.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_MICROCODE_MULTIPLE_FILES || cpu || bool ||  ||
 +
Select this option to install separate microcode container files into
 +
CBFS instead of using the traditional monolithic microcode file format.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_MICROCODE_HEADER_FILES || cpu || string || List of space separated microcode header files with the path ||
 +
A list of one or more microcode header files with path from the
 +
coreboot directory.  These should be separated by spaces.
 +
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| || || (comment) || || Northbridge ||
 
| || || (comment) || || Northbridge ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SVI_HIGH_FREQ || northbridge/amd/amdfam10 || bool ||  ||  
+
| OVERRIDE_CLOCK_DISABLE || northbridge/intel/i945 || bool ||  ||  
Select this for boards with a Voltage Regulator able to operate
+
Usually system firmware turns off system memory clock
at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.
+
signals to unused SO-DIMM slots to reduce EMI and power
 +
consumption.
 +
However, some boards do not like unused clock signals to
 +
be disabled.
  
 
||
 
||
|- bgcolor="#6699dd"
 
! align="left" | Menu: HyperTransport setup || || || ||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| None || northbridge/amd || None || HyperTransport frequency ||  
+
| MAXIMUM_SUPPORTED_FREQUENCY || northbridge/intel/i945 || int || ||  
This option sets the maximum permissible HyperTransport link
+
If non-zero, this designates the maximum DDR frequency
frequency.
+
the board supports, despite what the chipset should be
 +
capable of.
  
Use of this option will only limit the autodetected HT frequency.
+
||
It will not (and cannot) increase the frequency beyond the
+
|- bgcolor="#eeeeee"
autodetected limits.
+
| CHECK_SLFRCS_ON_RESUME || northbridge/intel/i945 || int ||  ||
 +
On some boards it may be neccessary to hard reset early
 +
during resume from S3 if the SLFRCS register indicates that
 +
a memory channel is not guaranteed to be in self-refresh.
 +
On other boards the check always creates a false positive,
 +
effectively making it impossible to resume.
  
This is primarily used to work around poorly designed or laid out
+
||
HT traces on certain motherboards.
+
|- bgcolor="#eeeeee"
 +
| USE_NATIVE_RAMINIT || northbridge/intel/sandybridge || bool || Use native raminit ||
 +
Select if you want to use coreboot implementation of raminit rather than
 +
System Agent/MRC.bin. You should answer Y.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| LIMIT_HT_SPEED_AUTO || northbridge/amd || bool || HyperTransport downlink width ||  
+
| MRC_FILE || northbridge/intel/sandybridge || string || Intel System Agent path and filename ||
 +
The path and filename of the file to use as System Agent
 +
binary.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_RAM_SIZE || northbridge/intel/haswell || hex ||  ||
 +
The size of the cache-as-ram region required during bootblock
 +
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
 +
must add up to a power of 2.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_RAM_MRC_VAR_SIZE || northbridge/intel/haswell || hex ||  ||
 +
The amount of cache-as-ram region required by the reference code.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_RAM_ROMSTAGE_STACK_SIZE || northbridge/intel/haswell || hex ||  ||
 +
The amount of anticipated stack usage from the data cache
 +
during pre-ram rom stage execution.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_MRC || northbridge/intel/haswell || bool || Add a System Agent binary ||
 +
Select this option to add a System Agent binary to
 +
the resulting coreboot image.
 +
 
 +
Note: Without this binary coreboot will not work
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MRC_FILE || northbridge/intel/haswell || string || Intel System Agent path and filename ||
 +
The path and filename of the file to use as System Agent
 +
binary.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PRE_GRAPHICS_DELAY || northbridge/intel/haswell || int || Graphics initialization delay in ms ||
 +
On some systems, coreboot boots so fast that connected monitors
 +
(mostly TVs) won't be able to wake up fast enough to talk to the
 +
VBIOS. On those systems we need to wait for a bit before executing
 +
the VBIOS.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_ID || northbridge/intel/fsp_sandybridge || string ||  ||
 +
This is the default PCI ID for the sandybridge/ivybridge graphics
 +
devices.  This string names the vbios ROM in cbfs.  The following
 +
PCI IDs will be remapped to load this ROM:
 +
0x80860102, 0x8086010a, 0x80860112, 0x80860116
 +
0x80860122, 0x80860126, 0x80860166
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_FILE || northbridge/intel/fsp_sandybridge/fsp || string ||  ||
 +
The path and filename of the Intel FSP binary for this platform.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_LOC || northbridge/intel/fsp_sandybridge/fsp || hex || Intel FSP Binary location in CBFS ||
 +
The location in CBFS that the FSP is located. This must match the
 +
value that is set in the FSP binary.  If the FSP needs to be moved,
 +
rebase the FSP with the Intel's BCT (tool).
 +
 
 +
The Ivy Bridge Processor/Panther Point FSP is built with a preferred
 +
base address of 0xFFF80000
 +
 
 +
||
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SDRAMPWR_4DIMM || northbridge/intel/i440bx || bool ||  ||
 +
This option affects how the SDRAMC register is programmed.
 +
Memory clock signals will not be routed properly if this option
 +
is set wrong.
 +
 
 +
If your board has 4 DIMM slots, you must use select this option, in
 +
your Kconfig file of the board. On boards with 3 DIMM slots,
 +
do _not_ select this option.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SET_TSEG_1MB || northbridge/intel/fsp_rangeley || bool || 1 MB ||
 +
Set the TSEG area to 1 MB.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SET_TSEG_2MB || northbridge/intel/fsp_rangeley || bool || 2 MB ||
 +
Set the TSEG area to 2 MB.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SET_TSEG_4MB || northbridge/intel/fsp_rangeley || bool || 4 MB ||
 +
Set the TSEG area to 4 MB.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SET_TSEG_8MB || northbridge/intel/fsp_rangeley || bool || 8 MB ||
 +
Set the TSEG area to 8 MB.
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_FILE || northbridge/intel/fsp_rangeley/fsp || string ||  ||
 +
The path and filename of the Intel FSP binary for this platform.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_LOC || northbridge/intel/fsp_rangeley/fsp || hex ||  ||
 +
The location in CBFS that the FSP is located. This must match the
 +
value that is set in the FSP binary.  If the FSP needs to be moved,
 +
rebase the FSP with Intel's BCT (tool).
 +
 
 +
The Rangeley FSP is built with a preferred base address of 0xFFF80000
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_ID || northbridge/amd/pi/00630F01 || string ||  ||
 +
The default VGA BIOS PCI vendor/device ID should be set to the
 +
result of the map_oprom_vendev() function in northbridge.c.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_ID || northbridge/amd/pi/00730F01 || string ||  ||
 +
The default VGA BIOS PCI vendor/device ID should be set to the
 +
result of the map_oprom_vendev() function in northbridge.c.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_ID || northbridge/amd/pi/00660F01 || string ||  ||
 +
The default VGA BIOS PCI vendor/device ID should be set to the
 +
result of the map_oprom_vendev() function in northbridge.c.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| REDIRECT_NBCIMX_TRACE_TO_SERIAL || northbridge/amd/cimx/rd890 || bool || Redirect AMD Northbridge CIMX Trace to serial console ||
 +
This Option allows you to redirect the AMD Northbridge CIMX
 +
Trace debug information to the serial console.
 +
 
 +
Warning: Only enable this option when debuging or tracing AMD CIMX code.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_ID || northbridge/amd/agesa/family16kb || string ||  ||
 +
The default VGA BIOS PCI vendor/device ID should be set to the
 +
result of the map_oprom_vendev() function in northbridge.c.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SVI_HIGH_FREQ || northbridge/amd/amdfam10 || bool ||  ||
 +
Select this for boards with a Voltage Regulator able to operate
 +
at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.
 +
 
 +
||
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: HyperTransport setup || || || ||
 +
|- bgcolor="#eeeeee"
 +
| SVI_HIGH_FREQ || northbridge/amd/amdfam10 || bool || HyperTransport downlink width ||  
 
This option sets the maximum permissible HyperTransport
 
This option sets the maximum permissible HyperTransport
 
downlink width.
 
downlink width.
Line 365: Line 2,103:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| LIMIT_HT_DOWN_WIDTH_16 || northbridge/amd || bool || HyperTransport uplink width ||  
+
| LIMIT_HT_DOWN_WIDTH_16 || northbridge/amd/amdfam10 || bool || HyperTransport uplink width ||  
 
This option sets the maximum permissible HyperTransport
 
This option sets the maximum permissible HyperTransport
 
uplink width.
 
uplink width.
Line 379: Line 2,117:
  
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SDRAMPWR_4DIMM || northbridge/intel/i440bx || bool ||  ||  
+
| || || (comment) || || Southbridge ||
This option affects how the SDRAMC register is programmed.
+
|- bgcolor="#eeeeee"
Memory clock signals will not be routed properly if this option
+
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/ibexpeak || bool ||  ||  
is set wrong.
+
If you set this option to y, the serial IRQ machine will be
 +
operated in continuous mode.
  
If your board has 4 DIMM slots, you must use select this option, in
+
||
your Kconfig file of the board. On boards with 3 DIMM slots,
+
|- bgcolor="#eeeeee"
do _not_ select this option.
+
| INTEL_LYNXPOINT_LP || southbridge/intel/lynxpoint || bool ||  ||
 +
Set this option to y for Lynxpont LP (Haswell ULT).
  
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/lynxpoint || bool ||  ||
 +
If you set this option to y, the serial IRQ machine will be
 +
operated in continuous mode.
  
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| ME_MBP_CLEAR_LATE || southbridge/intel/lynxpoint || bool || Defer wait for ME MBP Cleared ||
 +
If you set this option to y, the Management Engine driver
 +
will defer waiting for the MBP Cleared indicator until the
 +
finalize step.  This can speed up boot time if the ME takes
 +
a long time to indicate this status.
 +
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| OVERRIDE_CLOCK_DISABLE || northbridge/intel/i945 || bool || ||  
+
| FINALIZE_USB_ROUTE_XHCI || southbridge/intel/lynxpoint || bool || Route all ports to XHCI controller in finalize step ||  
Usually system firmware turns off system memory clock
+
If you set this option to y, the USB ports will be routed
signals to unused SO-DIMM slots to reduce EMI and power
+
to the XHCI controller during the finalize SMM callback.
consumption.
+
However, some boards do not like unused clock signals to
+
be disabled.
+
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MAXIMUM_SUPPORTED_FREQUENCY || northbridge/intel/i945 || int ||  ||  
+
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/bd82x6x || bool ||  ||  
If non-zero, this designates the maximum DDR frequency
+
If you set this option to y, the serial IRQ machine will be
the board supports, despite what the chipset should be
+
operated in continuous mode.
capable of.
+
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || Southbridge ||
+
| LOCK_SPI_ON_RESUME_RO || southbridge/intel/bd82x6x || bool || Lock all flash ROM sections on S3 resume ||  
|- bgcolor="#6699dd"
+
If the flash ROM shall be protected against write accesses from the
! align="left" | Menu: AMD Geode GX1 video support || || || ||
+
operating system (OS), the locking procedure has to be repeated after
 +
each resume from S3. Select this if you never want to update the flash
 +
ROM from within your OS. Notice: Even with this option, the write lock
 +
has still to be enabled on the normal boot path (e.g. by the payload).
  
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EXT_CONF_SUPPORT || southbridge/amd/rs690 || bool || ||  
+
| LOCK_SPI_ON_RESUME_NO_ACCESS || southbridge/intel/bd82x6x || bool || Lock and disable reads all flash ROM sections on S3 resume ||  
Select if RS690 should be setup to support MMCONF.
+
If the flash ROM shall be protected against all accesses from the
 +
operating system (OS), the locking procedure has to be repeated after
 +
each resume from S3. Select this if you never want to update the flash
 +
ROM from within your OS. Notice: Even with this option, the lock
 +
has still to be enabled on the normal boot path (e.g. by the payload).
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| USBDEBUG_DEFAULT_PORT || southbridge/amd/sb600 || int || SATA Mode ||  
+
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/fsp_bd82x6x || bool || ||  
Select the mode in which SATA should be driven. IDE or AHCI.
+
If you set this option to y, the serial IRQ machine will be
The default is IDE.
+
operated in continuous mode.
  
config SATA_MODE_IDE
+
||
bool "IDE"
+
|- bgcolor="#eeeeee"
 +
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/fsp_rangeley || bool ||  ||
 +
If you set this option to y, the serial IRQ machine will be
 +
operated in continuous mode.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| IFD_BIN_PATH || southbridge/intel/fsp_rangeley || string ||  ||
 +
The path and filename to the descriptor.bin file.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/fsp_i89xx || bool ||  ||
 +
If you set this option to y, the serial IRQ machine will be
 +
operated in continuous mode.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_XHCI_ENABLE || southbridge/amd/pi/hudson || bool || Enable Hudson XHCI Controller ||
 +
The XHCI controller must be enabled and the XHCI firmware
 +
must be added in order to have USB 3.0 support configured
 +
by coreboot. The OS will be responsible for enabling the XHCI
 +
controller if the the XHCI firmware is available but the
 +
XHCI controller is not enabled by coreboot.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_XHCI_FWM || southbridge/amd/pi/hudson || bool || Add xhci firmware ||
 +
Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_IMC_FWM || southbridge/amd/pi/hudson || bool || Add IMC firmware ||
 +
Add Hudson 2/3/4 IMC Firmware to support the onboard fan control
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_GEC_FWM || southbridge/amd/pi/hudson || bool ||  ||
 +
Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC.
 +
Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_FWM_POSITION || southbridge/amd/pi/hudson || hex || Hudson Firmware ROM Position ||
 +
Hudson requires the firmware MUST be located at
 +
a specific address (ROM start address + 0x20000), otherwise
 +
xhci host Controller can not find or load the xhci firmware.
 +
 
 +
The firmware start address is dependent on the ROM chip size.
 +
The default offset is 0x20000 from the ROM start address, namely
 +
0xFFF20000 if flash chip size is 1M
 +
0xFFE20000 if flash chip size is 2M
 +
0xFFC20000 if flash chip size is 4M
 +
0xFF820000 if flash chip size is 8M
 +
0xFF020000 if flash chip size is 16M
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_SATA_MODE || southbridge/amd/pi/hudson || int || SATA Mode ||
 +
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
 +
The default is NATIVE.
 +
0: NATIVE mode does not require a ROM.
 +
1: RAID mode must have the two ROM files.
 +
2: AHCI may work with or without AHCI ROM. It depends on the payload support.
 +
For example, seabios does not require the AHCI ROM.
 +
3: LEGACY IDE
 +
4: IDE to AHCI
 +
5: AHCI7804: ROM Required, and AMD driver required in the OS.
 +
6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || NATIVE ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || RAID ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || AHCI ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || LEGACY IDE ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || IDE to AHCI ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || AHCI7804 ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || IDE to AHCI7804 ||
 +
|- bgcolor="#eeeeee"
 +
| RAID_ROM_ID || southbridge/amd/pi/hudson || string || RAID device PCI IDs ||
 +
1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RAID_MISC_ROM_POSITION || southbridge/amd/pi/hudson || hex || RAID Misc ROM Position ||
 +
The RAID ROM requires that the MISC ROM is located between the range
 +
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
 +
The CONFIG_ROM_SIZE must be larger than 0x100000.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_LEGACY_FREE || southbridge/amd/pi/hudson || bool || System is legacy free ||
 +
Select y if there is no keyboard controller in the system.
 +
This sets variables in AGESA and ACPI.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AZ_PIN || southbridge/amd/pi/hudson || hex ||  ||
 +
bit 1,0 - pin 0
 +
bit 3,2 - pin 1
 +
bit 5,4 - pin 2
 +
bit 7,6 - pin 3
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_UART || southbridge/amd/pi/hudson || bool || UART controller on Kern ||
 +
There are two UART controllers in Kern.
 +
The UART registers are memory-mapped. UART
 +
controller 0 registers range from FEDC_6000h
 +
to FEDC_6FFFh. UART controller 1 registers
 +
range from FEDC_8000h to FEDC_8FFFh.
 +
 
 +
 
 +
 
 +
||
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SATA_CONTROLLER_MODE || southbridge/amd/cimx/sb700 || hex ||  ||
 +
0x0 = Native IDE mode.
 +
0x1 = RAID mode.
 +
0x2 = AHCI mode.
 +
0x3 = Legacy IDE mode.
 +
0x4 = IDE->AHCI mode.
 +
0x5 = AHCI mode as 7804 ID (AMD driver).
 +
0x6 = IDE->AHCI mode as 7804 ID (AMD driver).
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PCIB_ENABLE || southbridge/amd/cimx/sb700 || bool ||  ||
 +
n = Disable PCI Bridge Device 14 Function 4.
 +
y = Enable PCI Bridge Device 14 Function 4.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ACPI_SCI_IRQ || southbridge/amd/cimx/sb700 || hex ||  ||
 +
Set SCI IRQ to 9.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| REDIRECT_SBCIMX_TRACE_TO_SERIAL || southbridge/amd/cimx/sb700 || bool || Redirect AMD Southbridge CIMX Trace to serial console ||
 +
This Option allows you to redirect the AMD Southbridge CIMX Trace
 +
debug information to the serial console.
 +
 
 +
Warning: Only enable this option when debuging or tracing AMD CIMX code.
  
config SATA_MODE_AHCI
 
bool "AHCI"
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
Line 441: Line 2,345:
 
| IDE_COMBINED_MODE || southbridge/amd/cimx/sb800 || hex || SATA Mode ||  
 
| IDE_COMBINED_MODE || southbridge/amd/cimx/sb800 || hex || SATA Mode ||  
 
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
 
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
The default is NATIVE.
+
The default is AHCI.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| SB800_SATA_IDE || southbridge/amd/cimx/sb800 || bool || NATIVE ||  
 
| SB800_SATA_IDE || southbridge/amd/cimx/sb800 || bool || NATIVE ||  
NATIVE is the default mode and does not require a ROM.
+
NATIVE does not require a ROM.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| SB800_SATA_AHCI || southbridge/amd/cimx/sb800 || bool || AHCI ||  
 
| SB800_SATA_AHCI || southbridge/amd/cimx/sb800 || bool || AHCI ||  
AHCI may work with or without AHCI ROM. It depends on the payload support.
+
AHCI is the default and may work with or without AHCI ROM. It depends on the payload support.
 
For example, seabios does not require the AHCI ROM.
 
For example, seabios does not require the AHCI ROM.
  
Line 470: Line 2,374:
 
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
 
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
 
The CONFIG_ROM_SIZE must larger than 0x100000.
 
The CONFIG_ROM_SIZE must larger than 0x100000.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_IMC_FWM || southbridge/amd/cimx/sb800 || bool || Add IMC firmware ||
 +
Add SB800 / Hudson 1 IMC Firmware to support the onboard fan control.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_FWM_AT_FFFA0000 || southbridge/amd/cimx/sb800 || bool || 0xFFFA0000 ||
 +
The IMC and GEC ROMs requires a 'signature' located at one of several
 +
fixed locations in memory.  The location used shouldn't matter, just
 +
select an area that doesn't conflict with anything else.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_FWM_AT_FFF20000 || southbridge/amd/cimx/sb800 || bool || 0xFFF20000 ||
 +
The IMC and GEC ROMs requires a 'signature' located at one of several
 +
fixed locations in memory.  The location used shouldn't matter, just
 +
select an area that doesn't conflict with anything else.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_FWM_AT_FFE20000 || southbridge/amd/cimx/sb800 || bool || 0xFFE20000 ||
 +
The IMC and GEC ROMs requires a 'signature' located at one of several
 +
fixed locations in memory.  The location used shouldn't matter, just
 +
select an area that doesn't conflict with anything else.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_FWM_AT_FFC20000 || southbridge/amd/cimx/sb800 || bool || 0xFFC20000 ||
 +
The IMC and GEC ROMs requires a 'signature' located at one of several
 +
fixed locations in memory.  The location used shouldn't matter, just
 +
select an area that doesn't conflict with anything else.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_FWM_AT_FF820000 || southbridge/amd/cimx/sb800 || bool || 0xFF820000 ||
 +
The IMC and GEC ROMs requires a 'signature' located at one of several
 +
fixed locations in memory.  The location used shouldn't matter, just
 +
select an area that doesn't conflict with anything else.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EHCI_BAR || southbridge/amd/cimx/sb800 || hex || Fan Control ||
 +
Select the method of SB800 fan control to be used.  None would be
 +
for either fixed maximum speed fans connected to the SB800 or for
 +
an external chip controlling the fan speeds.  Manual control sets
 +
up the SB800 fan control registers.  IMC fan control uses the SB800
 +
IMC to actively control the fan speeds.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_NO_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || None ||
 +
No SB800 Fan control - Do not set up the SB800 fan control registers.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_MANUAL_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || Manual ||
 +
Configure the SB800 fan control registers in devicetree.cb.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_IMC_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || IMC Based ||
 +
Set up the SB800 to use the IMC based Fan controller.  This requires
 +
the IMC rom from AMD.  Configure the registers in devicetree.cb.
  
 
||
 
||
Line 495: Line 2,464:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HAVE_CMC || southbridge/intel/sch || bool || Add a CMC state machine binary ||  
+
| EXT_CONF_SUPPORT || southbridge/amd/sr5650 || bool || Enable PCI-E MMCONFIG support ||  
Select this option to add a CMC state machine binary to
+
Select to enable PCI-E MMCONFIG support on the SR5650.
the resulting coreboot image.
+
  
Note: Without this binary coreboot will not work
+
||
 +
|- bgcolor="#eeeeee"
 +
| EXT_CONF_SUPPORT || southbridge/amd/rs690 || bool ||  ||
 +
Select if RS690 should be setup to support MMCONF.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CMC_FILE || southbridge/intel/sch || string || Intel CMC path and filename ||  
+
| HUDSON_XHCI_ENABLE || southbridge/amd/agesa/hudson || bool || Enable Hudson XHCI Controller ||  
The path and filename of the file to use as CMC state machine
+
The XHCI controller must be enabled and the XHCI firmware
binary.
+
must be added in order to have USB 3.0 support configured
 +
by coreboot. The OS will be responsible for enabling the XHCI
 +
controller if the the XHCI firmware is available but the
 +
XHCI controller is not enabled by coreboot.
  
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_XHCI_FWM || southbridge/amd/agesa/hudson || bool || Add xhci firmware ||
 +
Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_IMC_FWM || southbridge/amd/agesa/hudson || bool || Add imc firmware ||
 +
Add Hudson 2/3/4 IMC Firmware to support the onboard fan control
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_GEC_FWM || southbridge/amd/agesa/hudson || bool ||  ||
 +
Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC.
 +
Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_FWM_POSITION || southbridge/amd/agesa/hudson || hex || Hudson Firmware ROM Position ||
 +
Hudson requires the firmware MUST be located at
 +
a specific address (ROM start address + 0x20000), otherwise
 +
xhci host Controller can not find or load the xhci firmware.
 +
 +
The firmware start address is dependent on the ROM chip size.
 +
The default offset is 0x20000 from the ROM start address, namely
 +
0xFFF20000 if flash chip size is 1M
 +
0xFFE20000 if flash chip size is 2M
 +
0xFFC20000 if flash chip size is 4M
 +
0xFF820000 if flash chip size is 8M
 +
0xFF020000 if flash chip size is 16M
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_SATA_MODE || southbridge/amd/agesa/hudson || int || SATA Mode ||
 +
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
 +
The default is NATIVE.
 +
0: NATIVE mode does not require a ROM.
 +
1: RAID mode must have the two ROM files.
 +
2: AHCI may work with or without AHCI ROM. It depends on the payload support.
 +
For example, seabios does not require the AHCI ROM.
 +
3: LEGACY IDE
 +
4: IDE to AHCI
 +
5: AHCI7804: ROM Required, and AMD driver required in the OS.
 +
6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || NATIVE ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || RAID ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || AHCI ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || LEGACY IDE ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || IDE to AHCI ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || AHCI7804 ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || IDE to AHCI7804 ||
 +
|- bgcolor="#eeeeee"
 +
| RAID_ROM_ID || southbridge/amd/agesa/hudson || string || RAID device PCI IDs ||
 +
1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RAID_MISC_ROM_POSITION || southbridge/amd/agesa/hudson || hex || RAID Misc ROM Position ||
 +
The RAID ROM requires that the MISC ROM is located between the range
 +
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
 +
The CONFIG_ROM_SIZE must be larger than 0x100000.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_LEGACY_FREE || southbridge/amd/agesa/hudson || bool || System is legacy free ||
 +
Select y if there is no keyboard controller in the system.
 +
This sets variables in AGESA and ACPI.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AZ_PIN || southbridge/amd/agesa/hudson || hex ||  ||
 +
bit 1,0 - pin 0
 +
bit 3,2 - pin 1
 +
bit 5,4 - pin 2
 +
bit 7,6 - pin 3
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EHCI_BAR || southbridge/amd/sb600 || hex || SATA Mode ||
 +
Select the mode in which SATA should be driven. IDE or AHCI.
 +
The default is IDE.
 +
 +
config SATA_MODE_IDE
 +
bool "IDE"
 +
 +
config SATA_MODE_AHCI
 +
bool "AHCI"
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| || || (comment) || || Super I/O ||
 
| || || (comment) || || Super I/O ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || Devices ||
+
| || || (comment) || || Embedded Controllers ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VGA_BRIDGE_SETUP || devices || bool || Setup bridges on path to VGA adapter ||  
+
| EC_ACPI || ec/acpi || bool || ||  
Allow bridges to set up legacy decoding ranges for VGA. Don't disable
+
ACPI Embedded Controller interface. Mostly found in laptops.
this unless you're sure you don't want the briges setup for VGA.
+
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VGA_ROM_RUN || devices || bool || Run VGA option ROMs ||  
+
| EC_GOOGLE_CHROMEEC || ec/google/chromeec || bool || ||  
Execute VGA option ROMs, if found. This is required to enable
+
Google's Chrome EC
PCI/AGP/PCI-E video cards.
+
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PCI_ROM_RUN || devices || bool || Run non-VGA option ROMs ||  
+
| EC_GOOGLE_CHROMEEC_ACPI_MEMMAP || ec/google/chromeec || bool || ||
Execute non-VGA PCI option ROMs, if found.
+
When defined, ACPI accesses EC memmap data on ports 66h/62h. When
 +
not defined, the memmap data is instead accessed on 900h-9ffh via
 +
the LPC bus.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_I2C || ec/google/chromeec || bool ||  ||
 +
Google's Chrome EC via I2C bus.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_I2C_PROTO3 || ec/google/chromeec || bool ||  ||
 +
Use only proto3 for i2c EC communication.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_LPC || ec/google/chromeec || bool ||  ||
 +
Google Chrome EC via LPC bus.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_MEC || ec/google/chromeec || bool ||  ||
 +
Microchip EC variant for LPC register access.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_PD || ec/google/chromeec || bool ||  ||
 +
Indicates that Google's Chrome USB PD chip is present.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_SPI || ec/google/chromeec || bool ||  ||
 +
Google's Chrome EC via SPI bus.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US || ec/google/chromeec || int ||  ||
 +
Force delay after asserting /CS to allow EC to wakeup.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_EXTERNAL_FIRMWARE || ec/google/chromeec || hex ||  ||
 +
Disable building EC firmware if it's already built externally (and
 +
added manually.)
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_BOARDNAME || ec/google/chromeec || string || Chrome EC board name for EC ||
 +
The board name used in the Chrome EC code base to build
 +
the EC firmware.  If set, the coreboot build with also
 +
build the EC firmware and add it to the image.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_PD_BOARDNAME || ec/google/chromeec || string || Chrome EC board name for PD ||
 +
The board name used in the Chrome EC code base to build
 +
the PD firmware.  If set, the coreboot build with also
 +
build the EC firmware and add it to the image.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_RTC || ec/google/chromeec || bool || Enable Chrome OS EC RTC ||
 +
Enable support for the real-time clock on the Chrome OS EC. This
 +
uses the EC_CMD_RTC_GET_VALUE command to read the current time.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_QUANTA_IT8518 || ec/quanta/it8518 || bool ||  ||
 +
Interface to QUANTA IT8518 Embedded Controller.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_QUANTA_ENE_KB3940Q || ec/quanta/ene_kb3940q || bool ||  ||
 +
Interface to QUANTA ENE KB3940Q Embedded Controller.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_SMSC_MEC1308 || ec/smsc/mec1308 || bool ||  ||
 +
Shared memory mailbox interface to SMSC MEC1308 Embedded Controller.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_PURISM_LIBREM || ec/purism/librem || bool ||  ||
 +
Purism Librem EC
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_COMPAL_ENE932 || ec/compal/ene932 || bool ||  ||
 +
Interface to COMPAL ENE932 Embedded Controller.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_KONTRON_IT8516E || ec/kontron/it8516e || bool ||  ||
 +
Kontron uses an ITE IT8516E on the KTQM77. Its firmware might
 +
come from Fintek (mentioned as Finte*c* somewhere in their Linux
 +
driver).
 +
The KTQM77 is an embedded board and the IT8516E seems to be
 +
only used for fan control and GPIO.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Intel FSP ||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_FSP_BIN || drivers/intel/fsp1_0 || bool || Use Intel Firmware Support Package ||
 +
Select this option to add an Intel FSP binary to
 +
the resulting coreboot image.
 +
 
 +
Note: Without this binary, coreboot builds relying on the FSP
 +
will not boot
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_FILE || drivers/intel/fsp1_0 || string || Intel FSP binary path and filename ||
 +
The path and filename of the Intel FSP binary for this platform.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_LOC || drivers/intel/fsp1_0 || hex || Intel FSP Binary location in CBFS ||
 +
The location in CBFS that the FSP is located. This must match the
 +
value that is set in the FSP binary.  If the FSP needs to be moved,
 +
rebase the FSP with Intel's BCT (tool).
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_FSP_FAST_BOOT || drivers/intel/fsp1_0 || bool || Enable Fast Boot ||
 +
Enabling this feature will force the MRC data to be cached in NV
 +
storage to be used for speeding up boot time on future reboots
 +
and/or power cycles.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_MRC_CACHE || drivers/intel/fsp1_0 || bool ||  ||
 +
Enabling this feature will cause MRC data to be cached in NV storage.
 +
This can either be used for fast boot, or just because the FSP wants
 +
it to be saved.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MRC_CACHE_FMAP || drivers/intel/fsp1_0 || bool || Use MRC Cache in FMAP ||
 +
Use the region "RW_MRC_CACHE" in FMAP instead of "mrc.cache" in CBFS.
 +
You must define a region in your FMAP named "RW_MRC_CACHE".
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MRC_CACHE_SIZE || drivers/intel/fsp1_0 || hex || Fast Boot Data Cache Size ||
 +
This is the amount of space in NV storage that is reserved for the
 +
fast boot data cache storage.
 +
 
 +
WARNING: Because this area will be erased and re-written, the size
 +
should be a full sector of the flash ROM chip and nothing else should
 +
be included in CBFS in any sector that the fast boot cache data is in.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VIRTUAL_ROM_SIZE || drivers/intel/fsp1_0 || hex || Virtual ROM Size ||
 +
This is used to calculate the offset of the MRC data cache in NV
 +
Storage for fast boot.  If in doubt, leave this set to the default
 +
which sets the virtual size equal to the ROM size.
 +
 
 +
Example: Cougar Canyon 2 has two 8 MB SPI ROMs.  When the SPI ROMs are
 +
loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB.  When
 +
the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM
 +
size is 16 MB.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CACHE_ROM_SIZE_OVERRIDE || drivers/intel/fsp1_0 || hex || Cache ROM Size ||
 +
This is the size of the cachable area that is passed into the FSP in
 +
the early initialization.  Typically this should be the size of the CBFS
 +
area, but the size must be a power of 2 whereas the CBFS size does not
 +
have this limitation.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USE_GENERIC_FSP_CAR_INC || drivers/intel/fsp1_0 || bool ||  ||
 +
The chipset can select this to use a generic cache_as_ram.inc file
 +
that should be good for all FSP based platforms.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_USES_UPD || drivers/intel/fsp1_0 || bool ||  ||
 +
If this FSP uses UPD/VPD data regions, select this in the chipset Kconfig.
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_INTEL_FIRMWARE || southbridge/intel/common/firmware || bool ||  ||
 +
Chipset uses the Intel Firmware Descriptor to describe the
 +
layout of the SPI ROM chip.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Intel Firmware ||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_IFD_BIN || southbridge/intel/common/firmware || bool || Add Intel descriptor.bin file ||
 +
The descriptor binary
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EM100 || southbridge/intel/common/firmware || bool || Configure IFD for EM100 usage ||
 +
Set SPI frequency to 20MHz and disable Dual Output Fast Read Support
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_ME_BIN || southbridge/intel/common/firmware || bool || Add Intel ME/TXE firmware ||
 +
The Intel processor in the selected system requires a special firmware
 +
for an integrated controller.  This might be called the Management
 +
Engine (ME), the Trusted Execution Engine (TXE) or something else
 +
depending on the chip. This firmware might or might not be available
 +
in coreboot's 3rdparty/blobs repository. If it is not and if you don't
 +
have access to the firmware from elsewhere, you can still build
 +
coreboot without it. In this case however, you'll have to make sure
 +
that you don't overwrite your ME/TXE firmware on your flash ROM.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_GBE_BIN || southbridge/intel/common/firmware || bool || Add gigabit ethernet firmware ||
 +
The integrated gigabit ethernet controller needs a firmware file.
 +
Select this if you are going to use the PCH integrated controller
 +
and have the firmware.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BUILD_WITH_FAKE_IFD || southbridge/intel/common/firmware || bool || Build with a fake IFD ||
 +
If you don't have an Intel Firmware Descriptor (descriptor.bin) for your
 +
board, you can select this option and coreboot will build without it.
 +
The resulting coreboot.rom will not contain all parts required
 +
to get coreboot running on your board. You can however write only the
 +
BIOS section to your board's flash ROM and keep the other sections
 +
untouched. Unfortunately the current version of flashrom doesn't
 +
support this yet. But there is a patch pending [1].
 +
 
 +
WARNING: Never write a complete coreboot.rom to your flash ROM if it
 +
was built with a fake IFD. It just won't work.
 +
 
 +
[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| IFD_BIOS_SECTION || southbridge/intel/common/firmware || string || BIOS Region Starting:Ending addresses within the ROM ||
 +
The BIOS region is typically the size of the CBFS area, and is located
 +
at the end of the ROM space.
 +
 
 +
For an 8MB ROM with a 3MB CBFS area, this would look like:
 +
0x00500000:0x007fffff
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| IFD_ME_SECTION || southbridge/intel/common/firmware || string || ME/TXE Region Starting:Ending addresses within the ROM ||
 +
The ME/TXE region typically starts at around 0x1000 and often fills the
 +
ROM space not used by CBFS.
 +
 
 +
For an 8MB ROM with a 3MB CBFS area, this might look like:
 +
0x00001000:0x004fffff
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| IFD_GBE_SECTION || southbridge/intel/common/firmware || string || GBE Region Starting:Ending addresses within the ROM ||
 +
The Gigabit Ethernet ROM region is used when an Intel NIC is built into
 +
the Southbridge/SOC and the platform uses this device instead of an external
 +
PCIe NIC.  It will be located between the ME/TXE and the BIOS region.
 +
 
 +
Leave this empty if you're unsure.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| IFD_PLATFORM_SECTION || southbridge/intel/common/firmware || string || Platform Region Starting:Ending addresses within the Rom ||
 +
The Platform region is used for platform specific data.
 +
It will be located between the ME/TXE and the BIOS region.
 +
 
 +
Leave this empty if you're unsure.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| LOCK_MANAGEMENT_ENGINE || southbridge/intel/common/firmware || bool || Lock ME/TXE section ||
 +
The Intel Firmware Descriptor supports preventing write accesses
 +
from the host to the ME or TXE section in the firmware
 +
descriptor. If the section is locked, it can only be overwritten
 +
with an external SPI flash programmer. You will want this if you
 +
want to increase security of your ROM image once you are sure
 +
that the ME/TXE firmware is no longer going to change.
 +
 
 +
If unsure, say N.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CBFS_SIZE || southbridge/intel/common/firmware || hex ||  ||
 +
Reduce CBFS size to give room to the IFD blobs.
 +
 
 +
||
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: AMD Platform Initialization || || || ||
 +
|- bgcolor="#eeeeee"
 +
| None || vendorcode/amd || None || AGESA source ||
 +
Select the method for including the AMD Platform Initialization
 +
code into coreboot.  Platform Initialization code is required for
 +
all AMD processors.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_AMD_AGESA_BINARY_PI || vendorcode/amd || bool || binary PI ||
 +
Use a binary PI package.  Generally, these will be stored in the
 +
"3rdparty/blobs" directory.  For some processors, these must be obtained
 +
directly from AMD Embedded Processors Group
 +
(http://www.amdcom/embedded).
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_AMD_AGESA_OPENSOURCE || vendorcode/amd || bool || open-source AGESA ||
 +
Build the PI package ("AGESA") from source code in the "vendorcode"
 +
directory.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AGESA_BINARY_PI_VENDORCODE_PATH || vendorcode/amd/pi || string || AGESA PI directory path ||
 +
Specify where to find the AGESA header files
 +
for AMD platform initialization.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AGESA_BINARY_PI_FILE || vendorcode/amd/pi || string || AGESA PI binary file name ||
 +
Specify the binary file to use for AMD platform initialization.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AGESA_BINARY_PI_LOCATION || vendorcode/amd/pi || string || AGESA PI binary address in ROM ||
 +
Specify the ROM address at which to store the binary Platform
 +
Initialization code.
 +
 
 +
||
 +
 
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: ChromeOS || || || ||
 +
|- bgcolor="#eeeeee"
 +
| CHROMEOS || vendorcode/google/chromeos || bool || Build for ChromeOS ||
 +
Enable ChromeOS specific features like the GPIO sub table in
 +
the coreboot table. NOTE: Enabling this option on an unsupported
 +
board will most likely break your build.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VBNV_OFFSET || vendorcode/google/chromeos || hex ||  ||
 +
CMOS offset for VbNv data. This value must match cmos.layout
 +
in the mainboard directory, minus 14 bytes for the RTC.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CHROMEOS_VBNV_CMOS || vendorcode/google/chromeos || bool || Vboot non-volatile storage in CMOS. ||
 +
VBNV is stored in CMOS
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH || vendorcode/google/chromeos || bool || Back up Vboot non-volatile storage from CMOS to flash. ||
 +
Vboot non-volatile storage data will be backed up from CMOS to flash
 +
and restored from flash if the CMOS is invalid due to power loss.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CHROMEOS_VBNV_EC || vendorcode/google/chromeos || bool || Vboot non-volatile storage in EC. ||
 +
VBNV is stored in EC
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CHROMEOS_VBNV_FLASH || vendorcode/google/chromeos || bool ||  ||
 +
VBNV is stored in flash storage
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_SOFTWARE_SYNC || vendorcode/google/chromeos || bool || Enable EC software sync ||
 +
EC software sync is a mechanism where the AP helps the EC verify its
 +
firmware similar to how vboot verifies the main system firmware. This
 +
option selects whether depthcharge should support EC software sync.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VBOOT_EC_SLOW_UPDATE || vendorcode/google/chromeos || bool || EC is slow to update ||
 +
Whether the EC (or PD) is slow to update and needs to display a
 +
screen that informs the user the update is happening.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VBOOT_OPROM_MATTERS || vendorcode/google/chromeos || bool || Video option ROM matters (= can skip display init) ||
 +
Set this option to indicate to vboot that this platform will skip its
 +
display initialization on a normal (non-recovery, non-developer) boot.
 +
Vboot calls this "oprom matters" because on x86 devices this
 +
traditionally meant that the video option ROM will not be loaded, but
 +
it works functionally the same for other platforms that can skip their
 +
native display initialization code instead.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VIRTUAL_DEV_SWITCH || vendorcode/google/chromeos || bool || Virtual developer switch support ||
 +
Whether this platform has a virtual developer switch.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VBOOT_VERIFY_FIRMWARE || vendorcode/google/chromeos || bool || Verify firmware with vboot. ||
 +
Enabling VBOOT_VERIFY_FIRMWARE will use vboot to verify the components
 +
of the firmware (stages, payload, etc).
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NO_TPM_RESUME || vendorcode/google/chromeos || bool ||  ||
 +
On some boards the TPM stays powered up in S3. On those
 +
boards, booting Windows will break if the TPM resume command
 +
is sent during an S3 resume.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PHYSICAL_REC_SWITCH || vendorcode/google/chromeos || bool || Physical recovery switch is present ||
 +
Whether this platform has a physical recovery switch
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| LID_SWITCH || vendorcode/google/chromeos || bool || Lid switch is present ||
 +
Whether this platform has a lid switch
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| WIPEOUT_SUPPORTED || vendorcode/google/chromeos || bool || User is able to request factory reset ||
 +
When this option is enabled, the firmware provides the ability to
 +
signal the application the need for factory reset (a.k.a. wipe
 +
out) of the device
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_REGULATORY_DOMAIN || vendorcode/google/chromeos || bool || Add regulatory domain methods ||
 +
This option is needed to add ACPI regulatory domain methods
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VBOOT_STARTS_IN_BOOTBLOCK || vendorcode/google/chromeos/vboot2 || bool || Vboot starts verifying in bootblock ||
 +
Firmware verification happens during or at the end of bootblock.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VBOOT_STARTS_IN_ROMSTAGE || vendorcode/google/chromeos/vboot2 || bool || Vboot starts verifying in romstage ||
 +
Firmware verification happens during or at the end of romstage.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VBOOT2_MOCK_SECDATA || vendorcode/google/chromeos/vboot2 || bool || Mock secdata for firmware verification ||
 +
Enabling VBOOT2_MOCK_SECDATA will mock secdata for the firmware
 +
verification to avoid access to a secdata storage (typically TPM).
 +
All operations for a secdata storage will be successful. This option
 +
can be used during development when a TPM is not present or broken.
 +
THIS SHOULD NOT BE LEFT ON FOR PRODUCTION DEVICES.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VBOOT_DISABLE_DEV_ON_RECOVERY || vendorcode/google/chromeos/vboot2 || bool || Disable dev mode on recovery requests ||
 +
When this option is enabled, the Chrome OS device leaves the
 +
developer mode as soon as recovery request is detected. This is
 +
handy on embedded devices with limited input capabilities.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RETURN_FROM_VERSTAGE || vendorcode/google/chromeos/vboot2 || bool || The separate verification stage returns to its caller ||
 +
If this is set, the verstage returns back to the calling stage instead
 +
of exiting to the succeeding stage so that the verstage space can be
 +
reused by the succeeding stage. This is useful if a ram space is too
 +
small to fit both the verstage and the succeeding stage.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CHIPSET_PROVIDES_VERSTAGE_MAIN_SYMBOL || vendorcode/google/chromeos/vboot2 || bool || The chipset provides the main() entry point for verstage ||
 +
The chipset code provides their own main() entry point.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VBOOT_DYNAMIC_WORK_BUFFER || vendorcode/google/chromeos/vboot2 || bool || Vboot's work buffer is dynamically allocated. ||
 +
This option is used when there isn't enough pre-main memory
 +
ram to allocate the vboot work buffer. That means vboot verification
 +
is after memory init and requires main memory to back the work
 +
buffer.
 +
 
 +
||
 +
 
 +
||
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: GBB configuration || || || ||
 +
 
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: Vboot Keys || || || ||
 +
 
 +
 
 +
|- bgcolor="#eeeeee"
 +
| ARM64_SECURE_OS_FILE || arch/arm64 || string || Secure OS binary file ||
 +
Secure OS binary file.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ARM64_A53_ERRATUM_843419 || arch/arm64 || bool ||  ||
 +
Some early Cortex-A53 revisions had a hardware bug that results in
 +
incorrect address calculations in rare cases. This option enables a
 +
linker workaround to avoid those cases if your toolchain supports it.
 +
Should be selected automatically by SoCs that are affected.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USE_MARCH_586 || arch/x86 || bool ||  ||
 +
Allow a platform or processor to select to be compiled using
 +
the '-march=i586' option instead of the typical '-march=i686'
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| LATE_CBMEM_INIT || arch/x86 || bool ||  ||
 +
Enable this in chipset's Kconfig if northbridge does not implement
 +
early get_top_of_ram() call for romstage. CBMEM tables will be
 +
allocated late in ramstage, after PCI devices resources are known.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOTBLOCK_DEBUG_SPINLOOP || arch/x86 || bool ||  ||
 +
Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait
 +
for a JTAG debugger to break into the execution sequence.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP || arch/x86 || bool ||  ||
 +
Select this value to provide a routine to save the BIST and timestamp
 +
values.  The default code places the BIST value in MM0 and the
 +
timestamp value in MM2:MM1.  Another file is necessary when the CPU
 +
does not support the MMx register set.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VERSTAGE_DEBUG_SPINLOOP || arch/x86 || bool ||  ||
 +
Add a spin (JMP .) in assembly_entry.S during early verstage to wait
 +
for a JTAG debugger to break into the execution sequence.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ROMSTAGE_DEBUG_SPINLOOP || arch/x86 || bool ||  ||
 +
Add a spin (JMP .) in assembly_entry.S during early romstage to wait
 +
for a JTAG debugger to break into the execution sequence.
 +
 
 +
||
 +
 
 +
||
 +
 
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: Devices || || || ||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_DO_NATIVE_VGA_INIT || device || bool || Use native graphics initialization ||
 +
Some mainboards, such as the Google Link, allow initializing the display
 +
without the need of a binary only VGA OPROM. Enabling this option may be
 +
faster, but also lacks flexibility in setting modes.
 +
 
 +
If unsure, say N.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_ROM_RUN || device || bool || Run VGA Option ROMs ||  
 +
Execute VGA Option ROMs in coreboot if found. This is required
 +
to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS
 +
payload.
 +
 
 +
When using a SeaBIOS payload it runs all option ROMs with much
 +
more complete BIOS interrupt services available than coreboot,
 +
which some option ROMs require in order to function correctly.
 +
 
 +
If unsure, say N when using SeaBIOS as payload, Y otherwise.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| S3_VGA_ROM_RUN || device || bool || Re-run VGA Option ROMs on S3 resume ||
 +
Execute VGA Option ROMs in coreboot when resuming from S3 suspend.
 +
 
 +
When using a SeaBIOS payload it runs all option ROMs with much
 +
more complete BIOS interrupt services available than coreboot,
 +
which some option ROMs require in order to function correctly.
 +
 
 +
If unsure, say N when using SeaBIOS as payload, Y otherwise.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ALWAYS_LOAD_OPROM || device || bool ||  ||
 +
Always load option ROMs if any are found. The decision to run
 +
the ROM is still determined at runtime, but the distinction
 +
between loading and not running comes into play for CHROMEOS.
 +
 
 +
An example where this is required is that VBT (Video BIOS Tables)
 +
are needed for the kernel's display driver to know how a piece of
 +
hardware is configured to be used.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ON_DEVICE_ROM_LOAD || device || bool || Load Option ROMs on PCI devices ||
 +
Load Option ROMs stored on PCI/PCIe/AGP devices in coreboot.
 +
 
 +
If disabled, only Option ROMs stored in CBFS will be executed by
 +
coreboot. If you are concerned about security, you might want to
 +
disable this option, but it might leave your system in a state of
 +
degraded functionality.
 +
 
 +
When using a SeaBIOS payload it runs all option ROMs with much
 +
more complete BIOS interrupt services available than coreboot,
 +
which some option ROMs require in order to function correctly.
  
Examples include IDE/SATA controller option ROMs and option ROMs
+
If unsure, say N when using SeaBIOS as payload, Y otherwise.
for network cards (NICs).
+
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PCI_OPTION_ROM_RUN_REALMODE || devices || bool || Native mode ||  
+
| PCI_OPTION_ROM_RUN_REALMODE || device || bool || Native mode ||  
If you select this option, PCI option ROMs will be executed
+
If you select this option, PCI Option ROMs will be executed
 
natively on the CPU in real mode. No CPU emulation is involved,
 
natively on the CPU in real mode. No CPU emulation is involved,
 
so this is the fastest, but also the least secure option.
 
so this is the fastest, but also the least secure option.
Line 541: Line 3,211:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PCI_OPTION_ROM_RUN_YABEL || devices || bool || Secure mode ||  
+
| PCI_OPTION_ROM_RUN_YABEL || device || bool || Secure mode ||  
 
If you select this option, the x86emu CPU emulator will be used to
 
If you select this option, the x86emu CPU emulator will be used to
execute PCI option ROMs.
+
execute PCI Option ROMs.
  
This option prevents option ROMs from doing dirty tricks with the
+
This option prevents Option ROMs from doing dirty tricks with the
 
system (such as installing SMM modules or hypervisors), but it is
 
system (such as installing SMM modules or hypervisors), but it is
also significantly slower than the native option ROM initialization
+
also significantly slower than the native Option ROM initialization
 
method.
 
method.
  
Line 554: Line 3,224:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| YABEL_PCI_ACCESS_OTHER_DEVICES || devices || bool || Allow option ROMs to access other devices ||  
+
| YABEL_PCI_ACCESS_OTHER_DEVICES || device || bool || Allow Option ROMs to access other devices ||  
Per default, YABEL only allows option ROMs to access the PCI device
+
Per default, YABEL only allows Option ROMs to access the PCI device
 
that they are associated with. However, this causes trouble for some
 
that they are associated with. However, this causes trouble for some
onboard graphics chips whose option ROM needs to reconfigure the
+
onboard graphics chips whose Option ROM needs to reconfigure the
 
north bridge.
 
north bridge.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| YABEL_VIRTMEM_LOCATION || devices || hex || Location of YABEL's virtual memory ||  
+
| YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG || device || bool || Fake success on writing other device's config space ||
 +
By default, YABEL aborts when the Option ROM tries to write to other
 +
devices' config spaces. With this option enabled, the write doesn't
 +
follow through, but the Option ROM is allowed to go on.
 +
This can create issues such as hanging Option ROMs (if it depends on
 +
that other register changing to the written value), so test for
 +
impact before using this option.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| YABEL_VIRTMEM_LOCATION || device || hex || Location of YABEL's virtual memory ||  
 
YABEL requires 1MB memory for its CPU emulation. This memory is
 
YABEL requires 1MB memory for its CPU emulation. This memory is
 
normally located at 16MB.
 
normally located at 16MB.
Line 568: Line 3,248:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| YABEL_DIRECTHW || devices || bool || Direct hardware access ||  
+
| YABEL_DIRECTHW || device || bool || Direct hardware access ||  
 
YABEL consists of two parts: It uses x86emu for the CPU emulation and
 
YABEL consists of two parts: It uses x86emu for the CPU emulation and
 
additionally provides a PC system emulation that filters bad device
 
additionally provides a PC system emulation that filters bad device
Line 576: Line 3,256:
 
When choosing this option, x86emu will pass through all hardware
 
When choosing this option, x86emu will pass through all hardware
 
accesses to memory and I/O devices to the underlying memory and I/O
 
accesses to memory and I/O devices to the underlying memory and I/O
addresses. While this option prevents option ROMs from doing dirty
+
addresses. While this option prevents Option ROMs from doing dirty
 
tricks with the CPU (such as installing SMM modules or hypervisors),
 
tricks with the CPU (such as installing SMM modules or hypervisors),
 
they can still access all devices in the system.
 
they can still access all devices in the system.
Line 583: Line 3,263:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || Embedded Controllers ||
+
| PCIEXP_COMMON_CLOCK || device || bool || Enable PCIe Common Clock ||  
 +
Detect and enable Common Clock on PCIe links.
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EC_ACPI || ec/acpi || bool || ||  
+
| PCIEXP_ASPM || device || bool || Enable PCIe ASPM ||  
ACPI Embedded Controller interface. Mostly found in laptops.
+
Detect and enable ASPM on PCIe links.
  
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| PCIEXP_CLK_PM || device || bool || Enable PCIe Clock Power Management ||
 +
Detect and enable Clock Power Management on PCIe.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EARLY_PCI_BRIDGE || device || bool || Early PCI bridge ||
 +
While coreboot is executing code from ROM, the coreboot resource
 +
allocator has not been running yet. Hence PCI devices living behind
 +
a bridge are not yet visible to the system.
 +
 +
This option enables static configuration for a single pre-defined
 +
PCI bridge function on bus 0.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PCIEXP_L1_SUB_STATE || device || bool || Enable PCIe ASPM L1 SubState ||
 +
Detect and enable ASPM on PCIe links.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SUBSYSTEM_VENDOR_ID || device || hex || Override PCI Subsystem Vendor ID ||
 +
This config option will override the devicetree settings for
 +
PCI Subsystem Vendor ID.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SUBSYSTEM_DEVICE_ID || device || hex || Override PCI Subsystem Device ID ||
 +
This config option will override the devicetree settings for
 +
PCI Subsystem Device ID.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS || device || bool || Add a VGA BIOS image ||
 +
Select this option if you have a VGA BIOS image that you would
 +
like to add to your ROM.
 +
 +
You will be able to specify the location and file name of the
 +
image later.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_FILE || device || string || VGA BIOS path and filename ||
 +
The path and filename of the file to use as VGA BIOS.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_ID || device || string || VGA device PCI IDs ||
 +
The comma-separated PCI vendor and device ID that would associate
 +
your VGA BIOS to your video card.
 +
 +
Example: 1106,3230
 +
 +
In the above example 1106 is the PCI vendor ID (in hex, but without
 +
the "0x" prefix) and 3230 specifies the PCI device ID of the
 +
video card (also in hex, without "0x" prefix).
 +
 +
Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| INTEL_MBI || device || bool || Add an MBI image ||
 +
Select this option if you have an Intel MBI image that you would
 +
like to add to your ROM.
 +
 +
You will be able to specify the location and file name of the
 +
image later.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MBI_FILE || device || string || Intel MBI path and filename ||
 +
The path and filename of the file to use as VGA BIOS.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOFTWARE_I2C || device || bool || Enable I2C controller emulation in software ||
 +
This config option will enable code to override the i2c_transfer
 +
routine with a (simple) software emulation of the protocol. This may
 +
be useful for debugging or on platforms where a driver for the real
 +
I2C controller is not (yet) available. The platform code needs to
 +
provide bindings to manually toggle I2C lines.
 +
 +
||
 +
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: Display || || || ||
 +
|- bgcolor="#eeeeee"
 +
| FRAMEBUFFER_SET_VESA_MODE || device || bool || Set framebuffer graphics resolution ||
 +
Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console)
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FRAMEBUFFER_SET_VESA_MODE || device || bool || framebuffer graphics resolution ||
 +
This option sets the resolution used for the coreboot framebuffer (and
 +
bootsplash screen).
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FRAMEBUFFER_KEEP_VESA_MODE || device || bool || Keep VESA framebuffer ||
 +
This option keeps the framebuffer mode set after coreboot finishes
 +
execution. If this option is enabled, coreboot will pass a
 +
framebuffer entry in its coreboot table and the payload will need a
 +
framebuffer driver. If this option is disabled, coreboot will switch
 +
back to text mode before handing control to a payload.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOTSPLASH || device || bool || Show graphical bootsplash ||
 +
This option shows a graphical bootsplash screen. The graphics are
 +
loaded from the CBFS file bootsplash.jpg.
 +
 +
You can either specify the location and file name of the
 +
image in the 'General' section or add it manually to CBFS, using,
 +
for example, cbfstool.
 +
 
||
 
||
  
Line 594: Line 3,392:
 
! align="left" | Menu: Generic Drivers || || || ||
 
! align="left" | Menu: Generic Drivers || || || ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DRIVERS_OXFORD_OXPCIE || drivers/oxford/oxpcie || bool || Oxford OXPCIe952 ||  
+
| ELOG || drivers/elog || bool || Support for flash based event log ||
 +
Enable support for flash based event logging.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ELOG_CBMEM || drivers/elog || bool || Store a copy of ELOG in CBMEM ||
 +
This option will have ELOG store a copy of the flash event log
 +
in a CBMEM region and export that address in SMBIOS to the OS.
 +
This is useful if the ELOG location is not in memory mapped flash,
 +
but it means that events added at runtime via the SMI handler
 +
will not be reflected in the CBMEM copy of the log.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ELOG_GSMI || drivers/elog || bool || SMI interface to write and clear event log ||
 +
This interface is compatible with the linux kernel driver
 +
available with CONFIG_GOOGLE_GSMI and can be used to write
 +
kernel reset/shutdown messages to the event log.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ELOG_BOOT_COUNT || drivers/elog || bool || Maintain a monotonic boot number in CMOS ||
 +
Store a monotonic boot number in CMOS and provide an interface
 +
to read the current value and increment the counter.  This boot
 +
counter will be logged as part of the System Boot event.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ELOG_BOOT_COUNT_CMOS_OFFSET || drivers/elog || int || Offset in CMOS to store the boot count ||
 +
This value must be greater than 16 bytes so as not to interfere
 +
with the standard RTC region.  Requires 8 bytes.
 +
 
 +
||
 +
# Use "select HAVE_USBDEBUG" on southbridges which have Debug Port code.
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USBDEBUG || drivers/usb || bool || USB 2.0 EHCI debug dongle support ||
 +
This option allows you to use a so-called USB EHCI Debug device
 +
(such as the Ajays NET20DC, AMIDebug RX, or a system using the
 +
Linux "EHCI Debug Device gadget" driver found in recent kernel)
 +
to retrieve the coreboot debug messages (instead, or in addition
 +
to, a serial port).
 +
 
 +
This feature is NOT supported on all chipsets in coreboot!
 +
 
 +
It also requires a USB2 controller which supports the EHCI
 +
Debug Port capability.
 +
 
 +
See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list
 +
of supported controllers.
 +
 
 +
If unsure, say N.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USBDEBUG_IN_ROMSTAGE || drivers/usb || bool || Enable early (pre-RAM) usbdebug ||
 +
Configuring USB controllers in system-agent binary may cause
 +
problems to usbdebug. Disabling this option delays usbdebug to
 +
be setup on entry to ramstage.
 +
 
 +
If unsure, say Y.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USBDEBUG_HCD_INDEX || drivers/usb || int || Index for EHCI controller to use with usbdebug ||
 +
Some boards have multiple EHCI controllers with possibly only
 +
one having the Debug Port capability on an external USB port.
 +
 
 +
Mapping of this index to PCI device functions is southbridge
 +
specific and mainboard level Kconfig should already provide
 +
a working default value here.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USBDEBUG_DEFAULT_PORT || drivers/usb || int || Default USB port to use as Debug Port ||
 +
Selects which physical USB port usbdebug dongle is connected to.
 +
Setting of 0 means to scan possible ports starting from 1.
 +
 
 +
Intel platforms have hardwired the debug port location and this
 +
setting makes no difference there.
 +
 
 +
Hence, if you select the correct port here, you can speed up
 +
your boot time. Which USB port number refers to which actual
 +
port on your mainboard (potentially also USB pin headers on
 +
your mainboard) is highly board-specific, and you'll likely
 +
have to find out by trial-and-error.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USBDEBUG_DONGLE_BEAGLEBONE || drivers/usb || bool || BeagleBone ||
 +
Use this to configure the USB hub on BeagleBone board.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USBDEBUG_DONGLE_BEAGLEBONE_BLACK || drivers/usb || bool || BeagleBone Black ||
 +
Use this with BeagleBone Black.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USBDEBUG_DONGLE_FTDI_FT232H || drivers/usb || bool || FTDI FT232H UART ||
 +
Use this with FT232H usb-to-uart. Configuration is hard-coded
 +
to use 115200, 8n1, no flow control.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH || drivers/spi || bool ||  ||
 +
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_ATOMIC_SEQUENCING || drivers/spi || bool ||  ||
 +
Select this option if the SPI controller uses "atomic sequencing."
 +
Atomic sequencing is when the sequence of commands is pre-programmed
 +
in the SPI controller. Hardware manages the transaction instead of
 +
software. This is common on x86 platforms.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_MEMORY_MAPPED || drivers/spi || bool ||  ||
 +
Inform system if SPI is memory-mapped or not.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_SMM || drivers/spi || bool || SPI flash driver support in SMM ||
 +
Select this option if you want SPI flash support in SMM.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_NO_FAST_READ || drivers/spi || bool || Disable Fast Read command ||
 +
Select this option if your setup requires to avoid "fast read"s
 +
from the SPI flash parts.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_ADESTO || drivers/spi || bool ||  ||
 +
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash and your SPI flash is made by Adesto Technologies.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_AMIC || drivers/spi || bool ||  ||
 +
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash and your SPI flash is made by AMIC.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_ATMEL || drivers/spi || bool ||  ||
 +
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash and your SPI flash is made by Atmel.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_EON || drivers/spi || bool ||  ||
 +
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash and your SPI flash is made by EON.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_GIGADEVICE || drivers/spi || bool ||  ||
 +
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash and your SPI flash is made by Gigadevice.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_MACRONIX || drivers/spi || bool ||  ||
 +
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash and your SPI flash is made by Macronix.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_SPANSION || drivers/spi || bool ||  ||
 +
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash and your SPI flash is made by Spansion.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_SST || drivers/spi || bool ||  ||
 +
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash and your SPI flash is made by SST.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_STMICRO || drivers/spi || bool ||  ||
 +
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash and your SPI flash is made by ST MICRO.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_WINBOND || drivers/spi || bool ||  ||
 +
Select this option if your chipset driver needs to store certain
 +
data in the SPI flash and your SPI flash is made by Winbond.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B || drivers/spi || bool ||  ||
 +
Select this option if your SPI flash supports the fast read dual-
 +
output command (opcode 0x3b) where the opcode and address are sent
 +
to the chip on MOSI and data is received on both MOSI and MISO.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DIGITIZER_AUTODETECT || drivers/lenovo || bool || Autodetect ||
 +
The presence of digitizer is inferred from model number stored in
 +
AT24RF chip.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DIGITIZER_PRESENT || drivers/lenovo || bool || Present ||
 +
The digitizer is assumed to be present.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DIGITIZER_ABSENT || drivers/lenovo || bool || Absent ||
 +
The digitizer is assumed to be absent.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HYBRID_GRAPHICS_GPIO_NUM || drivers/lenovo || int ||  ||
 +
Set a default GPIO that sets the panel LVDS signal routing to
 +
integrated or discrete GPU.
 +
 
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| UART_OVERRIDE_INPUT_CLOCK_DIVIDER || drivers/uart || boolean ||  ||
 +
Set to "y" when the platform overrides the uart_input_clock_divider
 +
routine.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| UART_OVERRIDE_REFCLK || drivers/uart || boolean ||  ||
 +
Set to "y" when the platform overrides the uart_platform_refclk
 +
routine.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DRIVERS_UART_OXPCIE || drivers/uart || bool || Oxford OXPCIe952 ||  
 
Support for Oxford OXPCIe952 serial port PCIe cards.
 
Support for Oxford OXPCIe952 serial port PCIe cards.
 
Currently only devices with the vendor ID 0x1415 and device ID
 
Currently only devices with the vendor ID 0x1415 and device ID
0xc158 will work.
+
0xc158 or 0xc11b will work.
NOTE: Right now you have to set the base address of your OXPCIe952
+
card to exactly the value that the device allocator would set them
+
later on, or serial console functionality will stop as soon as the
+
resource allocator assigns a new base address to the device.
+
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BRIDGE_BUS || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge bus number ||  
+
| UART_USE_REFCLK_AS_INPUT_CLOCK || drivers/uart || bool || ||  
While coreboot is executing code from ROM, the coreboot resource
+
Use uart_platform_refclk to specify the input clock value.
allocator has not been running yet. Hence PCI devices living behind
+
a bridge are not yet visible to the system. In order to use an
+
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
+
that controls the OXPCIe952 controller first.
+
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BRIDGE_DEVICE || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge device number ||  
+
| UART_PCI_ADDR || drivers/uart || hex || UART's PCI bus, device, function address ||  
While coreboot is executing code from ROM, the coreboot resource
+
Specify zero if the UART is connected to another bus type.
allocator has not been running yet. Hence PCI devices living behind
+
For PCI based UARTs, build the value as:
a bridge are not yet visible to the system. In order to use an
+
* 1 << 31 - Valid bit, PCI UART in use
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
+
* Bus << 20
that controls the OXPCIe952 controller first.
+
* Device << 15
 +
* Function << 12
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BRIDGE_FUNCTION || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge function number ||  
+
| GIC || drivers/gic || None || ||  
While coreboot is executing code from ROM, the coreboot resource
+
This option enables GIC support, the ARM generic interrupt controller.
allocator has not been running yet. Hence PCI devices living behind
+
a bridge are not yet visible to the system. In order to use an
+
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
+
that controls the OXPCIe952 controller first.
+
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BRIDGE_SUBORDINATE || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge subordinate bus ||  
+
| REALTEK_8168_RESET || drivers/net || bool || Realtek 8168 reset ||  
While coreboot is executing code from ROM, the coreboot resource
+
This forces a realtek 10ec:8168 card to reset to ensure power state
allocator has not been running yet. Hence PCI devices living behind
+
is correct at boot.
a bridge are not yet visible to the system. In order to use an
+
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
+
that controls the OXPCIe952 controller first.
+
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BASE_ADDRESS || drivers/oxford/oxpcie || hex || Base address for rom stage console ||  
+
| DRIVERS_PS2_KEYBOARD || drivers/pc80/pc || bool || PS/2 keyboard init ||  
While coreboot is executing code from ROM, the coreboot resource
+
Enable this option to initialize PS/2 keyboards found connected
allocator has not been running yet. Hence PCI devices living behind
+
to the PS/2 port.
a bridge are not yet visible to the system. In order to use an
+
OXPCIe952 based PCIe card, coreboot has to set up a temporary address
+
for the OXPCIe952 controller.
+
  
 +
Some payloads (eg, filo) require this option.  Other payloads
 +
(eg, GRUB 2, SeaBIOS, Linux) do not require it.
 +
Initializing a PS/2 keyboard can take several hundred milliseconds.
 +
 +
If you know you will only use a payload which does not require
 +
this option, then you can say N here to speed up boot time.
 +
Otherwise say Y.
  
 
||
 
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_HAS_LPC_TPM || drivers/pc80/tpm || bool ||  ||
 +
Board has TPM support
  
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| LPC_TPM || drivers/pc80/tpm || bool || Enable TPM support ||
 +
Enable this option to enable LPC TPM support in coreboot.
 +
 +
If unsure, say N.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TPM_TIS_BASE_ADDRESS || drivers/pc80/tpm || hex ||  ||
 +
This can be used to adjust the TPM memory base address.
 +
The default is specified by the TCG PC Client Specific TPM
 +
Interface Specification 1.2 and should not be changed unless
 +
the TPM being used does not conform to TPM TIS 1.2.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TPM_PIRQ || drivers/pc80/tpm || hex ||  ||
 +
This can be used to specify a PIRQ to use instead of SERIRQ,
 +
which is needed for SPI TPM interrupt support on x86.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TPM_INIT_FAILURE_IS_FATAL || drivers/pc80/tpm || bool ||  ||
 +
What to do if TPM init failed. If true, force a hard reset,
 +
otherwise just log error message to console.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SKIP_TPM_STARTUP_ON_NORMAL_BOOT || drivers/pc80/tpm || bool ||  ||
 +
Skip TPM init on normal boot. Useful if payload does TPM init.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TPM_DEACTIVATE || drivers/pc80/tpm || bool || Deactivate TPM ||
 +
Deactivate TPM by issuing deactivate command.
 +
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PLATFORM_USES_FSP1_1 || drivers/intel/fsp1_1 || bool ||  ||
 +
Does the code require the Intel Firmware Support Package?
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Intel FSP 1.1 ||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_FSP_BIN || drivers/intel/fsp1_1 || bool || Should the Intel FSP binary be added to the flash image ||
 +
Select this option to add an Intel FSP binary to
 +
the resulting coreboot image.
 +
 +
Note: Without this binary, coreboot builds relying on the FSP
 +
will not boot
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_MICROCODE_CBFS_LEN || drivers/intel/fsp1_1 || hex || Microcode update region length in bytes ||
 +
The length in bytes of the microcode update region.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_MICROCODE_CBFS_LOC || drivers/intel/fsp1_1 || hex || Microcode update base address in CBFS ||
 +
The location (base address) in CBFS that contains the microcode update
 +
binary.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_FILE || drivers/intel/fsp1_1 || string || Intel FSP binary path and filename ||
 +
The path and filename of the Intel FSP binary for this platform.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_IMAGE_ID_STRING || drivers/intel/fsp1_1 || string || 8 byte platform string identifying the FSP platform ||
 +
8 ASCII character byte signature string that will help match the FSP
 +
binary to a supported hardware configuration.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_LOC || drivers/intel/fsp1_1 || hex || Intel FSP Binary location in CBFS ||
 +
The location in CBFS that the FSP is located. This must match the
 +
value that is set in the FSP binary.  If the FSP needs to be moved,
 +
rebase the FSP with Intel's BCT (tool).
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DISPLAY_UPD_DATA || drivers/intel/fsp1_1 || bool || Display UPD data ||
 +
Display the user specified product data prior to memory
 +
initialization.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_USES_UPD || drivers/intel/fsp1_1 || bool ||  ||
 +
If this FSP uses UPD/VPD data regions, select this in the chipset
 +
Kconfig.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USE_GENERIC_FSP_CAR_INC || drivers/intel/fsp1_1 || bool ||  ||
 +
The chipset can select this to use a generic cache_as_ram.inc file
 +
that should be good for all FSP based platforms.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| INTEL_DP || drivers/intel/gma || bool ||  ||
 +
helper functions for intel display port operations
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| INTEL_DDI || drivers/intel/gma || bool ||  ||
 +
helper functions for intel DDI operations
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Intel FSP ||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_FSP_BIN || drivers/intel/fsp1_0 || bool || Use Intel Firmware Support Package ||
 +
Select this option to add an Intel FSP binary to
 +
the resulting coreboot image.
 +
 +
Note: Without this binary, coreboot builds relying on the FSP
 +
will not boot
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_FILE || drivers/intel/fsp1_0 || string || Intel FSP binary path and filename ||
 +
The path and filename of the Intel FSP binary for this platform.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_LOC || drivers/intel/fsp1_0 || hex || Intel FSP Binary location in CBFS ||
 +
The location in CBFS that the FSP is located. This must match the
 +
value that is set in the FSP binary.  If the FSP needs to be moved,
 +
rebase the FSP with Intel's BCT (tool).
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_FSP_FAST_BOOT || drivers/intel/fsp1_0 || bool || Enable Fast Boot ||
 +
Enabling this feature will force the MRC data to be cached in NV
 +
storage to be used for speeding up boot time on future reboots
 +
and/or power cycles.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_MRC_CACHE || drivers/intel/fsp1_0 || bool ||  ||
 +
Enabling this feature will cause MRC data to be cached in NV storage.
 +
This can either be used for fast boot, or just because the FSP wants
 +
it to be saved.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MRC_CACHE_FMAP || drivers/intel/fsp1_0 || bool || Use MRC Cache in FMAP ||
 +
Use the region "RW_MRC_CACHE" in FMAP instead of "mrc.cache" in CBFS.
 +
You must define a region in your FMAP named "RW_MRC_CACHE".
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MRC_CACHE_SIZE || drivers/intel/fsp1_0 || hex || Fast Boot Data Cache Size ||
 +
This is the amount of space in NV storage that is reserved for the
 +
fast boot data cache storage.
 +
 +
WARNING: Because this area will be erased and re-written, the size
 +
should be a full sector of the flash ROM chip and nothing else should
 +
be included in CBFS in any sector that the fast boot cache data is in.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VIRTUAL_ROM_SIZE || drivers/intel/fsp1_0 || hex || Virtual ROM Size ||
 +
This is used to calculate the offset of the MRC data cache in NV
 +
Storage for fast boot.  If in doubt, leave this set to the default
 +
which sets the virtual size equal to the ROM size.
 +
 +
Example: Cougar Canyon 2 has two 8 MB SPI ROMs.  When the SPI ROMs are
 +
loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB.  When
 +
the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM
 +
size is 16 MB.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CACHE_ROM_SIZE_OVERRIDE || drivers/intel/fsp1_0 || hex || Cache ROM Size ||
 +
This is the size of the cachable area that is passed into the FSP in
 +
the early initialization.  Typically this should be the size of the CBFS
 +
area, but the size must be a power of 2 whereas the CBFS size does not
 +
have this limitation.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USE_GENERIC_FSP_CAR_INC || drivers/intel/fsp1_0 || bool ||  ||
 +
The chipset can select this to use a generic cache_as_ram.inc file
 +
that should be good for all FSP based platforms.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_USES_UPD || drivers/intel/fsp1_0 || bool ||  ||
 +
If this FSP uses UPD/VPD data regions, select this in the chipset Kconfig.
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PLATFORM_USES_FSP2_0 || drivers/intel/fsp2_0 || bool ||  ||
 +
Include FSP 2.0 wrappers and functionality
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ADD_FSP_BINARIES || drivers/intel/fsp2_0 || bool || Add Intel FSP 2.0 binaries to CBFS ||
 +
Add the FSP-M and FSP-S binaries to CBFS. Currently coreboot does not
 +
use the FSP-T binary and it is not added.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_M_FILE || drivers/intel/fsp2_0 || string || Intel FSP-M (memory init) binary path and filename ||
 +
The path and filename of the Intel FSP-M binary for this platform.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_S_FILE || drivers/intel/fsp2_0 || string || Intel FSP-S (silicon init) binary path and filename ||
 +
The path and filename of the Intel FSP-S binary for this platform.
 +
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DRIVERS_SIL_3114 || drivers/sil || bool || Silicon Image SIL3114 ||  
+
| DRIVERS_SIL_3114 || drivers/sil/3114 || bool || Silicon Image SIL3114 ||  
 
It sets PCI class to IDE compatible native mode, allowing
 
It sets PCI class to IDE compatible native mode, allowing
 
SeaBIOS, FILO etc... to boot from it.
 
SeaBIOS, FILO etc... to boot from it.
  
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DRIVER_TI_TPS65090 || drivers/ti/tps65090 || bool ||  ||
 +
TI TPS65090
  
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DRIVERS_EMULATION_QEMU_BOCHS || drivers/emulation/qemu || bool || bochs dispi interface vga driver ||
 +
VGA driver for qemu emulated vga cards supporting
 +
the bochs dispi interface.  This includes
 +
standard vga, vmware svga and qxl.  The default
 +
vga (cirrus) is *not* supported, so you have to
 +
pick another one explicitly via 'qemu -vga $card'.
  
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| DRIVER_XPOWERS_AXP209 || drivers/xpowers/axp209 || bool ||  ||
 +
X-Powers AXP902 Power Management Unit
 +
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| DRIVER_XPOWERS_AXP209_BOOTBLOCK || drivers/xpowers/axp209 || bool ||  ||
 +
Make AXP209 functionality available in he bootblock.
  
|- bgcolor="#6699dd"
+
||
! align="left" | Menu: Console || || || ||
+
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL8250 || console || bool || Serial port console output ||  
+
| DRIVER_PARADE_PS8640 || drivers/parade/ps8640 || bool || ||  
Send coreboot debug output to an I/O mapped serial port console.
+
Parade PS8640 MIPI DSI to eDP Converter
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL8250MEM || console || bool || Serial port console output (memory mapped) ||  
+
| DRIVER_PARADE_PS8625 || drivers/parade/ps8625 || bool || ||  
Send coreboot debug output to a memory mapped serial port console.
+
Parade ps8625 display port to lvds bridge
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM1 || console || bool || COM1/ttyS0, I/O port 0x3f8 ||  
+
| DRIVER_MAXIM_MAX77686 || drivers/maxim/max77686 || bool || ||  
Serial console on COM1/ttyS0 at I/O port 0x3f8.
+
Maxim MAX77686 power regulator
 +
 
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM2 || console || bool || COM2/ttyS1, I/O port 0x2f8 ||  
+
| DRIVERS_I2C_RTD2132 || drivers/i2c/rtd2132 || bool || ||  
Serial console on COM2/ttyS1 at I/O port 0x2f8.
+
Enable support for Realtek RTD2132 DisplayPort to LVDS bridge chip.
 +
 
 
||
 
||
 +
||
 +
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM3 || console || bool || COM3/ttyS2, I/O port 0x3e8 ||  
+
| ACPI_SATA_GENERATOR || acpi || bool || ||  
Serial console on COM3/ttyS2 at I/O port 0x3e8.
+
Use acpi sata port generator.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM4 || console || bool || COM4/ttyS3, I/O port 0x2e8 ||  
+
| ACPI_INTEL_HARDWARE_SLEEP_VALUES || acpi || bool ||  ||
Serial console on COM4/ttyS3 at I/O port 0x2e8.
+
Provide common definitions for Intel hardware PM1_CNT regiser sleep
 +
values.
 +
 
 +
||
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TPM || toplevel || bool ||  ||
 +
Enable this option to enable TPM support in coreboot.
 +
 
 +
If unsure, say N.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TPM2 || toplevel || bool ||  ||
 +
Enable this option to enable TPM2 support in coreboot.
 +
 
 +
If unsure, say N.
 +
 
 +
||
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: Console || || || ||
 +
|- bgcolor="#eeeeee"
 +
| BOOTBLOCK_CONSOLE || console || bool || Enable early (bootblock) console output. ||
 +
Use console during the bootblock if supported
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SQUELCH_EARLY_SMP || console || bool || Squelch AP CPUs from early console. ||
 +
When selected only the BSP CPU will output to early console.
 +
 
 +
Console drivers have unpredictable behaviour if multiple threads
 +
attempt to share the same resources without a spinlock.
 +
 
 +
If unsure, say Y.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_SERIAL || console || bool || Serial port console output ||
 +
Send coreboot debug output to a serial port.
 +
 
 +
The type of serial port driver selected based on your configuration is
 +
shown on the following menu line. Supporting multiple different types
 +
of UARTs in one build is not supported.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || I/O mapped, 8250-compatible ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || memory mapped, 8250-compatible ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || device-specific UART ||
 +
|- bgcolor="#eeeeee"
 +
| UART_FOR_CONSOLE || console || int || Index for UART port to use for console ||
 +
Select an I/O port to use for serial console:
 +
0 = 0x3f8, 1 = 0x2f8, 2 = 0x3e8, 3 = 0x2e8
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| TTYS0_BASE || console || hex ||  ||  
 
| TTYS0_BASE || console || hex ||  ||  
Map the COM port names to the respective I/O port.
+
Map the COM port number to the respective I/O port.
  
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Serial port base address = 0x3f8 ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Serial port base address = 0x2f8 ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Serial port base address = 0x3e8 ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Serial port base address = 0x2e8 ||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_SERIAL_921600 || console || bool || 921600 ||
 +
Set serial port Baud rate to 921600.
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_SERIAL_460800 || console || bool || 460800 ||
 +
Set serial port Baud rate to 460800.
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_SERIAL_230400 || console || bool || 230400 ||
 +
Set serial port Baud rate to 230400.
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
Line 724: Line 4,074:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| USBDEBUG || console || bool || USB 2.0 EHCI debug dongle support ||  
+
| SPKMODEM || console || bool || spkmodem (console on speaker) console output ||  
This option allows you to use a so-called USB EHCI Debug device
+
Send coreboot debug output through speaker
(such as the Ajays NET20DC, AMIDebug RX, or a system using the
+
Linux "EHCI Debug Device gadget" driver found in recent kernel)
+
to retrieve the coreboot debug messages (instead, or in addition
+
to, a serial port).
+
 
+
This feature is NOT supported on all chipsets in coreboot!
+
 
+
It also requires a USB2 controller which supports the EHCI
+
Debug Port capability.
+
 
+
See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list
+
of supported controllers.
+
 
+
If unsure, say N.
+
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| USBDEBUG_DEFAULT_PORT || console || int || Default USB port to use as Debug Port ||  
+
| CONSOLE_USB || console || bool || USB dongle console output ||  
This option selects which physical USB port coreboot will try to
+
Send coreboot debug output to USB.
use as EHCI Debug Port first (valid values are: 1-15).
+
  
If coreboot doesn't detect an EHCI Debug Port dongle on this port,
+
Configuration for USB hardware is under menu Generic Drivers.
it will try all the other ports one after the other. This will take
+
a few seconds of time though, and thus slow down the booting process.
+
 
+
Hence, if you select the correct port here, you can speed up
+
your boot time. Which USB port number (1-15) refers to which
+
actual port on your mainboard (potentially also USB pin headers
+
on your mainboard) is highly board-specific, and you'll likely
+
have to find out by trial-and-error.
+
  
 
||
 
||
Line 779: Line 4,106:
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| CONSOLE_NE2K_DST_IP || console || string || Destination IP of logging system ||  
 
| CONSOLE_NE2K_DST_IP || console || string || Destination IP of logging system ||  
This is IP adress of the system running for example
+
This is IP address of the system running for example
 
netcat command to dump the packets.
 
netcat command to dump the packets.
  
Line 794: Line 4,121:
 
32 bytes of IO spaces will be used (and align on 32 bytes
 
32 bytes of IO spaces will be used (and align on 32 bytes
 
boundary, qemu needs broader align)
 
boundary, qemu needs broader align)
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_8 || console || bool || 8: SPEW ||  
+
| CONSOLE_CBMEM || console || bool || Send console output to a CBMEM buffer ||  
Way too many details.
+
Enable this to save the console output in a CBMEM buffer. This would
 +
allow to see coreboot console output from Linux space.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_7 || console || bool || 7: DEBUG ||  
+
| CONSOLE_CBMEM_BUFFER_SIZE || console || hex || Room allocated for console output in CBMEM ||  
Debug-level messages.
+
Space allocated for console output storage in CBMEM. The default
 +
value (128K or 0x20000 bytes) is large enough to accommodate
 +
even the BIOS_SPEW level.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_6 || console || bool || 6: INFO ||  
+
| CONSOLE_CBMEM_DUMP_TO_UART || console || bool || Dump CBMEM console on resets ||  
Informational messages.
+
Enable this to have CBMEM console buffer contents dumped on the
 +
serial output in case serial console is disabled and the device
 +
resets itself while trying to boot the payload.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_5 || console || bool || 5: NOTICE ||
+
| CONSOLE_QEMU_DEBUGCON || console || bool || QEMU debug console output ||  
Normal but significant conditions.
+
Send coreboot debug output to QEMU's isa-debugcon device:
||
+
 
|- bgcolor="#eeeeee"
+
qemu-system-x86_64 \
| MAXIMUM_CONSOLE_LOGLEVEL_4 || console || bool || 4: WARNING ||  
+
-chardev file,id=debugcon,path=/dir/file.log \
Warning conditions.
+
-device isa-debugcon,iobase=0x402,chardev=debugcon
||
+
|- bgcolor="#eeeeee"
+
| MAXIMUM_CONSOLE_LOGLEVEL_3 || console || bool || 3: ERR ||
+
Error conditions.
+
||
+
|- bgcolor="#eeeeee"
+
| MAXIMUM_CONSOLE_LOGLEVEL_2 || console || bool || 2: CRIT ||
+
Critical conditions.
+
||
+
|- bgcolor="#eeeeee"
+
| MAXIMUM_CONSOLE_LOGLEVEL_1 || console || bool || 1: ALERT ||
+
Action must be taken immediately.
+
||
+
|- bgcolor="#eeeeee"
+
| MAXIMUM_CONSOLE_LOGLEVEL_0 || console || bool || 0: EMERG ||
+
System is unusable.
+
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL || console || int || ||  
+
| SPI_CONSOLE || console || bool || SPI debug console output ||  
Map the log level config names to an integer.
+
Enable support for the debug console on the Dediprog EM100Pro.
 +
This is currently working only in ramstage due to how the spi
 +
drivers are written.
  
 
||
 
||
Line 879: Line 4,199:
 
| DEFAULT_CONSOLE_LOGLEVEL || console || int ||  ||  
 
| DEFAULT_CONSOLE_LOGLEVEL || console || int ||  ||  
 
Map the log level config names to an integer.
 
Map the log level config names to an integer.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CMOS_POST || console || bool || Store post codes in CMOS for debugging ||
 +
If enabled, coreboot will store post codes in CMOS and switch between
 +
two offsets on each boot so the last post code in the previous boot
 +
can be retrieved.  This uses 3 bytes of CMOS.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CMOS_POST_OFFSET || console || hex || Offset into CMOS to store POST codes ||
 +
If CMOS_POST is enabled then an offset into CMOS must be provided.
 +
If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value
 +
defined in the mainboard option table.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CMOS_POST_EXTRA || console || bool || Store extra logging info into CMOS ||
 +
This will enable extra logging of work that happens between post
 +
codes into CMOS for debug.  This uses an additional 8 bytes of CMOS.
  
 
||
 
||
Line 888: Line 4,228:
  
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| POST_IO || console || bool || Send POST codes to an IO port ||
 +
If enabled, POST codes will be written to an IO port.
  
 +
||
 +
|- bgcolor="#eeeeee"
 +
| POST_IO_PORT || console || hex || IO port for POST codes ||
 +
POST codes on x86 are typically written to the LPC bus on port
 +
0x80. However, it may be desirable to change the port number
 +
depending on the presence of coprocessors/microcontrollers or if the
 +
platform does not support IO in the conventional x86 manner.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NO_EARLY_BOOTBLOCK_POSTCODES || console || hex ||  ||
 +
Some chipsets require that the routing for the port 80h POST
 +
code be configured before any POST codes are sent out.
 +
This can be done in the boot block, but there are a couple of
 +
POST codes that go out before the chipset's bootblock initialization
 +
can happen.  This option suppresses those POST codes.
 +
 +
||
 +
 +
|- bgcolor="#eeeeee"
 +
| RESUME_PATH_SAME_AS_BOOT || toplevel || bool ||  ||
 +
This option indicates that when a system resumes it takes the
 +
same path as a regular boot. e.g. an x86 system runs from the
 +
reset vector at 0xfffffff0 on both resume and warm/cold boot.
 +
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| HAVE_HARD_RESET || toplevel || bool ||  ||  
 
| HAVE_HARD_RESET || toplevel || bool ||  ||  
 
This variable specifies whether a given board has a hard_reset
 
This variable specifies whether a given board has a hard_reset
 
function, no matter if it's provided by board code or chipset code.
 
function, no matter if it's provided by board code or chipset code.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK || toplevel || bool ||  ||
 +
This should be enabled on certain plaforms, such as the AMD
 +
SR565x, that cannot handle concurrent CBFS accesses from
 +
multiple APs during early startup.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_MONOTONIC_TIMER || toplevel || bool ||  ||
 +
The board/chipset provides a monotonic timer.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| GENERIC_UDELAY || toplevel || bool ||  ||
 +
The board/chipset uses a generic udelay function utilizing the
 +
monotonic timer.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TIMER_QUEUE || toplevel || bool ||  ||
 +
Provide a timer queue for performing time-based callbacks.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| COOP_MULTITASKING || toplevel || bool ||  ||
 +
Cooperative multitasking allows callbacks to be multiplexed on the
 +
main thread of ramstage. With this enabled it allows for multiple
 +
execution paths to take place when they have udelay() calls within
 +
their code.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NUM_THREADS || toplevel || int ||  ||
 +
How many execution threads to cooperatively multitask with.
  
 
||
 
||
Line 916: Line 4,321:
 
This variable specifies whether a given board has ACPI table support.
 
This variable specifies whether a given board has ACPI table support.
 
It is usually set in mainboard/*/Kconfig.
 
It is usually set in mainboard/*/Kconfig.
Whether or not the ACPI tables are actually generated by coreboot
 
is configurable by the user via GENERATE_ACPI_TABLES.
 
  
 
||
 
||
Line 936: Line 4,339:
  
 
||
 
||
|- bgcolor="#6699dd"
 
! align="left" | Menu: System tables || || || ||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| GENERATE_ACPI_TABLES || toplevel || bool || Generate ACPI tables ||  
+
| MAX_PIRQ_LINKS || toplevel || int || ||  
Generate ACPI tables for this board.
+
This variable specifies the number of PIRQ interrupt links which are
 +
routable. On most chipsets, this is 4, INTA through INTD. Some
 +
chipsets offer more than four links, commonly up to INTH. They may
 +
also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
 +
table specifies links greater than 4, pirq_route_irqs will not
 +
function properly, unless this variable is correctly set.
  
If unsure, say Y.
+
||
 +
|- bgcolor="#eeeeee"
 +
| ACPI_NHLT || toplevel || bool ||  ||
 +
Build support for NHLT (non HD Audio) ACPI table generation.
  
 
||
 
||
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: System tables || || || ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| GENERATE_MP_TABLE || toplevel || bool || Generate an MP table ||  
 
| GENERATE_MP_TABLE || toplevel || bool || Generate an MP table ||  
Line 965: Line 4,376:
  
 
If unsure, say Y.
 
If unsure, say Y.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_SERIAL_NUMBER || toplevel || string || SMBIOS Serial Number ||
 +
The Serial Number to store in SMBIOS structures.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_VERSION || toplevel || string || SMBIOS Version Number ||
 +
The Version Number to store in SMBIOS structures.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_SMBIOS_MANUFACTURER || toplevel || string || SMBIOS Manufacturer ||
 +
Override the default Manufacturer stored in SMBIOS structures.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_SMBIOS_PRODUCT_NAME || toplevel || string || SMBIOS Product name ||
 +
Override the default Product name stored in SMBIOS structures.
  
 
||
 
||
Line 971: Line 4,402:
 
! align="left" | Menu: Payload || || || ||
 
! align="left" | Menu: Payload || || || ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PAYLOAD_NONE || toplevel || bool || None ||  
+
| PAYLOAD_NONE || payloads || bool || None ||  
 
Select this option if you want to create an "empty" coreboot
 
Select this option if you want to create an "empty" coreboot
 
ROM image for a certain mainboard, i.e. a coreboot ROM image
 
ROM image for a certain mainboard, i.e. a coreboot ROM image
Line 981: Line 4,412:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PAYLOAD_ELF || toplevel || bool || An ELF executable payload ||  
+
| PAYLOAD_ELF || payloads || bool || An ELF executable payload ||  
 
Select this option if you have a payload image (an ELF file)
 
Select this option if you have a payload image (an ELF file)
 
which coreboot should run as soon as the basic hardware
 
which coreboot should run as soon as the basic hardware
Line 991: Line 4,422:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PAYLOAD_SEABIOS || toplevel || bool || SeaBIOS ||  
+
| PAYLOAD_UBOOT || payloads/external/U-Boot.name || bool || U-Boot (Experimental) ||
 +
Select this option if you want to build a coreboot image
 +
with a U-Boot payload.
 +
 
 +
See http://coreboot.org/Payloads and U-Boot's documentation
 +
at http://git.denx.de/?p=u-boot.git;a=blob;f=doc/README.x86
 +
for more information.
 +
 
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PAYLOAD_SEABIOS || payloads/external/SeaBIOS.name || bool || SeaBIOS ||  
 
Select this option if you want to build a coreboot image
 
Select this option if you want to build a coreboot image
 
with a SeaBIOS payload. If you don't know what this is
 
with a SeaBIOS payload. If you don't know what this is
Line 998: Line 4,441:
 
See http://coreboot.org/Payloads for more information.
 
See http://coreboot.org/Payloads for more information.
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PAYLOAD_FILO || toplevel || bool || FILO ||  
+
| PAYLOAD_FILO || payloads/external/FILO.name || bool || FILO ||  
 
Select this option if you want to build a coreboot image
 
Select this option if you want to build a coreboot image
 
with a FILO payload. If you don't know what this is
 
with a FILO payload. If you don't know what this is
Line 1,006: Line 4,450:
  
 
See http://coreboot.org/Payloads for more information.
 
See http://coreboot.org/Payloads for more information.
 +
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PAYLOAD_LINUX || payloads/external/linux.name || bool || A Linux payload ||
 +
Select this option if you have a Linux bzImage which coreboot
 +
should run as soon as the basic hardware initialization
 +
is completed.
 +
 +
You will be able to specify the location and file name of the
 +
payload image later.
 +
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PAYLOAD_TIANOCORE || payloads/external/tianocore.name || bool || Tiano Core ||
 +
Select this option if you want to build a coreboot image
 +
with a Tiano Core payload. If you don't know what this is
 +
about, just leave it enabled.
 +
 +
See http://coreboot.org/Payloads for more information.
 +
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PAYLOAD_GRUB2 || payloads/external/GRUB2.name || bool || GRUB2 ||
 +
Select this option if you want to build a coreboot image
 +
with a GRUB2 payload. If you don't know what this is
 +
about, just leave it enabled.
 +
 +
See http://coreboot.org/Payloads for more information.
 +
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PAYLOAD_DEPTHCHARGE || payloads/external/depthcharge.name || bool || Depthcharge ||
 +
Select this option if you want to build a coreboot image
 +
with a depthcharge payload.
 +
 +
See http://coreboot.org/Payloads for more information.
 +
 +
||
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| UBOOT_STABLE || payloads/external/U-Boot || bool || v2016.1 ||
 +
Stable U-Boot version
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| UBOOT_MASTER || payloads/external/U-Boot || bool || master ||
 +
Newest U-Boot version
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PAYLOAD_CONFIGFILE || payloads/external/U-Boot || string || U-Boot config file ||
 +
This option allows a platform to set Kconfig options for a basic
 +
U-Boot payload.  In general, if the option is used, the default
 +
would be "$(top)/src/mainboard/$(MAINBOARDDIR)/config_uboot"
 +
for a config stored in the coreboot mainboard directory, or
 +
"$(project_dir)/configs/coreboot-x86_defconfig" to use a config
 +
from the U-Boot config directory
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SEABIOS_STABLE || toplevel || bool || stable ||  
+
| SEABIOS_STABLE || payloads/external/SeaBIOS || bool || 1.9.1 ||  
 
Stable SeaBIOS version
 
Stable SeaBIOS version
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SEABIOS_MASTER || toplevel || bool || master ||  
+
| SEABIOS_MASTER || payloads/external/SeaBIOS || bool || master ||  
 
Newest SeaBIOS version
 
Newest SeaBIOS version
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FILO_STABLE || toplevel || bool || 0.6.0 ||  
+
| SEABIOS_REVISION || payloads/external/SeaBIOS || bool || git revision ||  
Stable FILO version
+
Select this option if you have a specific commit or branch
 +
that you want to use as the revision from which to
 +
build SeaBIOS.
 +
 
 +
You will be able to specify the name of a branch or a commit id
 +
later.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FILO_MASTER || toplevel || bool || HEAD ||  
+
| SEABIOS_REVISION_ID || payloads/external/SeaBIOS || string || Insert a commit's SHA-1 or a branch name ||  
Newest FILO version
+
The commit's SHA-1 or branch name of the revision to use.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PAYLOAD_FILE || toplevel || string || Payload path and filename ||  
+
| SEABIOS_PS2_TIMEOUT || payloads/external/SeaBIOS || int || PS/2 keyboard controller initialization timeout (milliseconds) ||  
The path and filename of the ELF executable file to use as payload.
+
Some PS/2 keyboard controllers don't respond to commands immediately
 +
after powering on. This specifies how long SeaBIOS will wait for the
 +
keyboard controller to become ready before giving up.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COMPRESSED_PAYLOAD_LZMA || toplevel || bool || Use LZMA compression for payloads ||  
+
| SEABIOS_THREAD_OPTIONROMS || payloads/external/SeaBIOS || bool || Hardware init during option ROM execution ||  
In order to reduce the size payloads take up in the ROM chip
+
Allow hardware init to run in parallel with optionrom execution.
coreboot can compress them using the LZMA algorithm.
+
 
 +
This can reduce boot time, but can cause some timing
 +
variations during option ROM code execution. It is not
 +
known if all option ROMs will behave properly with this option.
  
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| SEABIOS_VGA_COREBOOT || payloads/external/SeaBIOS || bool || Include generated option rom that implements legacy VGA BIOS compatibility ||
 +
Coreboot can initialize the GPU of some mainboards.
  
 +
After initializing the GPU, the information about it can be passed to the payload.
 +
Provide an option rom that implements this legacy VGA BIOS compatibility requirement.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PAYLOAD_CONFIGFILE || payloads/external/SeaBIOS || string || SeaBIOS config file ||
 +
This option allows a platform to set Kconfig options for a basic
 +
SeaBIOS payload.  In general, if the option is used, the default
 +
would be "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios"
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SEABIOS_BOOTORDER_FILE || payloads/external/SeaBIOS || string || SeaBIOS bootorder file ||
 +
Add a SeaBIOS bootorder file.  From the wiki:
 +
"The bootorder file may be used to configure the boot up order. The file
 +
should be ASCII text and contain one line per boot method. The description
 +
of each boot method follows an Open Firmware device path format. SeaBIOS
 +
will attempt to boot from each item in the file - first line of the file
 +
first."
 +
 +
See: https://www.coreboot.org/SeaBIOS#Configuring_boot_order
 +
 +
If used, a typical value would be:
 +
$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder
 +
 +
||
 
|- bgcolor="#6699dd"
 
|- bgcolor="#6699dd"
! align="left" | Menu: VGA BIOS || || || ||
+
! align="left" | Menu: PXE Options || || || ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VGA_BIOS || toplevel || bool || Add a VGA BIOS image ||  
+
| PXE_ROM || payloads/external/iPXE || bool || Add an existing PXE ROM image ||  
Select this option if you have a VGA BIOS image that you would
+
Select this option if you have a PXE ROM image that you would
 
like to add to your ROM.
 
like to add to your ROM.
  
You will be able to specify the location and file name of the
+
||
image later.
+
|- bgcolor="#eeeeee"
 +
| BUILD_IPXE || payloads/external/iPXE || bool || Build and add an iPXE ROM ||
 +
Select this option to fetch and build a ROM from the iPXE project.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VGA_BIOS_FILE || toplevel || string || VGA BIOS path and filename ||  
+
| IPXE_STABLE || payloads/external/iPXE || bool || 2016.2 ||  
The path and filename of the file to use as VGA BIOS.
+
iPXE uses a rolling release with no stable version, for
 +
reproducibility, use the last commit of a given month as the
 +
'stable' version.
 +
This is iPXE from the end of February, 2016.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VGA_BIOS_ID || toplevel || string || VGA device PCI IDs ||  
+
| IPXE_MASTER || payloads/external/iPXE || bool || master ||
 +
Newest iPXE version.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PXE_ROM_FILE || payloads/external/iPXE || string || PXE ROM filename ||
 +
The path and filename of the file to use as PXE ROM.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PXE_ROM_ID || payloads/external/iPXE || string || network card PCI IDs ||  
 
The comma-separated PCI vendor and device ID that would associate
 
The comma-separated PCI vendor and device ID that would associate
your VGA BIOS to your video card.
+
your PXE ROM to your network card.
  
Example: 1106,3230
+
Example: 10ec,8168
  
In the above example 1106 is the PCI vendor ID (in hex, but without
+
In the above example 10ec is the PCI vendor ID (in hex, but without
the "0x" prefix) and 3230 specifies the PCI device ID of the
+
the "0x" prefix) and 8168 specifies the PCI device ID of the
video card (also in hex, without "0x" prefix).
+
network card (also in hex, without "0x" prefix).
 +
 
 +
Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.
  
 
||
 
||
 +
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| INTEL_MBI || toplevel || bool || Add an MBI image ||  
+
| FILO_STABLE || payloads/external/FILO || bool || 0.6.0 ||  
Select this option if you have an Intel MBI image that you would
+
Stable FILO version
like to add to your ROM.
+
  
You will be able to specify the location and file name of the
+
||
image later.
+
|- bgcolor="#eeeeee"
 +
| FILO_MASTER || payloads/external/FILO || bool || HEAD ||
 +
Newest FILO version
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MBI_FILE || toplevel || string || Intel MBI path and filename ||  
+
| PAYLOAD_FILE || payloads/external/linux || string || Linux path and filename ||  
The path and filename of the file to use as VGA BIOS.
+
The path and filename of the bzImage kernel to use as payload.
  
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| LINUX_COMMAND_LINE || payloads/external/linux || string || Linux command line ||
 +
A command line to add to the Linux kernel.
  
 +
||
 +
|- bgcolor="#eeeeee"
 +
| LINUX_INITRD || payloads/external/linux || string || Linux initrd ||
 +
An initrd image to add to the Linux kernel.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PAYLOAD_FILE || payloads/external/tianocore || string || Tianocore firmware volume ||
 +
The result of a corebootPkg build
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| GRUB2_MASTER || payloads/external/GRUB2 || bool || HEAD ||
 +
Newest GRUB2 version
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| GRUB2_EXTRA_MODULES || payloads/external/GRUB2 || string || Extra modules to include in GRUB image ||
 +
Space-separated list of additional modules to include. Few common
 +
ones:
 +
* bsd for *BSD
 +
* png/jpg for PNG/JPG images
 +
* gfxmenu for graphical menus (you'll need a theme as well)
 +
* gfxterm_background for setting background
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PAYLOAD_FILE || payloads || string || Payload path and filename ||
 +
The path and filename of the ELF executable file to use as payload.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| COMPRESSED_PAYLOAD_LZMA || payloads || bool || Use LZMA compression for payloads ||
 +
In order to reduce the size payloads take up in the ROM chip
 +
coreboot can compress them using the LZMA algorithm.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PAYLOAD_OPTIONS || payloads || string ||  ||
 +
Additional cbfstool options for the payload
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PAYLOAD_IS_FLAT_BINARY || payloads || string ||  ||
 +
Add the payload to cbfs as a flat binary type instead of as an
 +
elf payload
 +
 +
||
 
|- bgcolor="#6699dd"
 
|- bgcolor="#6699dd"
! align="left" | Menu: Display || || || ||
+
! align="left" | Menu: Secondary Payloads || || || ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FRAMEBUFFER_SET_VESA_MODE || toplevel || bool || Set VESA framebuffer mode ||  
+
| COREINFO_SECONDARY_PAYLOAD || payloads || bool || Load coreinfo as a secondary payload ||  
Set VESA framebuffer mode (needed for bootsplash)
+
coreinfo can be loaded as a secondary payload under SeaBIOS, GRUB,
 +
or any other payload that can load additional payloads.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FRAMEBUFFER_VESA_MODE || toplevel || hex || VESA framebuffer video mode ||  
+
| MEMTEST_SECONDARY_PAYLOAD || payloads || bool || Load Memtest86+ as a secondary payload ||  
This option sets the resolution used for the coreboot framebuffer (and
+
Memtest86+ can be loaded as a secondary payload under SeaBIOS, GRUB,
bootsplash screen). Set to 0x117 for 1024x768x16. A diligent soul will
+
or any other payload that can load additional payloads.
some day make this a "choice".
+
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FRAMEBUFFER_KEEP_VESA_MODE || toplevel || bool || Keep VESA framebuffer ||  
+
| MEMTEST_STABLE || payloads || bool || Stable ||  
This option keeps the framebuffer mode set after coreboot finishes
+
Stable Memtest86+ version.
execution. If this option is enabled, coreboot will pass a
+
framebuffer entry in its coreboot table and the payload will need a
+
framebuffer driver. If this option is disabled, coreboot will switch
+
back to text mode before handing control to a payload.
+
  
 +
For reproducible builds, this option must be selected.
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOOTSPLASH || toplevel || bool || Show graphical bootsplash ||  
+
| MEMTEST_MASTER || payloads || bool || Master ||  
This option shows a graphical bootsplash screen. The grapics are
+
Newest Memtest86+ version.
loaded from the CBFS file bootsplash.jpg.
+
  
 +
This option will fetch the newest version of the Memtest86+ code,
 +
updating as new changes are committed.  This makes the build
 +
non-reproducible, as it can fetch different code each time.
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOOTSPLASH_FILE || toplevel || string || Bootsplash path and filename ||  
+
| NVRAMCUI_SECONDARY_PAYLOAD || payloads || bool || Load nvramcui as a secondary payload ||  
The path and filename of the file to use as graphical bootsplash
+
nvramcui can be loaded as a secondary payload under SeaBIOS, GRUB,
screen. The file format has to be jpg.
+
or any other payload that can load additional payloads.
 +
 
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| TINT_SECONDARY_PAYLOAD || payloads || bool || Load tint as a secondary payload ||
 +
tint can be loaded as a secondary payload under SeaBIOS, GRUB,
 +
or any other payload that can load additional payloads.
 +
 +
||
 +
  
 
|- bgcolor="#6699dd"
 
|- bgcolor="#6699dd"
Line 1,120: Line 4,744:
 
If enabled, you will be able to set breakpoints for gdb debugging.
 
If enabled, you will be able to set breakpoints for gdb debugging.
 
See src/arch/x86/lib/c_start.S for details.
 
See src/arch/x86/lib/c_start.S for details.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| GDB_WAIT || toplevel || bool || Wait for a GDB connection ||
 +
If enabled, coreboot will wait for a GDB connection.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FATAL_ASSERTS || toplevel || bool || Halt when hitting a BUG() or assertion error ||
 +
If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_CBFS || toplevel || bool || Output verbose CBFS debug messages ||
 +
This option enables additional CBFS related debug messages.
  
 
||
 
||
Line 1,177: Line 4,816:
  
 
If unsure, say N.
 
If unsure, say N.
 +
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
Line 1,185: Line 4,825:
  
 
If unsure, say N.
 
If unsure, say N.
 +
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
Line 1,193: Line 4,834:
  
 
If unsure, say N.
 
If unsure, say N.
 +
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
Line 1,308: Line 4,950:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| LLSHELL || toplevel || bool || Built-in low-level shell ||  
+
| X86EMU_DEBUG_TIMINGS || toplevel || bool || Output timing information ||  
If enabled, you will have a low level shell to examine your machine.
+
Print timing information needed by i915tool.
Put llshell() in your (romstage) code to start the shell.
+
 
See src/arch/x86/llshell/llshell.inc for details.
+
If unsure, say N.
  
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_TPM || toplevel || bool || Output verbose TPM debug messages ||
 +
This option enables additional TPM related debug messages.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_SPI_FLASH || toplevel || bool || Output verbose SPI flash debug messages ||
 +
This option enables additional SPI flash related debug messages.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_USBDEBUG || toplevel || bool || Output verbose USB 2.0 EHCI debug dongle messages ||
 +
This option enables additional USB 2.0 debug dongle related messages.
 +
 +
Select this to debug the connection of usbdebug dongle. Note that
 +
you need some other working console to receive the messages.
 +
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_INTEL_ME || toplevel || bool || Verbose logging for Intel Management Engine ||
 +
Enable verbose logging for Intel Management Engine driver that
 +
is present on Intel 6-series chipsets.
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
Line 1,319: Line 4,984:
 
the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
 
the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
 
the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
 
the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
of calling function. Please note some printk releated functions
+
of calling function. Please note some printk related functions
 
are omitted from trace to have good looking console dumps.
 
are omitted from trace to have good looking console dumps.
 +
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_COVERAGE || toplevel || bool || Debug code coverage ||
 +
If enabled, the code coverage hooks in coreboot will output some
 +
information about the coverage data that is dumped.
  
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_BOOT_STATE || toplevel || bool || Debug boot state machine ||
 +
Control debugging of the boot state machine.  When selected displays
 +
the state boundaries in ramstage.
 +
 +
||
 +
 +
|- bgcolor="#eeeeee"
 +
| IASL_WARNINGS_ARE_ERRORS || toplevel || bool ||  ||
 +
Select to Fail the build if a IASL generates a warning.
 +
This will be defaulted to disabled for the platforms that
 +
currently fail.  This allows the REST of the platforms to
 +
have this check enabled while we're working to get those
 +
boards fixed.
 +
 +
DO NOT ADD TO ANY ADDITIONAL PLATFORMS INSTEAD OF FIXING
 +
THE ASL.
 +
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| POWER_BUTTON_DEFAULT_ENABLE || toplevel || hex ||  ||  
+
| POWER_BUTTON_DEFAULT_ENABLE || toplevel || bool ||  ||  
 
Select when the board has a power button which can optionally be
 
Select when the board has a power button which can optionally be
 
disabled by the user.
 
disabled by the user.
Line 1,330: Line 5,020:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| POWER_BUTTON_DEFAULT_DISABLE || toplevel || hex ||  ||  
+
| POWER_BUTTON_DEFAULT_DISABLE || toplevel || bool ||  ||  
 
Select when the board has a power button which can optionally be
 
Select when the board has a power button which can optionally be
 
enabled by the user, e.g. when the board ships with a jumper over
 
enabled by the user, e.g. when the board ships with a jumper over
Line 1,337: Line 5,027:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| POWER_BUTTON_FORCE_ENABLE || toplevel || hex ||  ||  
+
| POWER_BUTTON_FORCE_ENABLE || toplevel || bool ||  ||  
 
Select when the board requires that the power button is always
 
Select when the board requires that the power button is always
 
enabled.
 
enabled.
Line 1,343: Line 5,033:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| POWER_BUTTON_FORCE_DISABLE || toplevel || hex ||  ||  
+
| POWER_BUTTON_FORCE_DISABLE || toplevel || bool ||  ||  
 
Select when the board requires that the power button is always
 
Select when the board requires that the power button is always
 
disabled, e.g. when it has been hardwired to ground.
 
disabled, e.g. when it has been hardwired to ground.
Line 1,353: Line 5,043:
  
 
||
 
||
|- bgcolor="#6699dd"
 
! align="left" | Menu: Deprecated || || || ||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOARD_HAS_HARD_RESET || toplevel.deprecated_options || bool ||  ||  
+
| REG_SCRIPT || toplevel || bool ||  ||  
This variable specifies whether a given board has a reset.c
+
Internal option that controls whether we compile in register scripts.
file containing a hard_reset() function.
+
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOARD_HAS_FADT || toplevel.deprecated_options || bool ||  ||  
+
| MAX_REBOOT_CNT || toplevel || int ||  ||  
This variable specifies whether a given board has a board-local
+
Internal option that sets the maximum number of bootblock executions allowed
FADT in fadt.c. Long-term, those should be moved to appropriate
+
with the normal image enabled before assuming the normal image is defective
chipset components (eg. southbridge).
+
and switching to the fallback image.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HAVE_BUS_CONFIG || toplevel.deprecated_options || bool ||  ||  
+
| CBFS_SIZE || toplevel || hex ||  ||  
This variable specifies whether a given board has a get_bus_conf.c
+
This is the part of the ROM actually managed by CBFS. Set it to be
file containing information about bus routing.
+
equal to the full rom size if that hasn't been overridden by the
 +
chipset or mainboard.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DRIVERS_PS2_KEYBOARD || toplevel.deprecated_options || bool || PS/2 keyboard init ||  
+
| CREATE_BOARD_CHECKLIST || toplevel || bool || ||  
Enable this option to initialize PS/2 keyboards found connected
+
When selected, creates a webpage showing the implementation status for
to the PS/2 port.
+
the boardRoutines highlighted in green are complete, yellow are
 
+
optional and red are required and must be implemented. A table is
Some payloads (eg, filo) require this optionOther payloads
+
produced for each stage of the boot process except the bootblock. The
(eg, SeaBIOS, Linux) do not require it.
+
red items may be used as an implementation checklist for the board.
Initializing a PS/2 keyboard can take several hundred milliseconds.
+
 
+
If you know you will only use a payload which does not require
+
this option, then you can say N here to speed up boot time.
+
Otherwise say Y.
+
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PCIE_TUNING || toplevel.deprecated_options || bool ||  ||  
+
| MAKE_CHECKLIST_PUBLIC || toplevel || bool ||  ||  
This variable enables certain PCIe optimizations. Right now it's
+
When selected, build/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html
only ASPM and it's untested.
+
is copied into the Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board
 +
directory.
  
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| CHECKLIST_DATA_FILE_LOCATION || toplevel || string ||  ||
 +
Location of the <stage>_complete.dat and <stage>_optional.dat files
 +
that are consumed during checklist processing.  <stage>_complete.dat
 +
contains the symbols that are expected to be in the resulting image.
 +
<stage>_optional.dat is a subset of <stage>_complete.dat and contains
 +
a list of weak symbols which the resulting image may consume.  Other
 +
symbols contained only in <stage>_complete.dat will be flagged as
 +
required and not implemented if a weak implementation is found in the
 +
resulting image.
  
 +
||
 
|}
 
|}

Latest revision as of 23:01, 23 July 2016

This is an automatically generated list of coreboot compile-time options.

Last update: 4.3-1760-g168eb6a

Option Source Format Short Description Description
Menu: General setup
LOCALVERSION toplevel string Local version string

Append an extra string to the end of the coreboot version.

This can be useful if, for instance, you want to append the respective board's hostname or some other identifying string to the coreboot version number, so that you can easily distinguish boot logs of different boards from each other.

CBFS_PREFIX toplevel string CBFS prefix to use

Select the prefix to all files put into the image. It's "fallback" by default, "normal" is a common alternative.

COMMON_CBFS_SPI_WRAPPER toplevel bool

Use common wrapper to interface CBFS to SPI bootrom.

MULTIPLE_CBFS_INSTANCES toplevel bool Multiple CBFS instances in the bootrom

Account for the firmware image containing more than one CBFS instance. Locations of instances are known at build time and are communicated between coreboot stages to make sure the next stage is loaded from the appropriate instance.

MULTIPLE_CBFS_INSTANCES toplevel bool Compiler to use

This option allows you to select the compiler used for building coreboot. You must build the coreboot crosscompiler for the board that you have selected.

To build all the GCC crosscompilers (takes a LONG time), run: make crossgcc

For help on individual architectures, run the command: make help_toolchain

COMPILER_GCC toplevel bool GCC

Use the GNU Compiler Collection (GCC) to build coreboot.

For details see http://gcc.gnu.org.

COMPILER_LLVM_CLANG toplevel bool LLVM/clang (TESTING ONLY - Not currently working)

Use LLVM/clang to build coreboot. To use this, you must build the coreboot version of the clang compiler. Run the command make clang Note that this option is not currently working correctly and should really only be selected if you're trying to work on getting clang operational.

For details see http://clang.llvm.org.

ANY_TOOLCHAIN toplevel bool Allow building with any toolchain

Many toolchains break when building coreboot since it uses quite unusual linker features. Unless developers explicitely request it, we'll have to assume that they use their distro compiler by mistake. Make sure that using patched compilers is a conscious decision.

CCACHE toplevel bool Use ccache to speed up (re)compilation

Enables the use of ccache for faster builds.

Requires the ccache utility in your system $PATH.

For details see https://ccache.samba.org.

FMD_GENPARSER toplevel bool Generate flashmap descriptor parser using flex and bison

Enable this option if you are working on the flashmap descriptor parser and made changes to fmd_scanner.l or fmd_parser.y.

Otherwise, say N to use the provided pregenerated scanner/parser.

SCONFIG_GENPARSER toplevel bool Generate SCONFIG parser using flex and bison

Enable this option if you are working on the sconfig device tree parser and made changes to sconfig.l or sconfig.y.

Otherwise, say N to use the provided pregenerated scanner/parser.

USE_OPTION_TABLE toplevel bool Use CMOS for configuration values

Enable this option if coreboot shall read options from the "CMOS" NVRAM instead of using hard-coded values.

STATIC_OPTION_TABLE toplevel bool Load default configuration values into CMOS on each boot

Enable this option to reset "CMOS" NVRAM values to default on every boot. Use this if you want the NVRAM configuration to never be modified from its default values.

COMPRESS_RAMSTAGE toplevel bool Compress ramstage with LZMA

Compress ramstage to save memory in the flash image. Note that decompression might slow down booting if the boot flash is connected through a slow link (i.e. SPI).

COMPRESS_PRERAM_STAGES toplevel bool Compress romstage and verstage with LZ4

Compress romstage and (if it exists) verstage with LZ4 to save flash space and speed up boot, since the time for reading the image from SPI (and in the vboot case verifying it) is usually much greater than the time spent decompressing. Doesn't work for XIP stages (assume all ARCH_X86 for now) for obvious reasons.

INCLUDE_CONFIG_FILE toplevel bool Include the coreboot .config file into the ROM image

Include the .config file that was used to compile coreboot in the (CBFS) ROM image. This is useful if you want to know which options were used to build a specific coreboot.rom image.

Saying Y here will increase the image size by 2-3KB.

You can use the following command to easily list the options:

grep -a CONFIG_ coreboot.rom

Alternatively, you can also use cbfstool to print the image contents (including the raw 'config' item we're looking for).

Example:

$ cbfstool coreboot.rom print coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304, offset 0x0 Alignment: 64 bytes

Name Offset Type Size cmos_layout.bin 0x0 cmos layout 1159 fallback/romstage 0x4c0 stage 339756 fallback/ramstage 0x53440 stage 186664 fallback/payload 0x80dc0 payload 51526 config 0x8d740 raw 3324 (empty) 0x8e480 null 3610440

NO_XIP_EARLY_STAGES toplevel bool

Identify if early stages are eXecute-In-Place(XIP).

COLLECT_TIMESTAMPS toplevel bool Create a table of timestamps collected during boot

Make coreboot create a table of timer-ID/timer-value pairs to allow measuring time spent at different phases of the boot process.

USE_BLOBS toplevel bool Allow use of binary-only repository

This draws in the blobs repository, which contains binary files that might be required for some chipsets or boards. This flag ensures that a "Free" option remains available for users.

COVERAGE toplevel bool Code coverage support

Add code coverage support for coreboot. This will store code coverage information in CBMEM for extraction from user space. If unsure, say N.

RELOCATABLE_MODULES toplevel bool

If RELOCATABLE_MODULES is selected then support is enabled for building relocatable modules in the RAM stage. Those modules can be loaded anywhere and all the relocations are handled automatically.

RELOCATABLE_RAMSTAGE toplevel bool Build the ramstage to be relocatable in 32-bit address space.

The reloctable ramstage support allows for the ramstage to be built as a relocatable module. The stage loader can identify a place out of the OS way so that copying memory is unnecessary during an S3 wake. When selecting this option the romstage is responsible for determing a stack location to use for loading the ramstage.

CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM toplevel bool Cache the relocated ramstage outside of cbmem.

The relocated ramstage is saved in an area specified by the by the board and/or chipset.

NO_STAGE_CACHE toplevel bool

Do not save any component in stage cache for resume path. On resume, all components would be read back from CBFS again.

SKIP_MAX_REBOOT_CNT_CLEAR toplevel bool Do not clear reboot count after successful boot

Do not clear the reboot count immediately after successful boot. Set to allow the payload to control normal/fallback image recovery. Note that it is the responsibility of the payload to reset the normal boot bit to 1 after each successsful boot.

UPDATE_IMAGE toplevel bool Update existing coreboot.rom image

If this option is enabled, no new coreboot.rom file is created. Instead it is expected that there already is a suitable file for further processing. The bootblock will not be modified.

If unsure, select 'N'

GENERIC_GPIO_LIB toplevel bool

If enabled, compile the generic GPIO library. A "generic" GPIO implies configurability usually found on SoCs, particularly the ability to control internal pull resistors.

BOARD_ID_AUTO toplevel bool

Mainboards that can read a board ID from the hardware straps (ie. GPIO) select this configuration option.

BOARD_ID_MANUAL toplevel bool

If you want to maintain a board ID, but the hardware does not have straps to automatically determine the ID, you can say Y here and add a file named 'board_id' to CBFS. If you don't know what this is about, say N.

BOARD_ID_STRING toplevel string Board ID

This string is placed in the 'board_id' CBFS file for indicating board type.

RAM_CODE_SUPPORT toplevel bool

If enabled, coreboot discovers RAM configuration (value obtained by reading board straps) and stores it in coreboot table.

BOOTSPLASH_IMAGE toplevel bool Add a bootsplash image

Select this option if you have a bootsplash image that you would like to add to your ROM.

This will only add the image to the ROM. To actually run it check options under 'Display' section.

BOOTSPLASH_FILE toplevel string Bootsplash path and filename

The path and filename of the file to use as graphical bootsplash screen. The file format has to be jpg.

Menu: Mainboard
UART_FOR_CONSOLE mainboard/intel/mohonpeak int

The Mohon Peak board uses COM2 (2f8) for the serial console.

PAYLOAD_CONFIGFILE mainboard/intel/mohonpeak string

The Avoton/Rangeley chip does not allow devices to write into the 0xe000 segment. This means that USB/SATA devices will not work in SeaBIOS unless we put the SeaBIOS buffer area down in the 0x9000 segment.

UART_FOR_CONSOLE mainboard/intel/littleplains int

The Little Plains board uses COM2 (2f8) for the serial console.

PAYLOAD_CONFIGFILE mainboard/intel/littleplains string

The Avoton/Rangeley chip does not allow devices to write into the 0xe000 segment. This means that USB/SATA devices will not work in SeaBIOS unless we put the SeaBIOS buffer area down in the 0x9000 segment.

GALILEO_GEN2 mainboard/intel/galileo bool Board generation: GEN1 (n) or GEN2 (y)

The coreboot binary will configure only one generation of the Galileo board since coreboot can not determine the board generation at runtime. Select which generation of the Galileo that coreboot should initialize.

VGA_BIOS_FILE mainboard/intel/strago string

The C0 version of the video bios gets computed from this name so that they can both be added. Only the correct one for the system will be run.

VGA_BIOS_ID mainboard/intel/strago string

The VGA_BIOS_ID for the C0 version of the video bios is hardcoded in soc/intel/braswell/Makefile.inc as 8086,22b1

ENABLE_DP3_DAUGHTER_CARD_IN_J120 mainboard/amd/lamar bool Use J120 as an additional graphics port

The PCI Express slot at J120 can be configured as an additional DisplayPort connector using an adapter card from AMD or as a normal PCI Express (x4) slot.

By default, the connector is configured as a PCI Express (x4) slot.

Select this option to enable the slot for use with one of AMD's passive graphics port expander cards (only available from AMD).

MAINBOARD_PART_NUMBER mainboard/google/nyan_blaze string BCT boot media

Which boot media to configure the BCT for.

NYAN_BLAZE_BCT_CFG_SPI mainboard/google/nyan_blaze bool SPI

Configure the BCT for booting from SPI.

NYAN_BLAZE_BCT_CFG_EMMC mainboard/google/nyan_blaze bool eMMC

Configure the BCT for booting from eMMC.

BOOT_MEDIA_SPI_BUS mainboard/google/nyan_blaze int SPI bus with boot media ROM

Which SPI bus the boot media is connected to.

BOOT_MEDIA_SPI_CHIP_SELECT mainboard/google/nyan_blaze int Chip select for SPI boot media

Which chip select to use for boot media.

DISPLAY_SPD_DATA mainboard/google/cyan bool Display Memory Serial Presence Detect Data

When enabled displays the memory configuration data.

VGA_BIOS_FILE mainboard/google/cyan string

The C0 version of the video bios gets computed from this name so that they can both be added. Only the correct one for the system will be run.

VGA_BIOS_ID mainboard/google/cyan string

The VGA_BIOS_ID for the C0 version of the video bios is hardcoded in soc/intel/braswell/Makefile.inc as 8086,22b1

MAINBOARD_PART_NUMBER mainboard/google/rush_ryu string BCT boot media

Which boot media to configure the BCT for.

RUSH_RYU_BCT_CFG_SPI mainboard/google/rush_ryu bool SPI

Configure the BCT for booting from SPI.

RUSH_RYU_BCT_CFG_EMMC mainboard/google/rush_ryu bool eMMC

Configure the BCT for booting from eMMC.

BOOT_MEDIA_SPI_BUS mainboard/google/rush_ryu int SPI bus with boot media ROM

Which SPI bus the boot media is connected to.

BOOT_MEDIA_SPI_CHIP_SELECT mainboard/google/rush_ryu int Chip select for SPI boot media

Which chip select to use for boot media.

DRAM_SIZE_MB mainboard/google/smaug int BCT boot media

Which boot media to configure the BCT for.

SMAUG_BCT_CFG_SPI mainboard/google/smaug bool SPI

Configure the BCT for booting from SPI.

SMAUG_BCT_CFG_EMMC mainboard/google/smaug bool eMMC

Configure the BCT for booting from eMMC.

BOOT_MEDIA_SPI_BUS mainboard/google/smaug int SPI bus with boot media ROM

Which SPI bus the boot media is connected to.

BOOT_MEDIA_SPI_CHIP_SELECT mainboard/google/smaug int Chip select for SPI boot media

Which chip select to use for boot media.

DRAM_SIZE_MB mainboard/google/rush int BCT boot media

Which boot media to configure the BCT for.

RUSH_BCT_CFG_SPI mainboard/google/rush bool SPI

Configure the BCT for booting from SPI.

RUSH_BCT_CFG_EMMC mainboard/google/rush bool eMMC

Configure the BCT for booting from eMMC.

BOOT_MEDIA_SPI_BUS mainboard/google/rush int SPI bus with boot media ROM

Which SPI bus the boot media is connected to.

BOOT_MEDIA_SPI_CHIP_SELECT mainboard/google/rush int Chip select for SPI boot media

Which chip select to use for boot media.

MAINBOARD_PART_NUMBER mainboard/google/nyan_big string BCT boot media

Which boot media to configure the BCT for.

NYAN_BIG_BCT_CFG_SPI mainboard/google/nyan_big bool SPI

Configure the BCT for booting from SPI.

NYAN_BIG_BCT_CFG_EMMC mainboard/google/nyan_big bool eMMC

Configure the BCT for booting from eMMC.

BOOT_MEDIA_SPI_BUS mainboard/google/nyan_big int SPI bus with boot media ROM

Which SPI bus the boot media is connected to.

BOOT_MEDIA_SPI_CHIP_SELECT mainboard/google/nyan_big int Chip select for SPI boot media

Which chip select to use for boot media.

DRAM_SIZE_MB mainboard/google/foster int BCT boot media

Which boot media to configure the BCT for.

FOSTER_BCT_CFG_SPI mainboard/google/foster bool SPI

Configure the BCT for booting from SPI.

FOSTER_BCT_CFG_EMMC mainboard/google/foster bool eMMC

Configure the BCT for booting from eMMC.

BOOT_MEDIA_SPI_BUS mainboard/google/foster int SPI bus with boot media ROM

Which SPI bus the boot media is connected to.

BOOT_MEDIA_SPI_CHIP_SELECT mainboard/google/foster int Chip select for SPI boot media

Which chip select to use for boot media.

MAINBOARD_PART_NUMBER mainboard/google/nyan string BCT boot media

Which boot media to configure the BCT for.

NYAN_BCT_CFG_SPI mainboard/google/nyan bool SPI

Configure the BCT for booting from SPI.

NYAN_BCT_CFG_EMMC mainboard/google/nyan bool eMMC

Configure the BCT for booting from eMMC.

BOOT_MEDIA_SPI_BUS mainboard/google/nyan int SPI bus with boot media ROM

Which SPI bus the boot media is connected to.

BOOT_MEDIA_SPI_CHIP_SELECT mainboard/google/nyan int Chip select for SPI boot media

Which chip select to use for boot media.

UART_FOR_CONSOLE mainboard/adi/rcc-dff int

The Mohon Peak board uses COM2 (2f8) for the serial console.

PAYLOAD_CONFIGFILE mainboard/adi/rcc-dff string

The Avoton/Rangeley chip does not allow devices to write into the 0xe000 segment. This means that USB/SATA devices will not work in SeaBIOS unless we put the SeaBIOS buffer area down in the 0x9000 segment.

BOARD_ASUS_F2A85_M_DDR3_VOLT_135 mainboard/asus/f2a85-m bool 1.35V

Set DRR3 memory voltage to 1.35V

BOARD_ASUS_F2A85_M_DDR3_VOLT_150 mainboard/asus/f2a85-m bool 1.50V

Set DRR3 memory voltage to 1.50V

BOARD_ASUS_F2A85_M_DDR3_VOLT_165 mainboard/asus/f2a85-m bool 1.65V

Set DRR3 memory voltage to 1.65V

BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_135 mainboard/asus/f2a85-m_le bool 1.35V

Set DRR3 memory voltage to 1.35V

BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_150 mainboard/asus/f2a85-m_le bool 1.50V

Set DRR3 memory voltage to 1.50V

BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_165 mainboard/asus/f2a85-m_le bool 1.65V

Set DRR3 memory voltage to 1.65V

DRIVERS_PS2_KEYBOARD mainboard/purism/librem13 None

Default PS/2 Keyboard to enabled on this board.

DRIVERS_UART_8250IO mainboard/purism/librem13 None

This platform does not have any way to get standard serial output so disable it by default.

NO_POST mainboard/purism/librem13 int

This platform does not have any way to see POST codes so disable them by default.

(comment) was acquired by ADLINK
ONBOARD_UARTS_RS485 mainboard/lippert/spacerunner-lx bool Switch on-board serial ports to RS485

If selected, both on-board serial ports will operate in RS485 mode instead of RS232.

ONBOARD_IDE_SLAVE mainboard/lippert/spacerunner-lx bool Make on-board SSD act as Slave

If selected, the on-board SSD will act as IDE Slave instead of Master.

BOARD_OLD_REVISION mainboard/lippert/hurricane-lx bool Board is old pre-3.0 revision

Look on the bottom side for a number like 406-0001-30. The last 2 digits state the PCB revision (3.0 in this example). For 2.0 or older boards choose Y, for 3.0 and newer say N.

Old revision boards need a jumper shorting the power button to power on automatically. You may enable the button only after this jumper has been removed. New revision boards are not restricted in this way, and always have the power button enabled.

ONBOARD_UARTS_RS485 mainboard/lippert/hurricane-lx bool Switch on-board serial ports to RS485

If selected, both on-board serial ports will operate in RS485 mode instead of RS232.

ONBOARD_UARTS_RS485 mainboard/lippert/literunner-lx bool Switch on-board serial ports 1 & 2 to RS485

If selected, the first two on-board serial ports will operate in RS485 mode instead of RS232.

ONBOARD_IDE_SLAVE mainboard/lippert/literunner-lx bool Make on-board CF socket act as Slave

If selected, the on-board Compact Flash card socket will act as IDE Slave instead of Master.

ONBOARD_UARTS_RS485 mainboard/lippert/roadrunner-lx bool Switch on-board serial ports to RS485

If selected, both on-board serial ports will operate in RS485 mode instead of RS232.

Menu: On-Chip Device Power Down Control
Menu: Watchdog Timer setting
Menu: IDE controller setting
IDE_STANDARD_COMPATIBLE mainboard/dmp/vortex86ex bool Standard IDE Compatible

Built-in IDE controller PCI vendor/device ID is 17F3:1012, which is not recognized by some OSes.

This option can change IDE controller PCI vendor/device ID to other value for software compatibility.

IDE_COMPATIBLE_SELECTION mainboard/dmp/vortex86ex hex IDE Compatible Selection

IDE controller PCI vendor/device ID value setting.

Higher 16-bit is vendor ID, lower 16-bit is device ID.

Menu: GPIO setting
Menu: UART setting
Menu: LPT setting
(comment) see under vendor LiPPERT
BOARD_ROMSIZE_KB_65536 mainboard bool ROM chip size

Select the size of the ROM chip you intend to flash coreboot on.

The build system will take care of creating a coreboot.rom file of the matching size.

COREBOOT_ROMSIZE_KB_64 mainboard bool 64 KB

Choose this option if you have a 64 KB ROM chip.

COREBOOT_ROMSIZE_KB_128 mainboard bool 128 KB

Choose this option if you have a 128 KB ROM chip.

COREBOOT_ROMSIZE_KB_256 mainboard bool 256 KB

Choose this option if you have a 256 KB ROM chip.

COREBOOT_ROMSIZE_KB_512 mainboard bool 512 KB

Choose this option if you have a 512 KB ROM chip.

COREBOOT_ROMSIZE_KB_1024 mainboard bool 1024 KB (1 MB)

Choose this option if you have a 1024 KB (1 MB) ROM chip.

COREBOOT_ROMSIZE_KB_2048 mainboard bool 2048 KB (2 MB)

Choose this option if you have a 2048 KB (2 MB) ROM chip.

COREBOOT_ROMSIZE_KB_4096 mainboard bool 4096 KB (4 MB)

Choose this option if you have a 4096 KB (4 MB) ROM chip.

COREBOOT_ROMSIZE_KB_8192 mainboard bool 8192 KB (8 MB)

Choose this option if you have a 8192 KB (8 MB) ROM chip.

COREBOOT_ROMSIZE_KB_12288 mainboard bool 12288 KB (12 MB)

Choose this option if you have a 12288 KB (12 MB) ROM chip.

COREBOOT_ROMSIZE_KB_16384 mainboard bool 16384 KB (16 MB)

Choose this option if you have a 16384 KB (16 MB) ROM chip.

COREBOOT_ROMSIZE_KB_32768 mainboard bool 32768 KB (32 MB)

Choose this option if you have a 32768 KB (32 MB) ROM chip.

COREBOOT_ROMSIZE_KB_65536 mainboard bool 65536 KB (64 MB)

Choose this option if you have a 65536 KB (64 MB) ROM chip.

ENABLE_POWER_BUTTON mainboard bool Enable the power button

The selected mainboard can optionally have the power button tied to ground with a jumper so that the button appears to be constantly depressed. If this option is enabled and the jumper is installed then the board will turn on, but turn off again after a short timeout, usually 4 seconds.

Select Y here if you have removed the jumper and want to use an actual power button. Select N if you have the jumper installed.

CBFS_SIZE toplevel hex Size of CBFS filesystem in ROM

This is the part of the ROM actually managed by CBFS, located at the end of the ROM (passed through cbfstool -o) on x86 and at at the start of the ROM (passed through cbfstool -s) everywhere else. It defaults to span the whole ROM on all but Intel systems that use an Intel Firmware Descriptor. It can be overridden to make coreboot live alongside other components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE binaries.

FMDFILE toplevel string fmap description file in fmd format

The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE, but in some cases more complex setups are required. When an fmd is specified, it overrides the default format.

MAINBOARD_HAS_TPM2 toplevel bool

There is a TPM device installed on the mainboard, and it is compliant with version 2 TCG TPM specification. Could be connected over LPC, SPI or I2C.

CBFS_AUTOGEN_ATTRIBUTES toplevel bool

If this option is selected, every file in cbfs which has a constraint regarding position or alignment will get an additional file attribute which describes this constraint.

Menu: Chipset
(comment) SoC
MAINBOARD_DO_DSI_INIT soc/nvidia/tegra210 bool Use dsi graphics interface

Initialize dsi display

MAINBOARD_DO_SOR_INIT soc/nvidia/tegra210 bool Use dp graphics interface

Initialize dp display

CONSOLE_SERIAL_TEGRA210_UARTA soc/nvidia/tegra210 bool UARTA

Serial console on UART A.

CONSOLE_SERIAL_TEGRA210_UARTB soc/nvidia/tegra210 bool UARTB

Serial console on UART B.

CONSOLE_SERIAL_TEGRA210_UARTC soc/nvidia/tegra210 bool UARTC

Serial console on UART C.

CONSOLE_SERIAL_TEGRA210_UARTD soc/nvidia/tegra210 bool UARTD

Serial console on UART D.

CONSOLE_SERIAL_TEGRA210_UARTE soc/nvidia/tegra210 bool UARTE

Serial console on UART E.

CONSOLE_SERIAL_TEGRA210_UART_ADDRESS soc/nvidia/tegra210 hex

Map the UART names to the respective MMIO addres.

BOOTROM_SDRAM_INIT soc/nvidia/tegra210 bool SoC BootROM does SDRAM init with full BCT

Use during Foster LPDDR4 bringup.

TRUSTZONE_CARVEOUT_SIZE_MB soc/nvidia/tegra210 hex Size of Trust Zone region

Size of Trust Zone area in MiB to reserve in memory map.

TTB_SIZE_MB soc/nvidia/tegra210 hex Size of TTB

Maximum size of Translation Table Buffer in MiB.

SEC_COMPONENT_SIZE_MB soc/nvidia/tegra210 hex Size of resident EL3 components

Maximum size of resident EL3 components in MiB including BL31 and Secure OS.

HAVE_MTC soc/nvidia/tegra210 bool Add external Memory controller Training Code binary

Select this option to add emc training firmware

MTC_FILE soc/nvidia/tegra210 string tegra mtc firmware filename

The filename of the mtc firmware

MTC_DIRECTORY soc/nvidia/tegra210 string Directory where MTC firmware file is located

Path to directory where MTC firmware file is located.

MTC_ADDRESS soc/nvidia/tegra210 hex

The DRAM location where MTC firmware to be loaded in. This location needs to be consistent with the location defined in tegra_mtc.ld

MAINBOARD_DO_DSI_INIT soc/nvidia/tegra132 bool Use dsi graphics interface

Initialize dsi display

MAINBOARD_DO_SOR_INIT soc/nvidia/tegra132 bool Use dp graphics interface

Initialize dp display

MTS_DIRECTORY soc/nvidia/tegra132 string Directory where MTS microcode files are located

Path to directory where MTS microcode files are located.

TRUSTZONE_CARVEOUT_SIZE_MB soc/nvidia/tegra132 hex Size of Trust Zone region

Size of Trust Zone area in MiB to reserve in memory map.

BOOTROM_SDRAM_INIT soc/nvidia/tegra132 bool SoC BootROM does SDRAM init with full BCT

Use during Ryu LPDDR3 bringup

SOC_INTEL_FSP_BAYTRAIL soc/intel/fsp_baytrail bool

Bay Trail I part support using the Intel FSP.

SMM_TSEG_SIZE soc/intel/fsp_baytrail hex

This is set by the FSP

VGA_BIOS_ID soc/intel/fsp_baytrail string

This is the default PCI ID for the Bay Trail graphics devices. This string names the vbios ROM in cbfs.

ENABLE_BUILTIN_COM1 soc/intel/fsp_baytrail bool Enable built-in legacy Serial Port

The Baytrail SOC has one legacy serial port. Choose this option to configure the pads and enable it. This serial port can be used for the debug console.

FSP_BAYTRAIL_GFX_INIT soc/intel/fsp_baytrail bool

Enabling this option will activate graphics init code. With this init, the graphic power gate registers will be initialized before VBIOS is executed.

FSP_FILE soc/intel/fsp_baytrail/fsp string

The path and filename of the Intel FSP binary for this platform.

FSP_LOC soc/intel/fsp_baytrail/fsp hex

The location in CBFS that the FSP is located. This must match the value that is set in the FSP binary. If the FSP needs to be moved, rebase the FSP with Intel's BCT (tool).

The Bay Trail FSP is built with a preferred base address of 0xFFFC0000.

HAVE_CMC soc/intel/sch bool Add a CMC state machine binary

Select this option to add a CMC state machine binary to the resulting coreboot image.

Note: Without this binary coreboot will not work

CMC_FILE soc/intel/sch string Intel CMC path and filename

The path and filename of the file to use as CMC state machine binary.

SOC_INTEL_BRASWELL soc/intel/braswell bool

Braswell M/D part support.

DCACHE_RAM_SIZE soc/intel/braswell hex Temporary RAM Size

The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2.

DCACHE_RAM_ROMSTAGE_STACK_SIZE soc/intel/braswell hex

The amount of anticipated stack usage from the data cache during pre-ram rom stage execution.

RESET_ON_INVALID_RAMSTAGE_CACHE soc/intel/braswell bool Reset the system on S3 wake when ramstage cache invalid.

The haswell romstage code caches the loaded ramstage program in SMM space. On S3 wake the romstage will copy over a fresh ramstage that was cached in the SMM space. This option determines the action to take when the ramstage cache is invalid. If selected the system will reset otherwise the ramstage will be reloaded from cbfs.

ENABLE_BUILTIN_COM1 soc/intel/braswell bool Enable builtin COM1 Serial Port

The PMC has a legacy COM1 serial port. Choose this option to configure the pads and enable it. This serial port can be used for the debug console.

SOC_INTEL_APOLLOLAKE soc/intel/apollolake bool

Intel Apollolake support

TPM_ON_FAST_SPI soc/intel/apollolake bool

TPM part is conntected on Fast SPI interface, but the LPC MMIO TPM transactions are decoded and serialized over the SPI interface.

DCACHE_RAM_SIZE soc/intel/apollolake hex Length in bytes of cache-as-RAM

The size of the cache-as-ram region required during bootblock and/or romstage.

DCACHE_BSP_STACK_SIZE soc/intel/apollolake hex

The amount of anticipated stack usage in CAR by bootblock and other stages.

ROMSTAGE_ADDR soc/intel/apollolake hex

The base address (in CAR) where romstage should be linked

VERSTAGE_ADDR soc/intel/apollolake hex

The base address (in CAR) where verstage should be linked

FSP_M_ADDR soc/intel/apollolake hex

The address FSP-M will be relocated to during build time

NEED_LBP2 soc/intel/apollolake bool Write contents for logical boot partition 2.

Write the contents from a file into the logical boot partition 2 region defined by LBP2_FMAP_NAME.

LBP2_FMAP_NAME soc/intel/apollolake string Name of FMAP region to put logical boot partition 2

Name of FMAP region to write logical boot partition 2 data.

LBP2_FILE_NAME soc/intel/apollolake string Path of file to write to logical boot partition 2 region

Name of file to store in the logical boot partition 2 region.

NEED_IFWI soc/intel/apollolake bool Write content into IFWI region

Write the content from a file into IFWI region defined by IFWI_FMAP_NAME.

IFWI_FMAP_NAME soc/intel/apollolake string Name of FMAP region to pull IFWI into

Name of FMAP region to write IFWI.

IFWI_FILE_NAME soc/intel/apollolake string Path of file to write to IFWI region

Name of file to store in the IFWI region.

NHLT_DMIC_2CH_16B soc/intel/apollolake bool

Include DSP firmware settings for 2 channel 16B DMIC array.

NHLT_MAX98357 soc/intel/apollolake bool

Include DSP firmware settings for headset codec.

NHLT_DA7219 soc/intel/apollolake bool

Include DSP firmware settings for headset codec.

SOC_INTEL_BAYTRAIL soc/intel/baytrail bool

Bay Trail M/D part support.

HAVE_MRC soc/intel/baytrail bool Add a Memory Reference Code binary

Select this option to add a blob containing memory reference code. Note: Without this binary coreboot will not work

MRC_FILE soc/intel/baytrail string Intel memory refeference code path and filename

The path and filename of the file to use as System Agent binary. Note that this points to the sandybridge binary file which is will not work, but it serves its purpose to do builds.

DCACHE_RAM_SIZE soc/intel/baytrail hex

The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2.

DCACHE_RAM_MRC_VAR_SIZE soc/intel/baytrail hex

The amount of cache-as-ram region required by the reference code.

DCACHE_RAM_ROMSTAGE_STACK_SIZE soc/intel/baytrail hex

The amount of anticipated stack usage from the data cache during pre-RAM ROM stage execution.

RESET_ON_INVALID_RAMSTAGE_CACHE soc/intel/baytrail bool Reset the system on S3 wake when ramstage cache invalid.

The baytrail romstage code caches the loaded ramstage program in SMM space. On S3 wake the romstage will copy over a fresh ramstage that was cached in the SMM space. This option determines the action to take when the ramstage cache is invalid. If selected the system will reset otherwise the ramstage will be reloaded from cbfs.

ENABLE_BUILTIN_COM1 soc/intel/baytrail bool Enable builtin COM1 Serial Port

The PMC has a legacy COM1 serial port. Choose this option to configure the pads and enable it. This serial port can be used for the debug console.

HAVE_REFCODE_BLOB soc/intel/baytrail bool An external reference code blob should be put into cbfs.

The reference code blob will be placed into cbfs.

REFCODE_BLOB_FILE soc/intel/baytrail string Path and filename to reference code blob.

The path and filename to the file to be added to cbfs.

SOC_INTEL_QUARK soc/intel/quark bool

Intel Quark support

ENABLE_BUILTIN_HSUART0 soc/intel/quark bool Enable built-in HSUART0

The Quark SoC has two HSUART. Choose this option to configure the pads and enable HSUART0, which can be used for the debug console.

ENABLE_BUILTIN_HSUART1 soc/intel/quark bool Enable built-in HSUART1

The Quark SoC has two HSUART. Choose this option to configure the pads and enable HSUART1, which can be used for the debug console.

TTYS0_BASE soc/intel/quark hex HSUART Base Address

Memory mapped MMIO of HSUART.

ENABLE_DEBUG_LED soc/intel/quark bool

Enable the use of the SD LED for early debugging before serial output is available. Setting this LED indicates that control has reached the desired check point.

ENABLE_DEBUG_LED_ESRAM soc/intel/quark bool SD LED indicates ESRAM initialized

Indicate that ESRAM has been successfully initialized.

ENABLE_DEBUG_LED_FINDFSP soc/intel/quark bool SD LED indicates fsp.bin file was found

Indicate that fsp.bin was found.

ENABLE_DEBUG_LED_TEMPRAMINIT soc/intel/quark bool SD LED indicates TempRamInit was successful

Indicate that TempRamInit was successful.

CBFS_SIZE soc/intel/quark hex

Specify the size of the coreboot file system in the read-only (recovery) portion of the flash part. On Quark systems the firmware image stores more than just coreboot, including: - The chipset microcode (RMU) binary file located at 0xFFF00000 - Intel Trusted Execution Engine firmware

ADD_FSP_RAW_BIN soc/intel/quark bool Add the Intel FSP binary to the flash image without relocation

Select this option to add an Intel FSP binary to the resulting coreboot image.

Note: Without this binary, coreboot builds relying on the FSP will not boot

FSP_FILE soc/intel/quark string Intel FSP binary path and filename

The path and filename of the Intel FSP binary for this platform.

FSP_IMAGE_ID_STRING soc/intel/quark string 8 byte platform string identifying the FSP platform

8 ASCII character byte signature string that will help match the FSP binary to a supported hardware configuration.

FSP_LOC soc/intel/quark hex

The location in CBFS that the FSP is located. This must match the value that is set in the FSP binary. If the FSP needs to be moved, rebase the FSP with Intel's BCT (tool).

FSP_ESRAM_LOC soc/intel/quark hex

The location in ESRAM where a copy of the FSP binary is placed.

RELOCATE_FSP_INTO_DRAM soc/intel/quark bool Relocate FSP into DRAM

Relocate the FSP binary into DRAM before the call to SiliconInit.

ADD_RMU_FILE soc/intel/quark bool Should the RMU binary be added to the flash image?

The RMU file is required to get the chip out of reset.

RMU_FILE soc/intel/quark string

The path and filename of the Intel Quark RMU binary.

RMU_LOC soc/intel/quark hex

The location in CBFS that the RMU is located. It must match the strap-determined base address.

SOC_INTEL_COMMON soc/intel/common bool

common code for Intel SOCs

SOC_INTEL_COMMON_LPSS_I2C soc/intel/common bool

This driver supports the Intel Low Power Subsystem (LPSS) I2C controllers that are based on Synopsys DesignWare IP.

SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ soc/intel/common int

The clock speed that the I2C controller is running at, in MHz. No default is set here as this is an SOC-specific value and must be provided by the SOC when it selects this driver.

SOC_SETS_MTRRS soc/intel/common bool

The SoC needs uses different access methods for reading and writing the MTRRs. Use SoC specific routines to handle the MTRR access.

MMA soc/intel/common bool enable MMA (Memory Margin Analysis) support

Set this option to y to enable MMA (Memory Margin Analysis) support

ADD_VBT_DATA_FILE soc/intel/common bool Add a Video Bios Table (VBT) binary to CBFS

Add a VBT file data file to CBFS. The VBT describes the integrated GPU and connections, and is needed by FSP in order to initialize the display.

VBT_FILE soc/intel/common string VBT binary path and filename

The path and filename of the VBT binary.

SOC_INTEL_FSP_BROADWELL_DE soc/intel/fsp_broadwell_de bool

Broadwell-DE support using the Intel FSP.

INTEGRATED_UART soc/intel/fsp_broadwell_de bool Integrated UART ports

Use Broadwell-DE Integrated UART ports @3F8h and 2F8h.

DRIVERS_UART_8250IO soc/intel/fsp_broadwell_de bool Serial port on SuperIO (Broadwell-DE's UART ports unselected)

Select to choose SuperIO's serial port for console output. CANNOT select if intend to use SoC integrated serial ports.

FSP_FILE soc/intel/fsp_broadwell_de/fsp string

The path and filename of the Intel FSP binary for this platform.

FSP_LOC soc/intel/fsp_broadwell_de/fsp hex

The location in CBFS that the FSP is located. This must match the value that is set in the FSP binary. If the FSP needs to be moved, rebase the FSP with Intel's BCT (tool).

The Broadwell-DE FSP is built with a preferred base address of 0xffeb0000.

FSP_MEMORY_DOWN soc/intel/fsp_broadwell_de/fsp bool Enable Memory Down

Load SPD data from ROM instead of trying to read from SMBus.

If the platform has DIMM sockets, say N. If memory is down, say Y and supply the appropriate SPD data for each Channel/DIMM.

FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT soc/intel/fsp_broadwell_de/fsp bool Channel 0, DIMM 0 Present

Select Y if Channel 0, DIMM 0 is present.

FSP_MEMORY_DOWN_CH0DIMM0_SPD_FILE soc/intel/fsp_broadwell_de/fsp string Channel 0, DIMM 0 SPD File

Path to the file which contains the SPD data for Channel 0, DIMM 0.

FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT soc/intel/fsp_broadwell_de/fsp bool Channel 0, DIMM 1 Present

Select Y if Channel 0, DIMM 1 is present.

FSP_MEMORY_DOWN_CH0DIMM1_SPD_FILE soc/intel/fsp_broadwell_de/fsp string Channel 0, DIMM 1 SPD File

Path to the file which contains the SPD data for Channel 0, DIMM 1.

FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT soc/intel/fsp_broadwell_de/fsp bool Channel 1, DIMM 0 Present

Select Y if Channel 1, DIMM 0 is present.

FSP_MEMORY_DOWN_CH1DIMM0_SPD_FILE soc/intel/fsp_broadwell_de/fsp string Channel 1, DIMM 0 SPD File

Path to the file which contains the SPD data for Channel 1, DIMM 0.

FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT soc/intel/fsp_broadwell_de/fsp bool Channel 1, DIMM 1 Present

Select Y if Channel 1, DIMM 1 is present.

FSP_MEMORY_DOWN_CH1DIMM1_SPD_FILE soc/intel/fsp_broadwell_de/fsp string Channel 1, DIMM 1 SPD File

Path to the file which contains the SPD data for Channel 1, DIMM 1.

FSP_HYPERTHREADING soc/intel/fsp_broadwell_de/fsp bool Enable Hyper-Threading

Enable Intel(r) Hyper-Threading Technology for the Broadwell-DE SoC.

SOC_INTEL_BROADWELL soc/intel/broadwell bool

Intel Broadwell and Haswell ULT support.

DCACHE_RAM_SIZE soc/intel/broadwell hex

The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2.

DCACHE_RAM_MRC_VAR_SIZE soc/intel/broadwell hex

The amount of cache-as-ram region required by the reference code.

DCACHE_RAM_ROMSTAGE_STACK_SIZE soc/intel/broadwell hex

The amount of anticipated stack usage from the data cache during pre-ram rom stage execution.

HAVE_MRC soc/intel/broadwell bool Add a Memory Reference Code binary

Select this option to add a Memory Reference Code binary to the resulting coreboot image.

Note: Without this binary coreboot will not work

MRC_FILE soc/intel/broadwell string Intel Memory Reference Code path and filename

The filename of the file to use as Memory Reference Code binary.

PRE_GRAPHICS_DELAY soc/intel/broadwell int Graphics initialization delay in ms

On some systems, coreboot boots so fast that connected monitors (mostly TVs) won't be able to wake up fast enough to talk to the VBIOS. On those systems we need to wait for a bit before executing the VBIOS.

RESET_ON_INVALID_RAMSTAGE_CACHE soc/intel/broadwell bool Reset the system on S3 wake when ramstage cache invalid.

The romstage code caches the loaded ramstage program in SMM space. On S3 wake the romstage will copy over a fresh ramstage that was cached in the SMM space. This option determines the action to take when the ramstage cache is invalid. If selected the system will reset otherwise the ramstage will be reloaded from cbfs.

SERIRQ_CONTINUOUS_MODE soc/intel/broadwell bool

If you set this option to y, the serial IRQ machine will be operated in continuous mode.

HAVE_REFCODE_BLOB soc/intel/broadwell bool An external reference code blob should be put into cbfs.

The reference code blob will be placed into cbfs.

REFCODE_BLOB_FILE soc/intel/broadwell string Path and filename to reference code blob.

The path and filename to the file to be added to cbfs.

SOC_INTEL_SKYLAKE soc/intel/skylake bool

Intel Skylake support

DCACHE_RAM_SIZE soc/intel/skylake hex Length in bytes of cache-as-RAM

The size of the cache-as-ram region required during bootblock and/or romstage.

EXCLUDE_NATIVE_SD_INTERFACE soc/intel/skylake bool

If you set this option to n, will not use native SD controller.

MONOTONIC_TIMER_MSR soc/intel/skylake hex

Provide a monotonic timer using the 24MHz MSR counter.

PRE_GRAPHICS_DELAY soc/intel/skylake int Graphics initialization delay in ms

On some systems, coreboot boots so fast that connected monitors (mostly TVs) won't be able to wake up fast enough to talk to the VBIOS. On those systems we need to wait for a bit before executing the VBIOS.

SERIRQ_CONTINUOUS_MODE soc/intel/skylake bool

If you set this option to y, the serial IRQ machine will be operated in continuous mode.

NHLT_DMIC_2CH soc/intel/skylake bool

Include DSP firmware settings for 2 channel DMIC array.

NHLT_DMIC_4CH soc/intel/skylake bool

Include DSP firmware settings for 4 channel DMIC array.

NHLT_NAU88L25 soc/intel/skylake bool

Include DSP firmware settings for nau88l25 headset codec.

NHLT_MAX98357 soc/intel/skylake bool

Include DSP firmware settings for max98357 amplifier.

NHLT_SSM4567 soc/intel/skylake bool

Include DSP firmware settings for ssm4567 smart amplifier.

SKIP_FSP_CAR soc/intel/skylake bool Skip cache as RAM setup in FSP

Skip Cache as RAM setup in FSP.

CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE soc/broadcom/cygnus bool Enable DDR auto self-refresh

Warning: M0 expects that auto self-refresh is enabled. Modify with caution.


DEBUG_DRAM soc/mediatek/mt8173 bool Output verbose DRAM related debug message

This option enables additional DRAM related debug messages.

DEBUG_I2C soc/mediatek/mt8173 bool Output verbose I2C related debug message

This option enables I2C related debug message.

DEBUG_PMIC soc/mediatek/mt8173 bool Output verbose PMIC related debug message

This option enables PMIC related debug message.

DEBUG_PMIC_WRAP soc/mediatek/mt8173 bool Output verbose PMIC WRAP related debug message

This option enables PMIC WRAP related debug message.

BOOTBLOCK_CPU_INIT soc/marvell/armada38x string

CPU/SoC-specific bootblock code. This is useful if the bootblock must load microcode or copy data from ROM before searching for the bootblock.

IPQ_QFN_PART soc/qualcomm/ipq40xx bool

Is the SoC a QFN part (as opposed to a BGA part)

SBL_ELF soc/qualcomm/ipq40xx string file name of the QCA SBL ELF

The path and filename of the binary blob containing ipq40xx early initialization code, as supplied by the vendor.

SBL_UTIL_PATH soc/qualcomm/ipq40xx string Path for utils to combine SBL_ELF and bootblock

Path for utils to combine SBL_ELF and bootblock

SBL_BLOB soc/qualcomm/ipq806x string file name of the Qualcomm SBL blob

The path and filename of the binary blob containing ipq806x early initialization code, as supplied by the vendor.

(comment) CPU
RESET_ON_INVALID_RAMSTAGE_CACHE cpu/intel/haswell bool Reset the system on S3 wake when ramstage cache invalid.

The haswell romstage code caches the loaded ramstage program in SMM space. On S3 wake the romstage will copy over a fresh ramstage that was cached in the SMM space. This option determines the action to take when the ramstage cache is invalid. If selected the system will reset otherwise the ramstage will be reloaded from cbfs.

CPU_INTEL_FIRMWARE_INTERFACE_TABLE cpu/intel/fit None

This option selects building a Firmware Interface Table (FIT).

CPU_INTEL_NUM_FIT_ENTRIES cpu/intel/fit int

This option selects the number of empty entries in the FIT table.

CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED cpu/intel/turbo None

This option indicates that the turbo mode setting is not package scoped. i.e. enable_turbo() needs to be called on not just the bsp

GEODE_VSA_FILE cpu/amd/geode_gx2 bool Add a VSA image

Select this option if you have an AMD Geode GX2 vsa that you would like to add to your ROM.

You will be able to specify the location and file name of the image later.

VSA_FILENAME cpu/amd/geode_gx2 string AMD Geode GX2 VSA path and filename

The path and filename of the file to use as VSA.

GEODE_VSA_FILE cpu/amd/geode_lx bool Add a VSA image

Select this option if you have an AMD Geode LX vsa that you would like to add to your ROM.

You will be able to specify the location and file name of the image later.

VSA_FILENAME cpu/amd/geode_lx string AMD Geode LX VSA path and filename

The path and filename of the file to use as VSA.

XIP_ROM_SIZE cpu/amd/agesa hex

Overwride the default write through caching size as 1M Bytes. On some AMD platforms, one socket supports 2 or more kinds of processor family, compiling several CPU families agesa code will increase the romstage size. In order to execute romstage in place on the flash ROM, more space is required to be set as write through caching.

REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL cpu/amd/agesa/family10 bool Redirect AGESA IDS_HDT_CONSOLE to serial console

This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console.

Warning: Only enable this option when debuging or tracing AMD AGESA code.

CPU_AMD_SOCKET_G34 cpu/amd/agesa/family15 bool

AMD G34 Socket

CPU_AMD_SOCKET_C32 cpu/amd/agesa/family15 bool

AMD C32 Socket

CPU_AMD_SOCKET_AM3R2 cpu/amd/agesa/family15 bool

AMD AM3r2 Socket

REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL cpu/amd/agesa/family15 bool Redirect AGESA IDS_HDT_CONSOLE to serial console

This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console.

Warning: Only enable this option when debuging or tracing AMD AGESA code.

FORCE_AM1_SOCKET_SUPPORT cpu/amd/agesa/family16kb bool

Force AGESA to ignore package type mismatch between CPU and northbridge in memory code. This enables Socket AM1 support with current AGESA version for Kabini platform. Enable this option only if you have Socket AM1 board. Note that the AGESA release shipped with coreboot does not officially support the AM1 socket. Selecting this option might damage your hardware.

XIP_ROM_SIZE cpu/amd/pi hex

Overwride the default write through caching size as 1M Bytes. On some AMD platforms, one socket supports 2 or more kinds of processor family, compiling several CPU families agesa code will increase the romstage size. In order to execute romstage in place on the flash ROM, more space is required to be set as write through caching.

PARALLEL_MP cpu/x86 bool

This option uses common MP infrastructure for bringing up APs in parallel. It additionally provides a more flexible mechanism for sequencing the steps of bringing up the APs.


LAPIC_MONOTONIC_TIMER cpu/x86 bool

Expose monotonic time using the local apic.

TSC_CONSTANT_RATE cpu/x86 bool

This option asserts that the TSC ticks at a known constant rate. Therefore, no TSC calibration is required.

TSC_MONOTONIC_TIMER cpu/x86 bool

Expose monotonic time using the TSC.

TSC_SYNC_LFENCE cpu/x86 bool

The CPU driver should select this if the CPU needs to execute an lfence instruction in order to synchronize rdtsc. This is true for all modern AMD CPUs.

TSC_SYNC_MFENCE cpu/x86 bool

The CPU driver should select this if the CPU needs to execute an mfence instruction in order to synchronize rdtsc. This is true for all modern Intel CPUs.

NO_FIXED_XIP_ROM_SIZE cpu/x86 bool

The XIP_ROM_SIZE Kconfig variable is used globally on x86 with the assumption that all chipsets utilize this value. For the chipsets which do not use the variable it can lead to unnecessary alignment constraints in cbfs for romstage. Therefore, allow those chipsets a path to not be burdened.

SMM_MODULE_HEAP_SIZE cpu/x86 hex

This option determines the size of the heap within the SMM handler modules.

SERIALIZED_SMM_INITIALIZATION cpu/x86 bool

On some CPUs, there is a race condition in SMM. This can occur when both hyperthreads change SMM state variables in parallel without coordination. Setting this option serializes the SMM initialization to avoid an ugly hang in the boot process at the cost of a slightly longer boot time.

X86_AMD_FIXED_MTRRS cpu/x86 bool

This option informs the MTRR code to use the RdMem and WrMem fields in the fixed MTRR MSRs.

PLATFORM_USES_FSP1_0 cpu/x86 bool

Selected for Intel processors/platform combinations that use the Intel Firmware Support Package (FSP) 1.0 for initialization.

MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING cpu/x86 bool

On certain platforms a boot speed gain can be realized if mirroring the payload data stored in non-volatile storage. On x86 systems the payload would typically live in a memory-mapped SPI part. Copying the SPI contents to RAM before performing the load can speed up the boot process.

BOOT_MEDIA_SPI_BUS cpu/x86 int

Most x86 systems which boot from SPI flash boot using bus 0.

SMP cpu bool

This option is used to enable certain functions to make coreboot work correctly on symmetric multi processor (SMP) systems.

AP_SIPI_VECTOR cpu hex

This must equal address of ap_sipi_vector from bootblock build.

MMX cpu bool

Select MMX in your socket or model Kconfig if your CPU has MMX streaming SIMD instructions. ROMCC can build more efficient code if it can spill to MMX registers.

SSE cpu bool

Select SSE in your socket or model Kconfig if your CPU has SSE streaming SIMD instructions. ROMCC can build more efficient code if it can spill to SSE (aka XMM) registers.

SSE2 cpu bool

Select SSE2 in your socket or model Kconfig if your CPU has SSE2 streaming SIMD instructions. Some parts of coreboot can be built with more efficient code if SSE2 instructions are available.

USES_MICROCODE_HEADER_FILES cpu bool

This is selected by a board or chipset to set the default for the microcode source choice to a list of external microcode headers

CPU_MICROCODE_CBFS_GENERATE cpu bool Generate from tree

Select this option if you want microcode updates to be assembled when building coreboot and included in the final image as a separate CBFS file. Microcode will not be hard-coded into ramstage.

The microcode file may be removed from the ROM image at a later time with cbfstool, if desired.

If unsure, select this option.

CPU_MICROCODE_CBFS_EXTERNAL_HEADER cpu bool Include external microcode header files

Select this option if you want to include external c header files containing the CPU microcode. This will be included as a separate file in CBFS.

A word of caution: only select this option if you are sure the microcode that you have is newer than the microcode shipping with coreboot.

The microcode file may be removed from the ROM image at a later time with cbfstool, if desired.

If unsure, select "Generate from tree"

CPU_MICROCODE_CBFS_NONE cpu bool Do not include microcode updates

Select this option if you do not want CPU microcode included in CBFS. Note that for some CPUs, the microcode is hard-coded into the source tree and is not loaded from CBFS. In this case, microcode will still be updated. There is a push to move all microcode to CBFS, but this change is not implemented for all CPUs.

This option currently applies to: - Intel SandyBridge/IvyBridge - VIA Nano

Microcode may be added to the ROM image at a later time with cbfstool, if desired.

If unsure, select "Generate from tree"

The GOOD: Microcode updates intend to solve issues that have been discovered after CPU production. The expected effect is that systems work as intended with the updated microcode, but we have also seen cases where issues were solved by not applying microcode updates.

The BAD: Note that some operating system include these same microcode patches, so you may need to also disable microcode updates in your operating system for this option to have an effect.

The UGLY: A word of CAUTION: some CPUs depend on microcode updates to function correctly. Not updating the microcode may leave the CPU operating at less than optimal performance, or may cause outright hangups. There are CPUs where coreboot cannot properly initialize the CPU without microcode updates For example, if running with the factory microcode, some Intel SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs will hang when changing the frequency.

Make sure you have a way of flashing the ROM externally before selecting this option.

CPU_MICROCODE_MULTIPLE_FILES cpu bool

Select this option to install separate microcode container files into CBFS instead of using the traditional monolithic microcode file format.

CPU_MICROCODE_HEADER_FILES cpu string List of space separated microcode header files with the path

A list of one or more microcode header files with path from the coreboot directory. These should be separated by spaces.

(comment) Northbridge
OVERRIDE_CLOCK_DISABLE northbridge/intel/i945 bool

Usually system firmware turns off system memory clock signals to unused SO-DIMM slots to reduce EMI and power consumption. However, some boards do not like unused clock signals to be disabled.

MAXIMUM_SUPPORTED_FREQUENCY northbridge/intel/i945 int

If non-zero, this designates the maximum DDR frequency the board supports, despite what the chipset should be capable of.

CHECK_SLFRCS_ON_RESUME northbridge/intel/i945 int

On some boards it may be neccessary to hard reset early during resume from S3 if the SLFRCS register indicates that a memory channel is not guaranteed to be in self-refresh. On other boards the check always creates a false positive, effectively making it impossible to resume.

USE_NATIVE_RAMINIT northbridge/intel/sandybridge bool Use native raminit

Select if you want to use coreboot implementation of raminit rather than System Agent/MRC.bin. You should answer Y.

MRC_FILE northbridge/intel/sandybridge string Intel System Agent path and filename

The path and filename of the file to use as System Agent binary.

DCACHE_RAM_SIZE northbridge/intel/haswell hex

The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2.

DCACHE_RAM_MRC_VAR_SIZE northbridge/intel/haswell hex

The amount of cache-as-ram region required by the reference code.

DCACHE_RAM_ROMSTAGE_STACK_SIZE northbridge/intel/haswell hex

The amount of anticipated stack usage from the data cache during pre-ram rom stage execution.

HAVE_MRC northbridge/intel/haswell bool Add a System Agent binary

Select this option to add a System Agent binary to the resulting coreboot image.

Note: Without this binary coreboot will not work

MRC_FILE northbridge/intel/haswell string Intel System Agent path and filename

The path and filename of the file to use as System Agent binary.

PRE_GRAPHICS_DELAY northbridge/intel/haswell int Graphics initialization delay in ms

On some systems, coreboot boots so fast that connected monitors (mostly TVs) won't be able to wake up fast enough to talk to the VBIOS. On those systems we need to wait for a bit before executing the VBIOS.

VGA_BIOS_ID northbridge/intel/fsp_sandybridge string

This is the default PCI ID for the sandybridge/ivybridge graphics devices. This string names the vbios ROM in cbfs. The following PCI IDs will be remapped to load this ROM: 0x80860102, 0x8086010a, 0x80860112, 0x80860116 0x80860122, 0x80860126, 0x80860166

FSP_FILE northbridge/intel/fsp_sandybridge/fsp string

The path and filename of the Intel FSP binary for this platform.

FSP_LOC northbridge/intel/fsp_sandybridge/fsp hex Intel FSP Binary location in CBFS

The location in CBFS that the FSP is located. This must match the value that is set in the FSP binary. If the FSP needs to be moved, rebase the FSP with the Intel's BCT (tool).

The Ivy Bridge Processor/Panther Point FSP is built with a preferred base address of 0xFFF80000

SDRAMPWR_4DIMM northbridge/intel/i440bx bool

This option affects how the SDRAMC register is programmed. Memory clock signals will not be routed properly if this option is set wrong.

If your board has 4 DIMM slots, you must use select this option, in your Kconfig file of the board. On boards with 3 DIMM slots, do _not_ select this option.

SET_TSEG_1MB northbridge/intel/fsp_rangeley bool 1 MB

Set the TSEG area to 1 MB.

SET_TSEG_2MB northbridge/intel/fsp_rangeley bool 2 MB

Set the TSEG area to 2 MB.

SET_TSEG_4MB northbridge/intel/fsp_rangeley bool 4 MB

Set the TSEG area to 4 MB.

SET_TSEG_8MB northbridge/intel/fsp_rangeley bool 8 MB

Set the TSEG area to 8 MB.

FSP_FILE northbridge/intel/fsp_rangeley/fsp string

The path and filename of the Intel FSP binary for this platform.

FSP_LOC northbridge/intel/fsp_rangeley/fsp hex

The location in CBFS that the FSP is located. This must match the value that is set in the FSP binary. If the FSP needs to be moved, rebase the FSP with Intel's BCT (tool).

The Rangeley FSP is built with a preferred base address of 0xFFF80000

VGA_BIOS_ID northbridge/amd/pi/00630F01 string

The default VGA BIOS PCI vendor/device ID should be set to the result of the map_oprom_vendev() function in northbridge.c.

VGA_BIOS_ID northbridge/amd/pi/00730F01 string

The default VGA BIOS PCI vendor/device ID should be set to the result of the map_oprom_vendev() function in northbridge.c.

VGA_BIOS_ID northbridge/amd/pi/00660F01 string

The default VGA BIOS PCI vendor/device ID should be set to the result of the map_oprom_vendev() function in northbridge.c.

REDIRECT_NBCIMX_TRACE_TO_SERIAL northbridge/amd/cimx/rd890 bool Redirect AMD Northbridge CIMX Trace to serial console

This Option allows you to redirect the AMD Northbridge CIMX Trace debug information to the serial console.

Warning: Only enable this option when debuging or tracing AMD CIMX code.

VGA_BIOS_ID northbridge/amd/agesa/family16kb string

The default VGA BIOS PCI vendor/device ID should be set to the result of the map_oprom_vendev() function in northbridge.c.

SVI_HIGH_FREQ northbridge/amd/amdfam10 bool

Select this for boards with a Voltage Regulator able to operate at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.

Menu: HyperTransport setup
SVI_HIGH_FREQ northbridge/amd/amdfam10 bool HyperTransport downlink width

This option sets the maximum permissible HyperTransport downlink width.

Use of this option will only limit the autodetected HT width. It will not (and cannot) increase the width beyond the autodetected limits.

This is primarily used to work around poorly designed or laid out HT traces on certain motherboards.

LIMIT_HT_DOWN_WIDTH_16 northbridge/amd/amdfam10 bool HyperTransport uplink width

This option sets the maximum permissible HyperTransport uplink width.

Use of this option will only limit the autodetected HT width. It will not (and cannot) increase the width beyond the autodetected limits.

This is primarily used to work around poorly designed or laid out HT traces on certain motherboards.

(comment) Southbridge
SERIRQ_CONTINUOUS_MODE southbridge/intel/ibexpeak bool

If you set this option to y, the serial IRQ machine will be operated in continuous mode.

INTEL_LYNXPOINT_LP southbridge/intel/lynxpoint bool

Set this option to y for Lynxpont LP (Haswell ULT).

SERIRQ_CONTINUOUS_MODE southbridge/intel/lynxpoint bool

If you set this option to y, the serial IRQ machine will be operated in continuous mode.

ME_MBP_CLEAR_LATE southbridge/intel/lynxpoint bool Defer wait for ME MBP Cleared

If you set this option to y, the Management Engine driver will defer waiting for the MBP Cleared indicator until the finalize step. This can speed up boot time if the ME takes a long time to indicate this status.

FINALIZE_USB_ROUTE_XHCI southbridge/intel/lynxpoint bool Route all ports to XHCI controller in finalize step

If you set this option to y, the USB ports will be routed to the XHCI controller during the finalize SMM callback.

SERIRQ_CONTINUOUS_MODE southbridge/intel/bd82x6x bool

If you set this option to y, the serial IRQ machine will be operated in continuous mode.

LOCK_SPI_ON_RESUME_RO southbridge/intel/bd82x6x bool Lock all flash ROM sections on S3 resume

If the flash ROM shall be protected against write accesses from the operating system (OS), the locking procedure has to be repeated after each resume from S3. Select this if you never want to update the flash ROM from within your OS. Notice: Even with this option, the write lock has still to be enabled on the normal boot path (e.g. by the payload).

LOCK_SPI_ON_RESUME_NO_ACCESS southbridge/intel/bd82x6x bool Lock and disable reads all flash ROM sections on S3 resume

If the flash ROM shall be protected against all accesses from the operating system (OS), the locking procedure has to be repeated after each resume from S3. Select this if you never want to update the flash ROM from within your OS. Notice: Even with this option, the lock has still to be enabled on the normal boot path (e.g. by the payload).

SERIRQ_CONTINUOUS_MODE southbridge/intel/fsp_bd82x6x bool

If you set this option to y, the serial IRQ machine will be operated in continuous mode.

SERIRQ_CONTINUOUS_MODE southbridge/intel/fsp_rangeley bool

If you set this option to y, the serial IRQ machine will be operated in continuous mode.

IFD_BIN_PATH southbridge/intel/fsp_rangeley string

The path and filename to the descriptor.bin file.

SERIRQ_CONTINUOUS_MODE southbridge/intel/fsp_i89xx bool

If you set this option to y, the serial IRQ machine will be operated in continuous mode.

HUDSON_XHCI_ENABLE southbridge/amd/pi/hudson bool Enable Hudson XHCI Controller

The XHCI controller must be enabled and the XHCI firmware must be added in order to have USB 3.0 support configured by coreboot. The OS will be responsible for enabling the XHCI controller if the the XHCI firmware is available but the XHCI controller is not enabled by coreboot.

HUDSON_XHCI_FWM southbridge/amd/pi/hudson bool Add xhci firmware

Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0

HUDSON_IMC_FWM southbridge/amd/pi/hudson bool Add IMC firmware

Add Hudson 2/3/4 IMC Firmware to support the onboard fan control

HUDSON_GEC_FWM southbridge/amd/pi/hudson bool

Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC. Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.

HUDSON_FWM_POSITION southbridge/amd/pi/hudson hex Hudson Firmware ROM Position

Hudson requires the firmware MUST be located at a specific address (ROM start address + 0x20000), otherwise xhci host Controller can not find or load the xhci firmware.

The firmware start address is dependent on the ROM chip size. The default offset is 0x20000 from the ROM start address, namely 0xFFF20000 if flash chip size is 1M 0xFFE20000 if flash chip size is 2M 0xFFC20000 if flash chip size is 4M 0xFF820000 if flash chip size is 8M 0xFF020000 if flash chip size is 16M

HUDSON_SATA_MODE southbridge/amd/pi/hudson int SATA Mode

Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. The default is NATIVE. 0: NATIVE mode does not require a ROM. 1: RAID mode must have the two ROM files. 2: AHCI may work with or without AHCI ROM. It depends on the payload support. For example, seabios does not require the AHCI ROM. 3: LEGACY IDE 4: IDE to AHCI 5: AHCI7804: ROM Required, and AMD driver required in the OS. 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.

(comment) NATIVE
(comment) RAID
(comment) AHCI
(comment) LEGACY IDE
(comment) IDE to AHCI
(comment) AHCI7804
(comment) IDE to AHCI7804
RAID_ROM_ID southbridge/amd/pi/hudson string RAID device PCI IDs

1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode

RAID_MISC_ROM_POSITION southbridge/amd/pi/hudson hex RAID Misc ROM Position

The RAID ROM requires that the MISC ROM is located between the range 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned. The CONFIG_ROM_SIZE must be larger than 0x100000.

HUDSON_LEGACY_FREE southbridge/amd/pi/hudson bool System is legacy free

Select y if there is no keyboard controller in the system. This sets variables in AGESA and ACPI.

AZ_PIN southbridge/amd/pi/hudson hex

bit 1,0 - pin 0 bit 3,2 - pin 1 bit 5,4 - pin 2 bit 7,6 - pin 3

HUDSON_UART southbridge/amd/pi/hudson bool UART controller on Kern

There are two UART controllers in Kern. The UART registers are memory-mapped. UART controller 0 registers range from FEDC_6000h to FEDC_6FFFh. UART controller 1 registers range from FEDC_8000h to FEDC_8FFFh.


SATA_CONTROLLER_MODE southbridge/amd/cimx/sb700 hex

0x0 = Native IDE mode. 0x1 = RAID mode. 0x2 = AHCI mode. 0x3 = Legacy IDE mode. 0x4 = IDE->AHCI mode. 0x5 = AHCI mode as 7804 ID (AMD driver). 0x6 = IDE->AHCI mode as 7804 ID (AMD driver).

PCIB_ENABLE southbridge/amd/cimx/sb700 bool

n = Disable PCI Bridge Device 14 Function 4. y = Enable PCI Bridge Device 14 Function 4.

ACPI_SCI_IRQ southbridge/amd/cimx/sb700 hex

Set SCI IRQ to 9.

REDIRECT_SBCIMX_TRACE_TO_SERIAL southbridge/amd/cimx/sb700 bool Redirect AMD Southbridge CIMX Trace to serial console

This Option allows you to redirect the AMD Southbridge CIMX Trace debug information to the serial console.

Warning: Only enable this option when debuging or tracing AMD CIMX code.

ENABLE_IDE_COMBINED_MODE southbridge/amd/cimx/sb800 bool Enable SATA IDE combined mode

If Combined Mode is enabled. IDE controller is exposed and SATA controller has control over Port0 through Port3, IDE controller has control over Port4 and Port5.

If Combined Mode is disabled, IDE controller is hidden and SATA controller has full control of all 6 Ports when operating in non-IDE mode.

IDE_COMBINED_MODE southbridge/amd/cimx/sb800 hex SATA Mode

Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. The default is AHCI.

SB800_SATA_IDE southbridge/amd/cimx/sb800 bool NATIVE

NATIVE does not require a ROM.

SB800_SATA_AHCI southbridge/amd/cimx/sb800 bool AHCI

AHCI is the default and may work with or without AHCI ROM. It depends on the payload support. For example, seabios does not require the AHCI ROM.

SB800_SATA_RAID southbridge/amd/cimx/sb800 bool RAID

sb800 RAID mode must have the two required ROM files.

RAID_ROM_ID southbridge/amd/cimx/sb800 string RAID device PCI IDs

1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode

RAID_MISC_ROM_POSITION southbridge/amd/cimx/sb800 hex RAID Misc ROM Position

The RAID ROM requires that the MISC ROM is located between the range 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned. The CONFIG_ROM_SIZE must larger than 0x100000.

SB800_IMC_FWM southbridge/amd/cimx/sb800 bool Add IMC firmware

Add SB800 / Hudson 1 IMC Firmware to support the onboard fan control.

SB800_FWM_AT_FFFA0000 southbridge/amd/cimx/sb800 bool 0xFFFA0000

The IMC and GEC ROMs requires a 'signature' located at one of several fixed locations in memory. The location used shouldn't matter, just select an area that doesn't conflict with anything else.

SB800_FWM_AT_FFF20000 southbridge/amd/cimx/sb800 bool 0xFFF20000

The IMC and GEC ROMs requires a 'signature' located at one of several fixed locations in memory. The location used shouldn't matter, just select an area that doesn't conflict with anything else.

SB800_FWM_AT_FFE20000 southbridge/amd/cimx/sb800 bool 0xFFE20000

The IMC and GEC ROMs requires a 'signature' located at one of several fixed locations in memory. The location used shouldn't matter, just select an area that doesn't conflict with anything else.

SB800_FWM_AT_FFC20000 southbridge/amd/cimx/sb800 bool 0xFFC20000

The IMC and GEC ROMs requires a 'signature' located at one of several fixed locations in memory. The location used shouldn't matter, just select an area that doesn't conflict with anything else.

SB800_FWM_AT_FF820000 southbridge/amd/cimx/sb800 bool 0xFF820000

The IMC and GEC ROMs requires a 'signature' located at one of several fixed locations in memory. The location used shouldn't matter, just select an area that doesn't conflict with anything else.

EHCI_BAR southbridge/amd/cimx/sb800 hex Fan Control

Select the method of SB800 fan control to be used. None would be for either fixed maximum speed fans connected to the SB800 or for an external chip controlling the fan speeds. Manual control sets up the SB800 fan control registers. IMC fan control uses the SB800 IMC to actively control the fan speeds.

SB800_NO_FAN_CONTROL southbridge/amd/cimx/sb800 bool None

No SB800 Fan control - Do not set up the SB800 fan control registers.

SB800_MANUAL_FAN_CONTROL southbridge/amd/cimx/sb800 bool Manual

Configure the SB800 fan control registers in devicetree.cb.

SB800_IMC_FAN_CONTROL southbridge/amd/cimx/sb800 bool IMC Based

Set up the SB800 to use the IMC based Fan controller. This requires the IMC rom from AMD. Configure the registers in devicetree.cb.

SATA_CONTROLLER_MODE southbridge/amd/cimx/sb900 hex

0x0 = Native IDE mode. 0x1 = RAID mode. 0x2 = AHCI mode. 0x3 = Legacy IDE mode. 0x4 = IDE->AHCI mode. 0x5 = AHCI mode as 7804 ID (AMD driver). 0x6 = IDE->AHCI mode as 7804 ID (AMD driver).

PCIB_ENABLE southbridge/amd/cimx/sb900 bool

n = Disable PCI Bridge Device 14 Function 4. y = Enable PCI Bridge Device 14 Function 4.

ACPI_SCI_IRQ southbridge/amd/cimx/sb900 hex

Set SCI IRQ to 9.

EXT_CONF_SUPPORT southbridge/amd/sr5650 bool Enable PCI-E MMCONFIG support

Select to enable PCI-E MMCONFIG support on the SR5650.