Difference between revisions of "Coreboot Options"

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This is an automatically generated list of '''coreboot compile-time options'''.
 
This is an automatically generated list of '''coreboot compile-time options'''.
  
Last update: 2011/10/14 00:44:39. (runknown)
+
Last update: 4.8-128-g0f5957a960
 
{| border="0" style="font-size: smaller"
 
{| border="0" style="font-size: smaller"
 
|- bgcolor="#6699dd"
 
|- bgcolor="#6699dd"
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|- bgcolor="#6699dd"
 
|- bgcolor="#6699dd"
 
! align="left" | Menu: General setup || || || ||
 
! align="left" | Menu: General setup || || || ||
|- bgcolor="#eeeeee"
 
| EXPERT || toplevel || bool || Expert mode ||
 
This allows you to select certain advanced configuration options.
 
 
Warning: Only enable this option if you really know what you are
 
doing! You have been warned!
 
 
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
 
| LOCALVERSION || toplevel || string || Local version string ||  
 
| LOCALVERSION || toplevel || string || Local version string ||  
Line 36: Line 28:
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CBFS_PREFIX || toplevel || string || Compiler ||  
+
| CBFS_PREFIX || toplevel || string || Compiler to use ||  
 
This option allows you to select the compiler used for building
 
This option allows you to select the compiler used for building
 
coreboot.
 
coreboot.
 +
You must build the coreboot crosscompiler for the board that you
 +
have selected.
 +
 +
To build all the GCC crosscompilers (takes a LONG time), run:
 +
make crossgcc
 +
 +
For help on individual architectures, run the command:
 +
make help_toolchain
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SCANBUILD_ENABLE || toplevel || bool || Build with scan-build for static analysis ||  
+
| COMPILER_GCC || toplevel || bool || GCC ||  
Changes the build process to scan-build is used.
+
Use the GNU Compiler Collection (GCC) to build coreboot.
Requires scan-build in path.
+
 
 +
For details see http://gcc.gnu.org.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SCANBUILD_REPORT_LOCATION || toplevel || string || Directory to put scan-build report in ||  
+
| COMPILER_LLVM_CLANG || toplevel || bool || LLVM/clang (TESTING ONLY - Not currently working) ||  
Where the scan-build report should be stored
+
Use LLVM/clang to build coreboot.  To use this, you must build the
 +
coreboot version of the clang compiler.  Run the command
 +
make clang
 +
Note that this option is not currently working correctly and should
 +
really only be selected if you're trying to work on getting clang
 +
operational.
 +
 
 +
For details see http://clang.llvm.org.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CCACHE || toplevel || bool || ccache ||  
+
| ANY_TOOLCHAIN || toplevel || bool || Allow building with any toolchain ||
 +
Many toolchains break when building coreboot since it uses quite
 +
unusual linker features. Unless developers explicitely request it,
 +
we'll have to assume that they use their distro compiler by mistake.
 +
Make sure that using patched compilers is a conscious decision.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CCACHE || toplevel || bool || Use ccache to speed up (re)compilation ||  
 
Enables the use of ccache for faster builds.
 
Enables the use of ccache for faster builds.
Requires ccache in path.
+
 
 +
Requires the ccache utility in your system $PATH.
 +
 
 +
For details see https://ccache.samba.org.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FMD_GENPARSER || toplevel || bool || Generate flashmap descriptor parser using flex and bison ||
 +
Enable this option if you are working on the flashmap descriptor
 +
parser and made changes to fmd_scanner.l or fmd_parser.y.
 +
 
 +
Otherwise, say N to use the provided pregenerated scanner/parser.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SCONFIG_GENPARSER || toplevel || bool || Generate SCONFIG parser using flex and bison ||  
+
| UTIL_GENPARSER || toplevel || bool || Generate SCONFIG & BINCFG parser using flex and bison ||  
Enable this option if you are working on the sconfig
+
Enable this option if you are working on the sconfig device tree
device tree parser and made changes to sconfig.l and
+
parser or bincfg and made changes to the .l or .y files.
sconfig.y.
+
 
Otherwise, say N.
+
Otherwise, say N to use the provided pregenerated scanner/parser.
  
 
||
 
||
Line 69: Line 96:
 
| USE_OPTION_TABLE || toplevel || bool || Use CMOS for configuration values ||  
 
| USE_OPTION_TABLE || toplevel || bool || Use CMOS for configuration values ||  
 
Enable this option if coreboot shall read options from the "CMOS"
 
Enable this option if coreboot shall read options from the "CMOS"
NVRAM instead of using hard coded values.
+
NVRAM instead of using hard-coded values.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| STATIC_OPTION_TABLE || toplevel || bool || Load default configuration values into CMOS on each boot ||
 +
Enable this option to reset "CMOS" NVRAM values to default on
 +
every boot.  Use this if you want the NVRAM configuration to
 +
never be modified from its default values.
  
 
||
 
||
Line 76: Line 110:
 
Compress ramstage to save memory in the flash image. Note
 
Compress ramstage to save memory in the flash image. Note
 
that decompression might slow down booting if the boot flash
 
that decompression might slow down booting if the boot flash
is connected through a slow Link (i.e. SPI)
+
is connected through a slow link (i.e. SPI).
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| INCLUDE_CONFIG_FILE || toplevel || bool || Include the coreboot config file into the ROM image ||
+
| COMPRESS_PRERAM_STAGES || toplevel || bool || Compress romstage and verstage with LZ4 ||
Include in CBFS the coreboot config file that was used to compile the ROM image
+
Compress romstage and (if it exists) verstage with LZ4 to save flash
 +
space and speed up boot, since the time for reading the image from SPI
 +
(and in the vboot case verifying it) is usually much greater than the
 +
time spent decompressing. Doesn't work for XIP stages (assume all
 +
ARCH_X86 for now) for obvious reasons.
  
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| COMPRESS_BOOTBLOCK || toplevel || bool ||  ||
 +
This option can be used to compress the bootblock with LZ4 and attach
 +
a small self-decompression stub to its front. This can drastically
 +
reduce boot time on platforms where the bootblock is loaded over a
 +
very slow connection and bootblock size trumps all other factors for
 +
speed. Since this using this option usually requires changes to the
 +
SoC memlayout and possibly extra support code, it should not be
 +
user-selectable. (There's no real point in offering this to the user
 +
anyway... if it works and saves boot time, you would always want it.)
  
|- bgcolor="#6699dd"
+
||
! align="left" | Menu: Mainboard || || || ||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOARD_LENOVO_X60 || mainboard/lenovo || bool || ThinkPad X60 / X60s ||  
+
| INCLUDE_CONFIG_FILE || toplevel || bool || Include the coreboot .config file into the ROM image ||  
The following X60 series ThinkPad machines have been verified to
+
Include the .config file that was used to compile coreboot
work correctly:
+
in the (CBFS) ROM image. This is useful if you want to know which
 +
options were used to build a specific coreboot.rom image.
  
ThinkPad X60s (Model 1702, 1703)
+
Saying Y here will increase the image size by 2-3KB.
ThinkPad X60 (Model 1709)
+
 
 +
You can use the following command to easily list the options:
 +
 
 +
grep -a CONFIG_ coreboot.rom
 +
 
 +
Alternatively, you can also use cbfstool to print the image
 +
contents (including the raw 'config' item we're looking for).
 +
 
 +
Example:
 +
 
 +
$ cbfstool coreboot.rom print
 +
coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
 +
offset 0x0
 +
Alignment: 64 bytes
 +
 
 +
Name                          Offset    Type        Size
 +
cmos_layout.bin                0x0        cmos layout 1159
 +
fallback/romstage              0x4c0      stage        339756
 +
fallback/ramstage              0x53440    stage        186664
 +
fallback/payload              0x80dc0    payload      51526
 +
config                        0x8d740    raw          3324
 +
(empty)                       0x8e480    null        3610440
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOARD_LENOVO_T60 || mainboard/lenovo || bool || ThinkPad T60 / T60p ||  
+
| COLLECT_TIMESTAMPS || toplevel || bool || Create a table of timestamps collected during boot ||  
The following T60 series ThinkPad machines have been verified to
+
Make coreboot create a table of timer-ID/timer-value pairs to
work correctly:
+
allow measuring time spent at different phases of the boot process.
  
Thinkpad T60p (Model 2007)
+
||
 +
|- bgcolor="#eeeeee"
 +
| TIMESTAMPS_ON_CONSOLE || toplevel || bool || Print the timestamp values on the console ||
 +
Print the timestamps to the debug console if enabled at level spew.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOARD_OLD_REVISION || mainboard/lippert/hurricane-lx || bool || Board is old pre-3.0 revision ||  
+
| USE_BLOBS || toplevel || bool || Allow use of binary-only repository ||  
Look on the bottom side for a number like 406-0001-30.  The last 2
+
This draws in the blobs repository, which contains binary files that
digits state the PCB revision (3.0 in this example).  For 2.0 or older
+
might be required for some chipsets or boards.
boards choose Y, for 3.0 and newer say N.
+
This flag ensures that a "Free" option remains available for users.
 
+
 
Old revision boards need a jumper shorting the power button to
 
power on automatically.  You may enable the button only after this
 
jumper has been removed.  New revision boards are not restricted
 
in this way, and always have the power button enabled.
 
 
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ONBOARD_UARTS_RS485 || mainboard/lippert/hurricane-lx || bool || Switch on-board serial ports to RS485 ||  
+
| COVERAGE || toplevel || bool || Code coverage support ||  
If selected, both on-board serial ports will operate in RS485 mode
+
Add code coverage support for coreboot. This will store code
instead of RS232.
+
coverage information in CBMEM for extraction from user space.
 +
If unsure, say N.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ONBOARD_UARTS_RS485 || mainboard/lippert/literunner-lx || bool || Switch on-board serial ports 1 & 2 to RS485 ||  
+
| UBSAN || toplevel || bool || Undefined behavior sanitizer support ||  
If selected, the first two on-board serial ports will operate in RS485
+
Instrument the code with checks for undefined behavior. If unsure,
mode instead of RS232.
+
say N because it adds a small performance penalty and may abort
 +
on code that happens to work in spite of the UB.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ONBOARD_IDE_SLAVE || mainboard/lippert/literunner-lx || bool || Make on-board CF socket act as Slave ||  
+
| RELOCATABLE_RAMSTAGE || toplevel || bool || Build the ramstage to be relocatable in 32-bit address space. ||  
If selected, the on-board Compact Flash card socket will act as IDE
+
The reloctable ramstage support allows for the ramstage to be built
Slave instead of Master.
+
as a relocatable module. The stage loader can identify a place
 +
out of the OS way so that copying memory is unnecessary during an S3
 +
wake. When selecting this option the romstage is responsible for
 +
determing a stack location to use for loading the ramstage.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ONBOARD_UARTS_RS485 || mainboard/lippert/roadrunner-lx || bool || Switch on-board serial ports to RS485 ||  
+
| CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM || toplevel || bool || ||  
If selected, both on-board serial ports will operate in RS485 mode
+
The relocated ramstage is saved in an area specified by the
instead of RS232.
+
by the board and/or chipset.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ONBOARD_UARTS_RS485 || mainboard/lippert/spacerunner-lx || bool || Switch on-board serial ports to RS485 ||  
+
| UPDATE_IMAGE || toplevel || bool || Update existing coreboot.rom image ||  
If selected, both on-board serial ports will operate in RS485 mode
+
If this option is enabled, no new coreboot.rom file
instead of RS232.
+
is created. Instead it is expected that there already
 +
is a suitable file for further processing.
 +
The bootblock will not be modified.
 +
 
 +
If unsure, select 'N'
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ONBOARD_IDE_SLAVE || mainboard/lippert/spacerunner-lx || bool || Make on-board SSD act as Slave ||  
+
| BOOTSPLASH_IMAGE || toplevel || bool || Add a bootsplash image ||  
If selected, the on-board SSD will act as IDE Slave instead of Master.
+
Select this option if you have a bootsplash image that you would
 +
like to add to your ROM.
 +
 
 +
This will only add the image to the ROM. To actually run it check
 +
options under 'Display' section.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SIO_PORT || mainboard/supermicro/h8qgi || hex || ||  
+
| BOOTSPLASH_FILE || toplevel || string || Bootsplash path and filename ||  
though UARTs are on the NUVOTON BMC, port 0x164E
+
The path and filename of the file to use as graphical bootsplash
PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E
+
screen. The file format has to be jpg.
  
 
||
 
||
 +
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: Mainboard || || || ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Important: Run 'make distclean' before switching boards ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOARD_ROMSIZE_KB_16384 || mainboard || bool || ROM chip size ||  
+
| VENDOR_WINNET || mainboard/winnet.name || bool || WinNET ||  
Select the size of the ROM chip you intend to flash coreboot on.
+
WinNET boards. Used in various thin client appliances.
  
The build system will take care of creating a coreboot.rom file
+
||
of the matching size.
+
||
 +
|- bgcolor="#eeeeee"
 +
| UART_FOR_CONSOLE || mainboard/intel/mohonpeak || int ||  ||
 +
The Mohon Peak board uses COM2 (2f8) for the serial console.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_128 || mainboard || bool || 128 KB ||  
+
| PAYLOAD_CONFIGFILE || mainboard/intel/mohonpeak || string || ||  
Choose this option if you have a 128 KB ROM chip.
+
The Avoton/Rangeley chip does not allow devices to write into the 0xe000
 +
segment.  This means that USB/SATA devices will not work in SeaBIOS unless
 +
we put the SeaBIOS buffer area down in the 0x9000 segment.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_256 || mainboard || bool || 256 KB ||  
+
| ENABLE_FSP_MEMORY_DOWN || mainboard/intel/harcuvar || bool || Enable Memory Down ||  
Choose this option if you have a 256 KB ROM chip.
+
Select this option to enable Memory Down function.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_512 || mainboard || bool || 512 KB ||  
+
| SPD_LOC || mainboard/intel/harcuvar || hex || SPD binary location in cbfs ||  
Choose this option if you have a 512 KB ROM chip.
+
Location of SPD binary for memory down function.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_1024 || mainboard || bool || 1024 KB (1 MB) ||  
+
| VBOOT || mainboard/intel/kblrvp || None || TPM to USE ||  
Choose this option if you have a 1024 KB (1 MB) ROM chip.
+
This option allows you to select the TPM to use.
 +
Select whether the board does not have TPM, TPM 1.1 or TPM 2.0
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_2048 || mainboard || bool || 2048 KB (2 MB) ||  
+
| UART_FOR_CONSOLE || mainboard/intel/littleplains || int || ||  
Choose this option if you have a 2048 KB (2 MB) ROM chip.
+
The Little Plains board uses COM2 (2f8) for the serial console.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_4096 || mainboard || bool || 4096 KB (4 MB) ||  
+
| PAYLOAD_CONFIGFILE || mainboard/intel/littleplains || string || ||  
Choose this option if you have a 4096 KB (4 MB) ROM chip.
+
The Avoton/Rangeley chip does not allow devices to write into the 0xe000
 +
segment.  This means that USB/SATA devices will not work in SeaBIOS unless
 +
we put the SeaBIOS buffer area down in the 0x9000 segment.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_8192 || mainboard || bool || 8192 KB (8 MB) ||  
+
| GALILEO_GEN2 || mainboard/intel/galileo || bool || Board generation: GEN1 (n) or GEN2 (y) ||  
Choose this option if you have a 8192 KB (8 MB) ROM chip.
+
The coreboot binary will configure only one generation of the Galileo
 +
board since coreboot can not determine the board generation at
 +
runtime.  Select which generation of the Galileo that coreboot
 +
should initialize.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_16384 || mainboard || bool || 16384 KB (16 MB) ||  
+
| FSP_VERSION_1_1 || mainboard/intel/galileo || bool || FSP 1.1 ||
Choose this option if you have a 16384 KB (16 MB) ROM chip.
+
Use FSP 1_1 binary
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_VERSION_2_0 || mainboard/intel/galileo || bool || FSP 2.0 ||  
 +
Use FSP 2.0 binary
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_POWER_BUTTON || mainboard || bool || Enable the power button ||  
+
| FSP_BUILD_TYPE_DEBUG || mainboard/intel/galileo || bool || Debug ||  
The selected mainboard can optionally have the power button tied
+
Use the debug version of FSP
to ground with a jumper so that the button appears to be
+
||
constantly depressed. If this option is enabled and the jumper is
+
|- bgcolor="#eeeeee"
installed then the board will turn on, but turn off again after a
+
| FSP_BUILD_TYPE_RELEASE || mainboard/intel/galileo || bool || Release ||
short timeout, usually 4 seconds.
+
Use the release version of FSP
 
 
Select Y here if you have removed the jumper and want to use an
 
actual power button. Select N if you have the jumper installed.
 
  
 
||
 
||
 
|- bgcolor="#6699dd"
 
! align="left" | Menu: Architecture (x86) || || || ||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| UPDATE_IMAGE || arch/x86 || bool || Update existing coreboot.rom image ||  
+
| FSP_TYPE_1_1 || mainboard/intel/galileo || bool || MemInit subroutine ||  
If this option is enabled, no new coreboot.rom file
+
FSP 1.1 implemented as subroutines, no EDK-II cores
is created. Instead it is expected that there already
+
||
is a suitable file for further processing.
+
|- bgcolor="#eeeeee"
The bootblock will not be modified.
+
| FSP_TYPE_1_1_PEI || mainboard/intel/galileo || bool || SEC + PEI Core + MemInit PEIM ||
 
+
FSP 1.1 implemented using SEC and PEI core
 
||
 
||
 
|- bgcolor="#6699dd"
 
! align="left" | Menu: Chipset || || || ||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || CPU ||
+
| FSP_TYPE_2_0 || mainboard/intel/galileo || bool || MemInit subroutine ||  
 +
FSP 2.0 implemented as subroutines, no EDK-II cores
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| UPDATE_CPU_MICROCODE || cpu/amd/model_10xxx || bool || Update CPU microcode ||  
+
| FSP_TYPE_2_0_PEI || mainboard/intel/galileo || bool || SEC + PEI Core + MemInit PEIM ||  
Select this to apply patches to the CPU microcode provided by
+
FSP 2.0 implemented using SEC and PEI core
AMD without source, and distributed with coreboot, to address
 
issues in the CPU post production.
 
 
 
Microcode updates distributed with coreboot are not necessarily
 
the latest version available from AMD. Updates are only applied
 
if they are newer than the microcode already in your CPU.
 
 
 
Unselect this to let Fam10h CPUs run with microcode as shipped
 
from factory. No binary microcode patches will be included in the
 
coreboot image in that case, which can help with creating an image
 
for which complete source code is available, which in turn might
 
simplify license compliance.
 
  
Microcode updates intend to solve issues that have been discovered
 
after CPU production. The common case is that systems work as
 
intended with updated microcode, but we have also seen cases where
 
issues were solved by not applying the microcode updates.
 
 
Note that some operating system include these same microcode
 
patches, so you may need to also disable microcode updates in
 
your operating system in order for this option to matter.
 
 
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| GEODE_VSA_FILE || cpu/amd/model_gx2 || bool || Add a VSA image ||  
+
| FSP_DEBUG_ALL || mainboard/intel/galileo || bool || Enable all FSP debug support ||  
Select this option if you have an AMD Geode GX2 vsa that you would
+
Turn on debug support to display HOBS, MTRRS, SMM_MEMORY_MAP, UPD_DATA
like to add to your ROM.
+
also turn on FSP 2.0 debug support for ESRAM_LAYOUT,
 
+
FSP_CALLS_AND_STATUS, FSP_HEADER, POSTCAR_CONSOLE and VERIFY_HOBS
You will be able to specify the location and file name of the
+
or FSP 1.1 DISPLAY_FSP_ENTRY_POINTS
image later.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VSA_FILENAME || cpu/amd/model_gx2 || string || AMD Geode GX2 VSA path and filename ||  
+
| VBOOT_WITH_CRYPTO_SHIELD || mainboard/intel/galileo || bool || Verified boot using the Crypto Shield board ||  
The path and filename of the file to use as VSA.
+
Perform a verified boot using the TPM on the Crypto Shield board.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| GEODE_VSA_FILE || cpu/amd/model_lx || bool || Add a VSA image ||  
+
| DRIVER_TPM_I2C_ADDR || mainboard/intel/galileo || hex || Address of the I2C TPM chip ||
Select this option if you have an AMD Geode LX vsa that you would
+
I2C address of the TPM chip on the Crypto Shield board.
like to add to your ROM.
+
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FMDFILE || mainboard/intel/galileo || string || FMAP description file in fmd format ||  
 +
The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
 +
but in some cases more complex setups are required.
  
You will be able to specify the location and file name of the
+
When an FMD descriptionn file is specified, the build system uses it
image later.
+
instead of creating a default FMAP file.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VSA_FILENAME || cpu/amd/model_lx || string || AMD Geode LX VSA path and filename ||  
+
| BASEBOARD_GLKRVP_LAPTOP || mainboard/intel/glkrvp || None || ON BOARD EC ||  
The path and filename of the file to use as VSA.
+
This option allows you to select the on board EC to use.
 +
Select whether the board  has Intel EC or Chrome EC
  
 
||
 
||
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: Debugging || || || ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL || cpu/amd/agesa/family10 || bool || Redirect AGESA IDS_HDT_CONSOLE to serial console ||  
+
| DISABLE_UART_ON_TESTPADS || mainboard/intel/dcp847ske || bool || Disable UART on testpads ||  
This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console.
+
Serial output requires soldering to the testpad next to
 +
NCT5577D pin 18 (txd) and gnd.
  
Warning: Only enable this option when debuging or tracing AMD AGESA code.
+
||
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SMP || cpu || bool ||  ||  
+
| VGA_BIOS_FILE || mainboard/intel/strago || string ||  ||  
This option is used to enable certain functions to make coreboot
+
The C0 version of the video bios gets computed from this name
work correctly on symmetric multi processor (SMP) systems.
+
so that they can both be added.  Only the correct one for the
 +
system will be run.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MMX || cpu || bool ||  ||  
+
| VGA_BIOS_ID || mainboard/intel/strago || string ||  ||  
Select MMX in your socket or model Kconfig if your CPU has MMX
+
The VGA_BIOS_ID for the C0 version of the video bios is hardcoded
streaming SIMD instructions. ROMCC can build more efficient
+
in soc/intel/braswell/Makefile.inc as 8086,22b1
code if it can spill to MMX registers.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SSE || cpu || bool || ||  
+
| BOARD_EMULATION_SPIKE_UCB_RISCV || mainboard/emulation/spike-riscv.name || bool || SPIKE ucb riscv ||  
Select SSE in your socket or model Kconfig if your CPU has SSE
+
To run coreboot in spike:
streaming SIMD instructions. ROMCC can build more efficient
+
* run "make" as usual
code if it can spill to SSE (aka XMM) registers.
+
* util/riscv/make-spike-elf.sh build/coreboot.{rom,elf}
 +
* spike -m1024 build/coreboot.elf
  
 +
||
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SSE2 || cpu || bool || ||  
+
| HUDSON_LEGACY_FREE || mainboard/bap/ode_e21XX || bool || Select DDR3 clock ||  
Select SSE2 in your socket or model Kconfig if your CPU has SSE2
+
Select your preferenced DDR3 clock setting.
streaming SIMD instructions. Some parts of coreboot can be built
+
 
with more efficient code if SSE2 instructions are available.
+
Note: This option changes the total power consumption.
 +
 
 +
If unsure, use DDR3-1333.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VAR_MTRR_HOLE || cpu || bool || ||  
+
| HUDSON_LEGACY_FREE || mainboard/bap/ode_e20XX || bool || Select DDR3 clock ||  
Unset this if you don't want the MTRR code to use
+
Select your preferred DDR3 clock setting.
subtractive MTRRs
+
 
 +
Note: This option changes the total power consumption.
 +
 
 +
If unsure, use DDR3-1066.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || Northbridge ||
+
| ENABLE_DP3_DAUGHTER_CARD_IN_J120 || mainboard/amd/lamar || bool || Use J120 as an additional graphics port ||
 +
The PCI Express slot at J120 can be configured as an additional
 +
DisplayPort connector using an adapter card from AMD or as a normal
 +
PCI Express (x4) slot.
 +
 
 +
By default, the connector is configured as a PCI Express (x4) slot.
 +
 
 +
Select this option to enable the slot for use with one of AMD's
 +
passive graphics port expander cards (only available from AMD).
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Slippy ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Octopus ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Auron ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Gru ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Cyan ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Reef ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Jecht ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Beltino ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Rambi ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Kahlee ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Poppy ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Zoombini ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Veyron ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Oak ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SVI_HIGH_FREQ || northbridge/amd/amdfam10 || bool || ||  
+
| MAINBOARD_PART_NUMBER || mainboard/google/nyan_blaze || string || BCT boot media ||  
Select this for boards with a Voltage Regulator able to operate
+
Which boot media to configure the BCT for.
at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.
 
  
 
||
 
||
|- bgcolor="#6699dd"
 
! align="left" | Menu: HyperTransport setup || || || ||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| None || northbridge/amd || None || HyperTransport frequency ||  
+
| NYAN_BLAZE_BCT_CFG_SPI || mainboard/google/nyan_blaze || bool || SPI ||  
This option sets the maximum permissible HyperTransport link
+
Configure the BCT for booting from SPI.
frequency.
 
  
Use of this option will only limit the autodetected HT frequency.
+
||
It will not (and cannot) increase the frequency beyond the
+
|- bgcolor="#eeeeee"
autodetected limits.
+
| NYAN_BLAZE_BCT_CFG_EMMC || mainboard/google/nyan_blaze || bool || eMMC ||
 +
Configure the BCT for booting from eMMC.
  
This is primarily used to work around poorly designed or laid out
+
||
HT traces on certain motherboards.
+
|- bgcolor="#eeeeee"
 +
| BOOT_DEVICE_SPI_FLASH_BUS || mainboard/google/nyan_blaze || int || SPI bus with boot media ROM ||
 +
Which SPI bus the boot media is connected to.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| LIMIT_HT_SPEED_AUTO || northbridge/amd || bool || HyperTransport downlink width ||  
+
| DISPLAY_SPD_DATA || mainboard/google/cyan || bool || Display Memory Serial Presence Detect Data ||  
This option sets the maximum permissible HyperTransport
+
When enabled displays the memory configuration data.
downlink width.
 
  
Use of this option will only limit the autodetected HT width.
+
||
It will not (and cannot) increase the width beyond the autodetected
+
|- bgcolor="#eeeeee"
limits.
+
| VGA_BIOS_FILE || mainboard/google/cyan || string ||  ||
 +
The C0 version of the video bios gets computed from this name
 +
so that they can both be added. Only the correct one for the
 +
system will be run.
  
This is primarily used to work around poorly designed or laid out HT
+
||
traces on certain motherboards.
+
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_ID || mainboard/google/cyan || string ||  ||
 +
The VGA_BIOS_ID for the C0 version of the video bios is hardcoded
 +
in soc/intel/braswell/Makefile.inc as 8086,22b1
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| LIMIT_HT_DOWN_WIDTH_16 || northbridge/amd || bool || HyperTransport uplink width ||  
+
| FMDFILE || mainboard/google/kahlee || string || ||  
This option sets the maximum permissible HyperTransport
+
The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
uplink width.
+
but in some cases more complex setups are required.
 +
When an fmd is specified, it overrides the default format.
  
Use of this option will only limit the autodetected HT width.
+
||
It will not (and cannot) increase the width beyond the autodetected
+
|- bgcolor="#eeeeee"
limits.
+
| DRAM_SIZE_MB || mainboard/google/smaug || int || BCT boot media ||
 +
Which boot media to configure the BCT for.
  
This is primarily used to work around poorly designed or laid out HT
+
||
traces on certain motherboards.
+
|- bgcolor="#eeeeee"
 +
| SMAUG_BCT_CFG_SPI || mainboard/google/smaug || bool || SPI ||
 +
Configure the BCT for booting from SPI.
  
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| SMAUG_BCT_CFG_EMMC || mainboard/google/smaug || bool || eMMC ||
 +
Configure the BCT for booting from eMMC.
  
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SDRAMPWR_4DIMM || northbridge/intel/i440bx || bool || ||  
+
| BOOT_DEVICE_SPI_FLASH_BUS || mainboard/google/smaug || int || SPI bus with boot media ROM ||  
This option affects how the SDRAMC register is programmed.
+
Which SPI bus the boot media is connected to.
Memory clock signals will not be routed properly if this option
 
is set wrong.
 
  
If your board has 4 DIMM slots, you must use select this option, in
+
||
your Kconfig file of the board. On boards with 3 DIMM slots,
+
|- bgcolor="#eeeeee"
do _not_ select this option.
+
| MAINBOARD_PART_NUMBER || mainboard/google/nyan_big || string || BCT boot media ||
 +
Which boot media to configure the BCT for.
  
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NYAN_BIG_BCT_CFG_SPI || mainboard/google/nyan_big || bool || SPI ||
 +
Configure the BCT for booting from SPI.
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| OVERRIDE_CLOCK_DISABLE || northbridge/intel/i945 || bool || ||  
+
| NYAN_BIG_BCT_CFG_EMMC || mainboard/google/nyan_big || bool || eMMC ||  
Usually system firmware turns off system memory clock
+
Configure the BCT for booting from eMMC.
signals to unused SO-DIMM slots to reduce EMI and power
 
consumption.
 
However, some boards do not like unused clock signals to
 
be disabled.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MAXIMUM_SUPPORTED_FREQUENCY || northbridge/intel/i945 || int || ||  
+
| BOOT_DEVICE_SPI_FLASH_BUS || mainboard/google/nyan_big || int || SPI bus with boot media ROM ||  
If non-zero, this designates the maximum DDR frequency
+
Which SPI bus the boot media is connected to.
the board supports, despite what the chipset should be
 
capable of.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || Southbridge ||
+
| DRAM_SIZE_MB || mainboard/google/foster || int || BCT boot media ||  
|- bgcolor="#6699dd"
+
Which boot media to configure the BCT for.
! align="left" | Menu: AMD Geode GX1 video support || || || ||
 
  
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EXT_CONF_SUPPORT || southbridge/amd/rs690 || bool || ||  
+
| FOSTER_BCT_CFG_SPI || mainboard/google/foster || bool || SPI ||  
Select if RS690 should be setup to support MMCONF.
+
Configure the BCT for booting from SPI.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| USBDEBUG_DEFAULT_PORT || southbridge/amd/sb600 || int || SATA Mode ||  
+
| FOSTER_BCT_CFG_EMMC || mainboard/google/foster || bool || eMMC ||  
Select the mode in which SATA should be driven. IDE or AHCI.
+
Configure the BCT for booting from eMMC.
The default is IDE.
 
  
config SATA_MODE_IDE
+
||
bool "IDE"
+
|- bgcolor="#eeeeee"
 +
| BOOT_DEVICE_SPI_FLASH_BUS || mainboard/google/foster || int || SPI bus with boot media ROM ||
 +
Which SPI bus the boot media is connected to.
  
config SATA_MODE_AHCI
 
bool "AHCI"
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_IDE_COMBINED_MODE || southbridge/amd/cimx/sb800 || bool || Enable SATA IDE combined mode ||  
+
| MAINBOARD_PART_NUMBER || mainboard/google/nyan || string || BCT boot media ||  
If Combined Mode is enabled. IDE controller is exposed and
+
Which boot media to configure the BCT for.
SATA controller has control over Port0 through Port3,
 
IDE controller has control over Port4 and Port5.
 
 
 
If Combined Mode is disabled, IDE controller is hidden and
 
SATA controller has full control of all 6 Ports when operating in non-IDE mode.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| IDE_COMBINED_MODE || southbridge/amd/cimx/sb800 || hex || SATA Mode ||  
+
| NYAN_BCT_CFG_SPI || mainboard/google/nyan || bool || SPI ||  
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
+
Configure the BCT for booting from SPI.
The default is NATIVE.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SB800_SATA_IDE || southbridge/amd/cimx/sb800 || bool || NATIVE ||  
+
| NYAN_BCT_CFG_EMMC || mainboard/google/nyan || bool || eMMC ||  
NATIVE is the default mode and does not require a ROM.
+
Configure the BCT for booting from eMMC.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SB800_SATA_AHCI || southbridge/amd/cimx/sb800 || bool || AHCI ||  
+
| BOOT_DEVICE_SPI_FLASH_BUS || mainboard/google/nyan || int || SPI bus with boot media ROM ||  
AHCI may work with or without AHCI ROM. It depends on the payload support.
+
Which SPI bus the boot media is connected to.
For example, seabios does not require the AHCI ROM.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SB800_SATA_RAID || southbridge/amd/cimx/sb800 || bool || RAID ||  
+
| UART_FOR_CONSOLE || mainboard/adi/rcc-dff || int || ||  
sb800 RAID mode must have the two required ROM files.
+
The Mohon Peak board uses COM2 (2f8) for the serial console.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| RAID_ROM_ID || southbridge/amd/cimx/sb800 || string || RAID device PCI IDs ||  
+
| PAYLOAD_CONFIGFILE || mainboard/adi/rcc-dff || string || ||  
1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode
+
The Avoton/Rangeley chip does not allow devices to write into the 0xe000
 +
segment.  This means that USB/SATA devices will not work in SeaBIOS unless
 +
we put the SeaBIOS buffer area down in the 0x9000 segment.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| RAID_MISC_ROM_POSITION || southbridge/amd/cimx/sb800 || hex || RAID Misc ROM Position ||  
+
| BOARD_ASUS_F2A85_M_DDR3_VOLT_135 || mainboard/asus/f2a85-m || bool || 1.35V ||  
The RAID ROM requires that the MISC ROM is located between the range
+
Set DRR3 memory voltage to 1.35V
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
 
The CONFIG_ROM_SIZE must larger than 0x100000.
 
 
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SATA_CONTROLLER_MODE || southbridge/amd/cimx/sb900 || hex || ||  
+
| BOARD_ASUS_F2A85_M_DDR3_VOLT_150 || mainboard/asus/f2a85-m || bool || 1.50V ||  
0x0 = Native IDE mode.
+
Set DRR3 memory voltage to 1.50V
0x1 = RAID mode.
 
0x2 = AHCI mode.
 
0x3 = Legacy IDE mode.
 
0x4 = IDE->AHCI mode.
 
0x5 = AHCI mode as 7804 ID (AMD driver).
 
0x6 = IDE->AHCI mode as 7804 ID (AMD driver).
 
 
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PCIB_ENABLE || southbridge/amd/cimx/sb900 || bool || ||  
+
| BOARD_ASUS_F2A85_M_DDR3_VOLT_165 || mainboard/asus/f2a85-m || bool || 1.65V ||  
n = Disable PCI Bridge Device 14 Function 4.
+
Set DRR3 memory voltage to 1.65V
y = Enable PCI Bridge Device 14 Function 4.
 
 
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ACPI_SCI_IRQ || southbridge/amd/cimx/sb900 || hex || ||  
+
| BOARD_WINNET_G170 || mainboard/winnet/g170.name || bool || WinNET G170 (Neoware CA19, IGEL 2110) ||  
Set SCI IRQ to 9.
+
G170 is a board manufactured by WinNET, used in thin clients including
 +
HP Neoware CA19 and IGEL 2110.
  
 
||
 
||
|- bgcolor="#eeeeee"
 
| HAVE_CMC || southbridge/intel/sch || bool || Add a CMC state machine binary ||
 
Select this option to add a CMC state machine binary to
 
the resulting coreboot image.
 
 
Note: Without this binary coreboot will not work
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CMC_FILE || southbridge/intel/sch || string || Intel CMC path and filename ||  
+
| BMC_INFO_LOC || mainboard/scaleway/tagada || hex || BMC information location in flash ||  
The path and filename of the file to use as CMC state machine
+
Location of BMC SERIAL information.
binary.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || Super I/O ||
+
| NO_POST || mainboard/purism/librem_skl || int || ||  
|- bgcolor="#eeeeee"
+
This platform does not have any way to see POST codes
| || || (comment) || || Devices ||
+
so disable them by default.
|- bgcolor="#eeeeee"
 
| VGA_BRIDGE_SETUP || devices || bool || Setup bridges on path to VGA adapter ||
 
Allow bridges to set up legacy decoding ranges for VGA. Don't disable
 
this unless you're sure you don't want the briges setup for VGA.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VGA_ROM_RUN || devices || bool || Run VGA option ROMs ||  
+
| DRIVERS_PS2_KEYBOARD || mainboard/purism/librem_bdw || string || ||  
Execute VGA option ROMs, if found. This is required to enable
+
Default PS/2 Keyboard to enabled on this board.
PCI/AGP/PCI-E video cards.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PCI_ROM_RUN || devices || bool || Run non-VGA option ROMs ||  
+
| DRIVERS_UART_8250IO || mainboard/purism/librem_bdw || string || ||  
Execute non-VGA PCI option ROMs, if found.
+
This platform does not have any way to get standard
 
+
serial output so disable it by default.
Examples include IDE/SATA controller option ROMs and option ROMs
 
for network cards (NICs).
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PCI_OPTION_ROM_RUN_REALMODE || devices || bool || Native mode ||  
+
| NO_POST || mainboard/purism/librem_bdw || int || ||  
If you select this option, PCI option ROMs will be executed
+
This platform does not have any way to see POST codes
natively on the CPU in real mode. No CPU emulation is involved,
+
so disable them by default.
so this is the fastest, but also the least secure option.
 
(only works on x86/x64 systems)
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PCI_OPTION_ROM_RUN_YABEL || devices || bool || Secure mode ||  
+
| || || (comment) || || was acquired by ADLINK ||
If you select this option, the x86emu CPU emulator will be used to
+
|- bgcolor="#eeeeee"
execute PCI option ROMs.
+
| ONBOARD_UARTS_RS485 || mainboard/lippert/spacerunner-lx || bool || Switch on-board serial ports to RS485 ||  
 +
If selected, both on-board serial ports will operate in RS485 mode
 +
instead of RS232.
  
This option prevents option ROMs from doing dirty tricks with the
+
||
system (such as installing SMM modules or hypervisors), but it is
+
|- bgcolor="#eeeeee"
also significantly slower than the native option ROM initialization
+
| ONBOARD_IDE_SLAVE || mainboard/lippert/spacerunner-lx || bool || Make on-board SSD act as Slave ||
method.
+
If selected, the on-board SSD will act as IDE Slave instead of Master.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOARD_OLD_REVISION || mainboard/lippert/hurricane-lx || bool || Board is old pre-3.0 revision ||
 +
Look on the bottom side for a number like 406-0001-30.  The last 2
 +
digits state the PCB revision (3.0 in this example).  For 2.0 or older
 +
boards choose Y, for 3.0 and newer say N.
  
This is the default choice for non-x86 systems.
+
Old revision boards need a jumper shorting the power button to
 +
power on automatically.  You may enable the button only after this
 +
jumper has been removed.  New revision boards are not restricted
 +
in this way, and always have the power button enabled.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| YABEL_PCI_ACCESS_OTHER_DEVICES || devices || bool || Allow option ROMs to access other devices ||  
+
| ONBOARD_UARTS_RS485 || mainboard/lippert/hurricane-lx || bool || Switch on-board serial ports to RS485 ||  
Per default, YABEL only allows option ROMs to access the PCI device
+
If selected, both on-board serial ports will operate in RS485 mode
that they are associated with. However, this causes trouble for some
+
instead of RS232.
onboard graphics chips whose option ROM needs to reconfigure the
 
north bridge.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| YABEL_VIRTMEM_LOCATION || devices || hex || Location of YABEL's virtual memory ||  
+
| ONBOARD_UARTS_RS485 || mainboard/lippert/literunner-lx || bool || Switch on-board serial ports 1 & 2 to RS485 ||  
YABEL requires 1MB memory for its CPU emulation. This memory is
+
If selected, the first two on-board serial ports will operate in RS485
normally located at 16MB.
+
mode instead of RS232.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| YABEL_DIRECTHW || devices || bool || Direct hardware access ||  
+
| ONBOARD_IDE_SLAVE || mainboard/lippert/literunner-lx || bool || Make on-board CF socket act as Slave ||  
YABEL consists of two parts: It uses x86emu for the CPU emulation and
+
If selected, the on-board Compact Flash card socket will act as IDE
additionally provides a PC system emulation that filters bad device
+
Slave instead of Master.
and memory access (such as PCI config space access to other devices
 
than the initialized one).
 
  
When choosing this option, x86emu will pass through all hardware
+
||
accesses to memory and I/O devices to the underlying memory and I/O
+
|- bgcolor="#eeeeee"
addresses. While this option prevents option ROMs from doing dirty
+
| ONBOARD_UARTS_RS485 || mainboard/lippert/roadrunner-lx || bool || Switch on-board serial ports to RS485 ||
tricks with the CPU (such as installing SMM modules or hypervisors),
+
If selected, both on-board serial ports will operate in RS485 mode
they can still access all devices in the system.
+
instead of RS232.
Enable this option for a good compromise between security and speed.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || Embedded Controllers ||
+
| || || (comment) || || see under vendor LiPPERT ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || WARNING: This mainboard uses LATE_CBMEM_INIT, which is deprecated ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EC_ACPI || ec/acpi || bool || ||  
+
| BOARD_ROMSIZE_KB_65536 || mainboard || bool || ROM chip size ||  
ACPI Embedded Controller interface. Mostly found in laptops.
+
Select the size of the ROM chip you intend to flash coreboot on.
 +
 
 +
The build system will take care of creating a coreboot.rom file
 +
of the matching size.
  
 
||
 
||
||
 
 
|- bgcolor="#6699dd"
 
! align="left" | Menu: Generic Drivers || || || ||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DRIVERS_OXFORD_OXPCIE || drivers/oxford/oxpcie || bool || Oxford OXPCIe952 ||  
+
| COREBOOT_ROMSIZE_KB_64 || mainboard || bool || 64 KB ||  
Support for Oxford OXPCIe952 serial port PCIe cards.
+
Choose this option if you have a 64 KB ROM chip.
Currently only devices with the vendor ID 0x1415 and device ID
 
0xc158 will work.
 
NOTE: Right now you have to set the base address of your OXPCIe952
 
card to exactly the value that the device allocator would set them
 
later on, or serial console functionality will stop as soon as the
 
resource allocator assigns a new base address to the device.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BRIDGE_BUS || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge bus number ||  
+
| COREBOOT_ROMSIZE_KB_128 || mainboard || bool || 128 KB ||  
While coreboot is executing code from ROM, the coreboot resource
+
Choose this option if you have a 128 KB ROM chip.
allocator has not been running yet. Hence PCI devices living behind
 
a bridge are not yet visible to the system. In order to use an
 
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
 
that controls the OXPCIe952 controller first.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BRIDGE_DEVICE || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge device number ||  
+
| COREBOOT_ROMSIZE_KB_256 || mainboard || bool || 256 KB ||  
While coreboot is executing code from ROM, the coreboot resource
+
Choose this option if you have a 256 KB ROM chip.
allocator has not been running yet. Hence PCI devices living behind
 
a bridge are not yet visible to the system. In order to use an
 
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
 
that controls the OXPCIe952 controller first.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BRIDGE_FUNCTION || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge function number ||  
+
| COREBOOT_ROMSIZE_KB_512 || mainboard || bool || 512 KB ||  
While coreboot is executing code from ROM, the coreboot resource
+
Choose this option if you have a 512 KB ROM chip.
allocator has not been running yet. Hence PCI devices living behind
 
a bridge are not yet visible to the system. In order to use an
 
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
 
that controls the OXPCIe952 controller first.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BRIDGE_SUBORDINATE || drivers/oxford/oxpcie || hex || OXPCIe's PCIe bridge subordinate bus ||  
+
| COREBOOT_ROMSIZE_KB_1024 || mainboard || bool || 1024 KB (1 MB) ||  
While coreboot is executing code from ROM, the coreboot resource
+
Choose this option if you have a 1024 KB (1 MB) ROM chip.
allocator has not been running yet. Hence PCI devices living behind
 
a bridge are not yet visible to the system. In order to use an
 
OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge
 
that controls the OXPCIe952 controller first.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| OXFORD_OXPCIE_BASE_ADDRESS || drivers/oxford/oxpcie || hex || Base address for rom stage console ||  
+
| COREBOOT_ROMSIZE_KB_2048 || mainboard || bool || 2048 KB (2 MB) ||  
While coreboot is executing code from ROM, the coreboot resource
+
Choose this option if you have a 2048 KB (2 MB) ROM chip.
allocator has not been running yet. Hence PCI devices living behind
 
a bridge are not yet visible to the system. In order to use an
 
OXPCIe952 based PCIe card, coreboot has to set up a temporary address
 
for the OXPCIe952 controller.
 
 
 
  
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| COREBOOT_ROMSIZE_KB_4096 || mainboard || bool || 4096 KB (4 MB) ||
 +
Choose this option if you have a 4096 KB (4 MB) ROM chip.
  
||
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DRIVERS_SIL_3114 || drivers/sil || bool || Silicon Image SIL3114 ||  
+
| COREBOOT_ROMSIZE_KB_8192 || mainboard || bool || 8192 KB (8 MB) ||  
It sets PCI class to IDE compatible native mode, allowing
+
Choose this option if you have a 8192 KB (8 MB) ROM chip.
SeaBIOS, FILO etc... to boot from it.
 
 
 
 
 
  
 
||
 
||
||
 
 
|- bgcolor="#6699dd"
 
! align="left" | Menu: Console || || || ||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL8250 || console || bool || Serial port console output ||  
+
| COREBOOT_ROMSIZE_KB_10240 || mainboard || bool || 10240 KB (10 MB) ||  
Send coreboot debug output to an I/O mapped serial port console.
+
Choose this option if you have a 10240 KB (10 MB) ROM chip.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL8250MEM || console || bool || Serial port console output (memory mapped) ||  
+
| COREBOOT_ROMSIZE_KB_12288 || mainboard || bool || 12288 KB (12 MB) ||  
Send coreboot debug output to a memory mapped serial port console.
+
Choose this option if you have a 12288 KB (12 MB) ROM chip.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM1 || console || bool || COM1/ttyS0, I/O port 0x3f8 ||  
+
| COREBOOT_ROMSIZE_KB_16384 || mainboard || bool || 16384 KB (16 MB) ||  
Serial console on COM1/ttyS0 at I/O port 0x3f8.
+
Choose this option if you have a 16384 KB (16 MB) ROM chip.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM2 || console || bool || COM2/ttyS1, I/O port 0x2f8 ||  
+
| COREBOOT_ROMSIZE_KB_32768 || mainboard || bool || 32768 KB (32 MB) ||  
Serial console on COM2/ttyS1 at I/O port 0x2f8.
+
Choose this option if you have a 32768 KB (32 MB) ROM chip.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM3 || console || bool || COM3/ttyS2, I/O port 0x3e8 ||  
+
| COREBOOT_ROMSIZE_KB_65536 || mainboard || bool || 65536 KB (64 MB) ||  
Serial console on COM3/ttyS2 at I/O port 0x3e8.
+
Choose this option if you have a 65536 KB (64 MB) ROM chip.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_COM4 || console || bool || COM4/ttyS3, I/O port 0x2e8 ||  
+
| ENABLE_POWER_BUTTON || mainboard || bool || Enable the power button ||  
Serial console on COM4/ttyS3 at I/O port 0x2e8.
+
The selected mainboard can optionally have the power button tied
 +
to ground with a jumper so that the button appears to be
 +
constantly depressed. If this option is enabled and the jumper is
 +
installed then the board will turn on, but turn off again after a
 +
short timeout, usually 4 seconds.
 +
 
 +
Select Y here if you have removed the jumper and want to use an
 +
actual power button. Select N if you have the jumper installed.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| TTYS0_BASE || console || hex ||  ||  
+
| DEVICETREE || toplevel || string ||  ||  
Map the COM port names to the respective I/O port.
+
This symbol allows mainboards to select a different file under their
 +
mainboard directory for the devicetree.cb file.  This allows the board
 +
variants that need different devicetrees to be in the same directory.
 +
 
 +
Examples: "devicetree.variant.cb"
 +
"variant/devicetree.cb"
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_115200 || console || bool || 115200 ||  
+
| CBFS_SIZE || toplevel || hex || Size of CBFS filesystem in ROM ||  
Set serial port Baud rate to 115200.
+
This is the part of the ROM actually managed by CBFS, located at the
 +
end of the ROM (passed through cbfstool -o) on x86 and at at the start
 +
of the ROM (passed through cbfstool -s) everywhere else. It defaults
 +
to span the whole ROM on all but Intel systems that use an Intel Firmware
 +
Descriptor.  It can be overridden to make coreboot live alongside other
 +
components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
 +
binaries.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_57600 || console || bool || 57600 ||  
+
| FMDFILE || toplevel || string || fmap description file in fmd format ||  
Set serial port Baud rate to 57600.
+
The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
 +
but in some cases more complex setups are required.
 +
When an fmd is specified, it overrides the default format.
 +
 
 
||
 
||
 +
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_38400 || console || bool || 38400 ||  
+
| CBFS_AUTOGEN_ATTRIBUTES || toplevel || bool || ||  
Set serial port Baud rate to 38400.
+
If this option is selected, every file in cbfs which has a constraint
 +
regarding position or alignment will get an additional file attribute
 +
which describes this constraint.
 +
 
 
||
 
||
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: Chipset || || || ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || SoC ||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_19200 || console || bool || 19200 ||  
+
| MAINBOARD_DO_DSI_INIT || soc/nvidia/tegra210 || bool || Use dsi graphics interface ||  
Set serial port Baud rate to 19200.
+
Initialize dsi display
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_9600 || console || bool || 9600 ||  
+
| MAINBOARD_DO_SOR_INIT || soc/nvidia/tegra210 || bool || Use dp graphics interface ||  
Set serial port Baud rate to 9600.
+
Initialize dp display
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| TTYS0_BAUD || console || int || ||  
+
| CONSOLE_SERIAL_TEGRA210_UARTA || soc/nvidia/tegra210 || bool || UARTA ||  
Map the Baud rates to an integer.
+
Serial console on UART A.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| USBDEBUG || console || bool || USB 2.0 EHCI debug dongle support ||  
+
| CONSOLE_SERIAL_TEGRA210_UARTB || soc/nvidia/tegra210 || bool || UARTB ||
This option allows you to use a so-called USB EHCI Debug device
+
Serial console on UART B.
(such as the Ajays NET20DC, AMIDebug RX, or a system using the
+
 
Linux "EHCI Debug Device gadget" driver found in recent kernel)
+
||
to retrieve the coreboot debug messages (instead, or in addition
+
|- bgcolor="#eeeeee"
to, a serial port).
+
| CONSOLE_SERIAL_TEGRA210_UARTC || soc/nvidia/tegra210 || bool || UARTC ||
 +
Serial console on UART C.
  
This feature is NOT supported on all chipsets in coreboot!
+
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_SERIAL_TEGRA210_UARTD || soc/nvidia/tegra210 || bool || UARTD ||
 +
Serial console on UART D.
  
It also requires a USB2 controller which supports the EHCI
+
||
Debug Port capability.
+
|- bgcolor="#eeeeee"
 
+
| CONSOLE_SERIAL_TEGRA210_UARTE || soc/nvidia/tegra210 || bool || UARTE ||
See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list
+
Serial console on UART E.
of supported controllers.
 
 
 
If unsure, say N.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| USBDEBUG_DEFAULT_PORT || console || int || Default USB port to use as Debug Port ||  
+
| CONSOLE_SERIAL_TEGRA210_UART_ADDRESS || soc/nvidia/tegra210 || hex || ||  
This option selects which physical USB port coreboot will try to
+
Map the UART names to the respective MMIO addres.
use as EHCI Debug Port first (valid values are: 1-15).
 
 
 
If coreboot doesn't detect an EHCI Debug Port dongle on this port,
 
it will try all the other ports one after the other. This will take
 
a few seconds of time though, and thus slow down the booting process.
 
 
 
Hence, if you select the correct port here, you can speed up
 
your boot time. Which USB port number (1-15) refers to which
 
actual port on your mainboard (potentially also USB pin headers
 
on your mainboard) is highly board-specific, and you'll likely
 
have to find out by trial-and-error.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ONBOARD_VGA_IS_PRIMARY || console || bool || Use onboard VGA as primary video device ||  
+
| BOOTROM_SDRAM_INIT || soc/nvidia/tegra210 || bool || SoC BootROM does SDRAM init with full BCT ||  
If not selected, the last adapter found will be used.
+
Use during Foster LPDDR4 bringup.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_NE2K || console || bool || Network console over NE2000 compatible Ethernet adapter ||  
+
| TRUSTZONE_CARVEOUT_SIZE_MB || soc/nvidia/tegra210 || hex || Size of Trust Zone region ||  
Send coreboot debug output to a Ethernet console, it works
+
Size of Trust Zone area in MiB to reserve in memory map.
same way as Linux netconsole, packets are received to UDP
 
port 6666 on IP/MAC specified with options bellow.
 
Use following netcat command: nc -u -l -p 6666
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_NE2K_DST_MAC || console || string || Destination MAC address of remote system ||  
+
| TTB_SIZE_MB || soc/nvidia/tegra210 || hex || Size of TTB ||  
Type in either MAC address of logging system or MAC address
+
Maximum size of Translation Table Buffer in MiB.
of the router.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_NE2K_DST_IP || console || string || Destination IP of logging system ||  
+
| SEC_COMPONENT_SIZE_MB || soc/nvidia/tegra210 || hex || Size of resident EL3 components ||  
This is IP adress of the system running for example
+
Maximum size of resident EL3 components in MiB including BL31 and
netcat command to dump the packets.
+
Secure OS.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_NE2K_SRC_IP || console || string || IP address of coreboot system ||  
+
| HAVE_MTC || soc/nvidia/tegra210 || bool || Add external Memory controller Training Code binary ||  
This is the IP of the coreboot system
+
Select this option to add emc training firmware
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_NE2K_IO_PORT || console || hex || NE2000 adapter fixed IO port address ||  
+
| MTC_FILE || soc/nvidia/tegra210 || string || tegra mtc firmware filename ||  
This is the IO port address for the IO port
+
The filename of the mtc firmware
on the card, please select some non-conflicting region,
 
32 bytes of IO spaces will be used (and align on 32 bytes
 
boundary, qemu needs broader align)
 
  
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MTC_DIRECTORY || soc/nvidia/tegra210 || string || Directory where MTC firmware file is located ||
 +
Path to directory where MTC firmware file is located.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_8 || console || bool || 8: SPEW ||  
+
| MTC_ADDRESS || soc/nvidia/tegra210 || hex || ||  
Way too many details.
+
The DRAM location where MTC firmware to be loaded in. This location
 +
needs to be consistent with the location defined in tegra_mtc.ld
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_7 || console || bool || 7: DEBUG ||  
+
| SOC_INTEL_APOLLOLAKE || soc/intel/apollolake || bool || ||  
Debug-level messages.
+
Intel Apollolake support
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_6 || console || bool || 6: INFO ||  
+
| SOC_INTEL_GLK || soc/intel/apollolake || bool || ||  
Informational messages.
+
Intel GLK support
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_5 || console || bool || 5: NOTICE ||  
+
| TPM_ON_FAST_SPI || soc/intel/apollolake || bool || ||  
Normal but significant conditions.
+
TPM part is conntected on Fast SPI interface, but the LPC MMIO
 +
TPM transactions are decoded and serialized over the SPI interface.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_4 || console || bool || 4: WARNING ||  
+
| PCR_BASE_ADDRESS || soc/intel/apollolake || hex || ||  
Warning conditions.
+
This option allows you to select MMIO Base Address of sideband bus.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_3 || console || bool || 3: ERR ||  
+
| DCACHE_RAM_SIZE || soc/intel/apollolake || hex || ||  
Error conditions.
+
The size of the cache-as-ram region required during bootblock
 +
and/or romstage.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_2 || console || bool || 2: CRIT ||  
+
| DCACHE_BSP_STACK_SIZE || soc/intel/apollolake || hex || ||  
Critical conditions.
+
The amount of anticipated stack usage in CAR by bootblock and
 +
other stages.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_1 || console || bool || 1: ALERT ||  
+
| ROMSTAGE_ADDR || soc/intel/apollolake || hex || ||  
Action must be taken immediately.
+
The base address (in CAR) where romstage should be linked
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL_0 || console || bool || 0: EMERG ||  
+
| VERSTAGE_ADDR || soc/intel/apollolake || hex || ||  
System is unusable.
+
The base address (in CAR) where verstage should be linked
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MAXIMUM_CONSOLE_LOGLEVEL || console || int ||  ||  
+
| FSP_M_ADDR || soc/intel/apollolake || hex ||  ||  
Map the log level config names to an integer.
+
The address FSP-M will be relocated to during build time
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_8 || console || bool || 8: SPEW ||  
+
| NEED_LBP2 || soc/intel/apollolake || bool || Write contents for logical boot partition 2. ||  
Way too many details.
+
Write the contents from a file into the logical boot partition 2
 +
region defined by LBP2_FMAP_NAME.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_7 || console || bool || 7: DEBUG ||  
+
| LBP2_FMAP_NAME || soc/intel/apollolake || string || Name of FMAP region to put logical boot partition 2 ||  
Debug-level messages.
+
Name of FMAP region to write logical boot partition 2 data.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_6 || console || bool || 6: INFO ||  
+
| LBP2_FILE_NAME || soc/intel/apollolake || string || Path of file to write to logical boot partition 2 region ||  
Informational messages.
+
Name of file to store in the logical boot partition 2 region.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_5 || console || bool || 5: NOTICE ||  
+
| NEED_IFWI || soc/intel/apollolake || bool || Write content into IFWI region ||  
Normal but significant conditions.
+
Write the content from a file into IFWI region defined by
 +
IFWI_FMAP_NAME.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_4 || console || bool || 4: WARNING ||  
+
| IFWI_FMAP_NAME || soc/intel/apollolake || string || Name of FMAP region to pull IFWI into ||  
Warning conditions.
+
Name of FMAP region to write IFWI.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_3 || console || bool || 3: ERR ||  
+
| IFWI_FILE_NAME || soc/intel/apollolake || string || Path of file to write to IFWI region ||  
Error conditions.
+
Name of file to store in the IFWI region.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_2 || console || bool || 2: CRIT ||  
+
| NHLT_DMIC_1CH_16B || soc/intel/apollolake || bool || ||  
Critical conditions.
+
Include DSP firmware settings for 1 channel 16B DMIC array.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_1 || console || bool || 1: ALERT ||  
+
| NHLT_DMIC_2CH_16B || soc/intel/apollolake || bool || ||  
Action must be taken immediately.
+
Include DSP firmware settings for 2 channel 16B DMIC array.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_0 || console || bool || 0: EMERG ||  
+
| NHLT_DMIC_4CH_16B || soc/intel/apollolake || bool || ||  
System is unusable.
+
Include DSP firmware settings for 4 channel 16B DMIC array.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL || console || int ||  ||  
+
| NHLT_MAX98357 || soc/intel/apollolake || bool ||  ||  
Map the log level config names to an integer.
+
Include DSP firmware settings for headset codec.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_POST || console || bool || Show POST codes on the debug console ||  
+
| NHLT_DA7219 || soc/intel/apollolake || bool || ||  
If enabled, coreboot will additionally print POST codes (which are
+
Include DSP firmware settings for headset codec.
usually displayed using a so-called "POST card" ISA/PCI/PCI-E
 
device) on the debug console.
 
  
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| NHLT_RT5682 || soc/intel/apollolake || bool ||  ||
 +
Include DSP firmware settings for headset codec.
  
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HAVE_HARD_RESET || toplevel || bool || ||  
+
| NHLT_RT5682 || soc/intel/apollolake || bool || Cache-as-ram implementation ||  
This variable specifies whether a given board has a hard_reset
+
This option allows you to select how cache-as-ram (CAR) is set up.
function, no matter if it's provided by board code or chipset code.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HAVE_OPTION_TABLE || toplevel || bool || ||  
+
| CAR_NEM || soc/intel/apollolake || bool || Non-evict mode ||  
This variable specifies whether a given board has a cmos.layout
+
Traditionally, CAR is set up by using Non-Evict mode. This method
file containing NVRAM/CMOS bit definitions.
+
does not allow CAR and cache to co-exist, because cache fills are
It defaults to 'n' but can be selected in mainboard/*/Kconfig.
+
block in NEM mode.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VGA || toplevel || bool || ||  
+
| CAR_CQOS || soc/intel/apollolake || bool || Cache Quality of Service ||  
Build board-specific VGA code.
+
Cache Quality of Service allows more fine-grained control of cache
 +
usage. As result, it is possible to set up portion of L2 cache for
 +
CAR and use remainder for actual caching.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| GFXUMA || toplevel || bool || ||  
+
| USE_APOLLOLAKE_FSP_CAR || soc/intel/apollolake || bool || Use FSP CAR ||  
Enable Unified Memory Architecture for graphics.
+
Use FSP APIs to initialize & tear down the Cache-As-Ram.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HAVE_ACPI_TABLES || toplevel || bool ||  ||  
+
| APL_SKIP_SET_POWER_LIMITS || soc/intel/apollolake || bool ||  ||  
This variable specifies whether a given board has ACPI table support.
+
Some Apollo Lake mainboards do not need the Running Average Power
It is usually set in mainboard/*/Kconfig.
+
Limits (RAPL) algorithm for a constant power management.
Whether or not the ACPI tables are actually generated by coreboot
+
Set this config option to skip the RAPL configuration.
is configurable by the user via GENERATE_ACPI_TABLES.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HAVE_MP_TABLE || toplevel || bool ||  ||  
+
| SOC_ESPI || soc/intel/apollolake || bool ||  ||  
This variable specifies whether a given board has MP table support.
+
Use eSPI bus instead of LPC
It is usually set in mainboard/*/Kconfig.
 
Whether or not the MP table is actually generated by coreboot
 
is configurable by the user via GENERATE_MP_TABLE.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HAVE_PIRQ_TABLE || toplevel || bool ||  ||  
+
| SOC_INTEL_BAYTRAIL || soc/intel/baytrail || bool ||  ||  
This variable specifies whether a given board has PIRQ table support.
+
Bay Trail M/D part support.
It is usually set in mainboard/*/Kconfig.
 
Whether or not the PIRQ table is actually generated by coreboot
 
is configurable by the user via GENERATE_PIRQ_TABLE.
 
  
 
||
 
||
|- bgcolor="#6699dd"
 
! align="left" | Menu: System tables || || || ||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| GENERATE_ACPI_TABLES || toplevel || bool || Generate ACPI tables ||  
+
| HAVE_MRC || soc/intel/baytrail || bool || Add a Memory Reference Code binary ||  
Generate ACPI tables for this board.
+
Select this option to add a blob containing
 +
memory reference code.
 +
Note: Without this binary coreboot will not work
  
If unsure, say Y.
+
||
 +
|- bgcolor="#eeeeee"
 +
| MRC_FILE || soc/intel/baytrail || string || Intel memory refeference code path and filename ||
 +
The path and filename of the file to use as System Agent
 +
binary. Note that this points to the sandybridge binary file
 +
which is will not work, but it serves its purpose to do builds.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| GENERATE_MP_TABLE || toplevel || bool || Generate an MP table ||  
+
| DCACHE_RAM_SIZE || soc/intel/baytrail || hex || ||  
Generate an MP table (conforming to the Intel MultiProcessor
+
The size of the cache-as-ram region required during bootblock
specification 1.4) for this board.
+
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
 +
must add up to a power of 2.
  
If unsure, say Y.
+
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_RAM_MRC_VAR_SIZE || soc/intel/baytrail || hex ||  ||
 +
The amount of cache-as-ram region required by the reference code.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| GENERATE_PIRQ_TABLE || toplevel || bool || Generate a PIRQ table ||  
+
| RESET_ON_INVALID_RAMSTAGE_CACHE || soc/intel/baytrail || bool || Reset the system on S3 wake when ramstage cache invalid. ||  
Generate a PIRQ table for this board.
+
The baytrail romstage code caches the loaded ramstage program
 +
in SMM space. On S3 wake the romstage will copy over a fresh
 +
ramstage that was cached in the SMM space. This option determines
 +
the action to take when the ramstage cache is invalid. If selected
 +
the system will reset otherwise the ramstage will be reloaded from
 +
cbfs.
  
If unsure, say Y.
+
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_BUILTIN_COM1 || soc/intel/baytrail || bool || Enable builtin COM1 Serial Port ||
 +
The PMC has a legacy COM1 serial port. Choose this option to
 +
configure the pads and enable it. This serial port can be used for
 +
the debug console.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| GENERATE_SMBIOS_TABLES || toplevel || bool || Generate SMBIOS tables ||  
+
| HAVE_REFCODE_BLOB || soc/intel/baytrail || bool || An external reference code blob should be put into cbfs. ||  
Generate SMBIOS tables for this board.
+
The reference code blob will be placed into cbfs.
 
 
If unsure, say Y.
 
  
 
||
 
||
 
|- bgcolor="#6699dd"
 
! align="left" | Menu: Payload || || || ||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PAYLOAD_NONE || toplevel || bool || None ||  
+
| REFCODE_BLOB_FILE || soc/intel/baytrail || string || Path and filename to reference code blob. ||  
Select this option if you want to create an "empty" coreboot
+
The path and filename to the file to be added to cbfs.
ROM image for a certain mainboard, i.e. a coreboot ROM image
 
which does not yet contain a payload.
 
 
 
For such an image to be useful, you have to use 'cbfstool'
 
to add a payload to the ROM image later.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PAYLOAD_ELF || toplevel || bool || An ELF executable payload ||  
+
| SOC_INTEL_BRASWELL || soc/intel/braswell || bool || ||  
Select this option if you have a payload image (an ELF file)
+
Braswell M/D part support.
which coreboot should run as soon as the basic hardware
 
initialization is completed.
 
 
 
You will be able to specify the location and file name of the
 
payload image later.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PAYLOAD_SEABIOS || toplevel || bool || SeaBIOS ||  
+
| DCACHE_RAM_SIZE || soc/intel/braswell || hex || ||  
Select this option if you want to build a coreboot image
+
The size of the cache-as-ram region required during bootblock
with a SeaBIOS payload. If you don't know what this is
+
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
about, just leave it enabled.
+
must add up to a power of 2.
 
 
See http://coreboot.org/Payloads for more information.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PAYLOAD_FILO || toplevel || bool || FILO ||  
+
| RESET_ON_INVALID_RAMSTAGE_CACHE || soc/intel/braswell || bool || Reset the system on S3 wake when ramstage cache invalid. ||  
Select this option if you want to build a coreboot image
+
The haswell romstage code caches the loaded ramstage program
with a FILO payload. If you don't know what this is
+
in SMM space. On S3 wake the romstage will copy over a fresh
about, just leave it enabled.
+
ramstage that was cached in the SMM space. This option determines
 
+
the action to take when the ramstage cache is invalid. If selected
See http://coreboot.org/Payloads for more information.
+
the system will reset otherwise the ramstage will be reloaded from
 +
cbfs.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SEABIOS_STABLE || toplevel || bool || stable ||  
+
| ENABLE_BUILTIN_COM1 || soc/intel/braswell || bool || Enable builtin COM1 Serial Port ||  
Stable SeaBIOS version
+
The PMC has a legacy COM1 serial port. Choose this option to
 +
configure the pads and enable it. This serial port can be used for
 +
the debug console.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SEABIOS_MASTER || toplevel || bool || master ||  
+
| SOC_INTEL_BROADWELL || soc/intel/broadwell || bool || ||  
Newest SeaBIOS version
+
Intel Broadwell and Haswell ULT support.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FILO_STABLE || toplevel || bool || 0.6.0 ||
+
| DCACHE_RAM_SIZE || soc/intel/broadwell || hex || ||
Stable FILO version
+
The size of the cache-as-ram region required during bootblock
 +
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
 +
must add up to a power of 2.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FILO_MASTER || toplevel || bool || HEAD ||  
+
| DCACHE_RAM_MRC_VAR_SIZE || soc/intel/broadwell || hex || ||  
Newest FILO version
+
The amount of cache-as-ram region required by the reference code.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PAYLOAD_FILE || toplevel || string || Payload path and filename ||  
+
| HAVE_MRC || soc/intel/broadwell || bool || Add a Memory Reference Code binary ||  
The path and filename of the ELF executable file to use as payload.
+
Select this option to add a Memory Reference Code binary to
 +
the resulting coreboot image.
  
||
+
Note: Without this binary coreboot will not work
 +
 
 +
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COMPRESSED_PAYLOAD_LZMA || toplevel || bool || Use LZMA compression for payloads ||  
+
| MRC_FILE || soc/intel/broadwell || string || Intel Memory Reference Code path and filename ||  
In order to reduce the size payloads take up in the ROM chip
+
The filename of the file to use as Memory Reference Code binary.
coreboot can compress them using the LZMA algorithm.
 
  
 
||
 
||
 
|- bgcolor="#6699dd"
 
! align="left" | Menu: VGA BIOS || || || ||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VGA_BIOS || toplevel || bool || Add a VGA BIOS image ||  
+
| PRE_GRAPHICS_DELAY || soc/intel/broadwell || int || Graphics initialization delay in ms ||  
Select this option if you have a VGA BIOS image that you would
+
On some systems, coreboot boots so fast that connected monitors
like to add to your ROM.
+
(mostly TVs) won't be able to wake up fast enough to talk to the
 
+
VBIOS. On those systems we need to wait for a bit before executing
You will be able to specify the location and file name of the
+
the VBIOS.
image later.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VGA_BIOS_FILE || toplevel || string || VGA BIOS path and filename ||  
+
| RESET_ON_INVALID_RAMSTAGE_CACHE || soc/intel/broadwell || bool || Reset the system on S3 wake when ramstage cache invalid. ||  
The path and filename of the file to use as VGA BIOS.
+
The romstage code caches the loaded ramstage program in SMM space.
 +
On S3 wake the romstage will copy over a fresh ramstage that was
 +
cached in the SMM space. This option determines the action to take
 +
when the ramstage cache is invalid. If selected the system will
 +
reset otherwise the ramstage will be reloaded from cbfs.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VGA_BIOS_ID || toplevel || string || VGA device PCI IDs ||  
+
| SERIRQ_CONTINUOUS_MODE || soc/intel/broadwell || bool || ||  
The comma-separated PCI vendor and device ID that would associate
+
If you set this option to y, the serial IRQ machine will be
your VGA BIOS to your video card.
+
operated in continuous mode.
 
 
Example: 1106,3230
 
 
 
In the above example 1106 is the PCI vendor ID (in hex, but without
 
the "0x" prefix) and 3230 specifies the PCI device ID of the
 
video card (also in hex, without "0x" prefix).
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| INTEL_MBI || toplevel || bool || Add an MBI image ||  
+
| HAVE_REFCODE_BLOB || soc/intel/broadwell || bool || An external reference code blob should be put into cbfs. ||  
Select this option if you have an Intel MBI image that you would
+
The reference code blob will be placed into cbfs.
like to add to your ROM.
 
 
 
You will be able to specify the location and file name of the
 
image later.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MBI_FILE || toplevel || string || Intel MBI path and filename ||  
+
| REFCODE_BLOB_FILE || soc/intel/broadwell || string || Path and filename to reference code blob. ||  
The path and filename of the file to use as VGA BIOS.
+
The path and filename to the file to be added to cbfs.
  
 
||
 
||
 
|- bgcolor="#6699dd"
 
! align="left" | Menu: Display || || || ||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FRAMEBUFFER_SET_VESA_MODE || toplevel || bool || Set VESA framebuffer mode ||  
+
| SOC_INTEL_CANNONLAKE || soc/intel/cannonlake || bool || ||  
Set VESA framebuffer mode (needed for bootsplash)
+
Intel Cannonlake support
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FRAMEBUFFER_VESA_MODE || toplevel || hex || VESA framebuffer video mode ||  
+
| UART_FOR_CONSOLE || soc/intel/cannonlake || int || Index for LPSS UART port to use for console ||  
This option sets the resolution used for the coreboot framebuffer (and
+
Index for LPSS UART port to use for console:
bootsplash screen). Set to 0x117 for 1024x768x16. A diligent soul will
+
0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
some day make this a "choice".
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FRAMEBUFFER_KEEP_VESA_MODE || toplevel || bool || Keep VESA framebuffer ||  
+
| DCACHE_RAM_SIZE || soc/intel/cannonlake || int || ||  
This option keeps the framebuffer mode set after coreboot finishes
+
The size of the cache-as-ram region required during bootblock
execution. If this option is enabled, coreboot will pass a
+
and/or romstage.
framebuffer entry in its coreboot table and the payload will need a
 
framebuffer driver. If this option is disabled, coreboot will switch
 
back to text mode before handing control to a payload.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOOTSPLASH || toplevel || bool || Show graphical bootsplash ||  
+
| DCACHE_BSP_STACK_SIZE || soc/intel/cannonlake || hex || ||  
This option shows a graphical bootsplash screen. The grapics are
+
The amount of anticipated stack usage in CAR by bootblock and
loaded from the CBFS file bootsplash.jpg.
+
other stages.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOOTSPLASH_FILE || toplevel || string || Bootsplash path and filename ||  
+
| NHLT_DMIC_1CH_16B || soc/intel/cannonlake || bool || ||  
The path and filename of the file to use as graphical bootsplash
+
Include DSP firmware settings for 1 channel 16B DMIC array.
screen. The file format has to be jpg.
+
 
 
||
 
||
 +
|- bgcolor="#eeeeee"
 +
| NHLT_DMIC_2CH_16B || soc/intel/cannonlake || bool ||  ||
 +
Include DSP firmware settings for 2 channel 16B DMIC array.
  
|- bgcolor="#6699dd"
+
||
! align="left" | Menu: Debugging || || || ||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| GDB_STUB || toplevel || bool || GDB debugging support ||  
+
| NHLT_DMIC_4CH_16B || soc/intel/cannonlake || bool || ||  
If enabled, you will be able to set breakpoints for gdb debugging.
+
Include DSP firmware settings for 4 channel 16B DMIC array.
See src/arch/x86/lib/c_start.S for details.
 
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DEBUG_RAM_SETUP || toplevel || bool || Output verbose RAM init debug messages ||  
+
| NHLT_MAX98357 || soc/intel/cannonlake || bool || ||  
This option enables additional RAM init related debug messages.
+
Include DSP firmware settings for headset codec.
It is recommended to enable this when debugging issues on your
 
board which might be RAM init related.
 
  
Note: This option will increase the size of the coreboot image.
+
||
 +
|- bgcolor="#eeeeee"
 +
| NHLT_MAX98373 || soc/intel/cannonlake || bool ||  ||
 +
Include DSP firmware settings for headset codec.
  
If unsure, say N.
+
||
 +
|- bgcolor="#eeeeee"
 +
| NHLT_DA7219 || soc/intel/cannonlake || bool ||  ||
 +
Include DSP firmware settings for headset codec.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DEBUG_CAR || toplevel || bool || Output verbose Cache-as-RAM debug messages ||  
+
| PCR_BASE_ADDRESS || soc/intel/cannonlake || hex || ||  
This option enables additional CAR related debug messages.
+
This option allows you to select MMIO Base Address of sideband bus.
 +
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DEBUG_PIRQ || toplevel || bool || Check PIRQ table consistency ||  
+
| STACK_SIZE || soc/intel/cannonlake || hex || Cache-as-ram implementation ||  
If unsure, say N.
+
This option allows you to select how cache-as-ram (CAR) is set up.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DEBUG_SMBUS || toplevel || bool || Output verbose SMBus debug messages ||  
+
| USE_CANNONLAKE_CAR_NEM_ENHANCED || soc/intel/cannonlake || bool || Enhanced Non-evict mode ||  
This option enables additional SMBus (and SPD) debug messages.
+
A current limitation of NEM (Non-Evict mode) is that code and data
 +
sizes are derived from the requirement to not write out any modified
 +
cache line. With NEM, if there is no physical memory behind the
 +
cached area, the modified data will be lost and NEM results will be
 +
inconsistent. ENHANCED NEM guarantees that modified data is always
 +
kept in cache while clean data is replaced.
  
Note: This option will increase the size of the coreboot image.
+
||
 +
|- bgcolor="#eeeeee"
 +
| USE_CANNONLAKE_FSP_CAR || soc/intel/cannonlake || bool || Use FSP CAR ||
 +
Use FSP APIs to initialize and tear down the Cache-As-Ram.
  
If unsure, say N.
+
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_DENVERTON_NS || soc/intel/denverton_ns || bool ||  ||
 +
Intel Denverton-NS SoC support
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DEBUG_SMI || toplevel || bool || Output verbose SMI debug messages ||  
+
| FSP_T_ADDR || soc/intel/denverton_ns || hex || Intel FSP-T (temp ram init) binary location ||  
This option enables additional SMI related debug messages.
+
The memory location of the Intel FSP-T binary for this platform.
  
Note: This option will increase the size of the coreboot image.
+
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_M_ADDR || soc/intel/denverton_ns || hex || Intel FSP-M (memory init) binary location ||
 +
The memory location of the Intel FSP-M binary for this platform.
  
If unsure, say N.
+
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_S_ADDR || soc/intel/denverton_ns || hex || Intel FSP-S (silicon init) binary location ||
 +
The memory location of the Intel FSP-S binary for this platform.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DEBUG_SMM_RELOCATION || toplevel || bool || Debug SMM relocation code ||  
+
| PCR_BASE_ADDRESS || soc/intel/denverton_ns || hex || ||  
This option enables additional SMM handler relocation related
+
This option allows you to select MMIO Base Address of sideband bus.
debug messages.
 
  
Note: This option will increase the size of the coreboot image.
+
||
 +
|- bgcolor="#eeeeee"
 +
| IQAT_MEMORY_REGION_SIZE || soc/intel/denverton_ns || hex ||  ||
 +
Do not change this value
  
If unsure, say N.
+
||
 +
|- bgcolor="#eeeeee"
 +
| NON_LEGACY_UART_MODE || soc/intel/denverton_ns || bool || Non Legacy Mode ||
 +
Disable legacy UART mode
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DEBUG_MALLOC || toplevel || bool || Output verbose malloc debug messages ||  
+
| LEGACY_UART_MODE || soc/intel/denverton_ns || bool || Legacy Mode ||  
This option enables additional malloc related debug messages.
+
Enable legacy UART mode
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DENVERTON_NS_CAR_NEM_ENHANCED || soc/intel/denverton_ns || bool || Enhanced Non-evict mode ||
 +
A current limitation of NEM (Non-Evict mode) is that code and data sizes
 +
are derived from the requirement to not write out any modified cache line.
 +
With NEM, if there is no physical memory behind the cached area,
 +
the modified data will be lost and NEM results will be inconsistent.
 +
ENHANCED NEM guarantees that modified data is always
 +
kept in cache while clean data is replaced.
  
Note: This option will increase the size of the coreboot image.
+
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_FSP_BAYTRAIL || soc/intel/fsp_baytrail || bool ||  ||
 +
Bay Trail I part support using the Intel FSP.
  
If unsure, say N.
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DEBUG_ACPI || toplevel || bool || Output verbose ACPI debug messages ||  
+
| SMM_TSEG_SIZE || soc/intel/fsp_baytrail || hex || ||  
This option enables additional ACPI related debug messages.
+
This is set by the FSP
  
Note: This option will slightly increase the size of the coreboot image.
+
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_ID || soc/intel/fsp_baytrail || string ||  ||
 +
This is the default PCI ID for the Bay Trail graphics
 +
devices.  This string names the vbios ROM in cbfs.
  
If unsure, say N.
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| REALMODE_DEBUG || toplevel || bool || Enable debug messages for option ROM execution ||  
+
| ENABLE_BUILTIN_COM1 || soc/intel/fsp_baytrail || bool || Enable built-in legacy Serial Port ||  
This option enables additional x86emu related debug messages.
+
The Baytrail SOC has one legacy serial port. Choose this option to
 +
configure the pads and enable it. This serial port can be used for
 +
the debug console.
  
Note: This option will increase the time to emulate a ROM.
+
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_FILE || soc/intel/fsp_baytrail/fsp || string ||  ||
 +
The path and filename of the Intel FSP binary for this platform.
  
If unsure, say N.
 
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| X86EMU_DEBUG || toplevel || bool || Output verbose x86emu debug messages ||  
+
| FSP_LOC || soc/intel/fsp_baytrail/fsp || hex || ||  
This option enables additional x86emu related debug messages.
+
The location in CBFS that the FSP is located. This must match the
 +
value that is set in the FSP binary.  If the FSP needs to be moved,
 +
rebase the FSP with Intel's BCT (tool).
  
Note: This option will increase the size of the coreboot image.
+
The Bay Trail FSP is built with a preferred base address of
 +
0xFFFC0000.
  
If unsure, say N.
+
||
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_JMP || toplevel || bool || Trace JMP/RETF ||  
+
| SOC_INTEL_FSP_BROADWELL_DE || soc/intel/fsp_broadwell_de || bool || ||  
Print information about JMP and RETF opcodes from x86emu.
+
Broadwell-DE support using the Intel FSP.
  
Note: This option will increase the size of the coreboot image.
+
||
 +
|- bgcolor="#eeeeee"
 +
| INTEGRATED_UART || soc/intel/fsp_broadwell_de || bool || Integrated UART ports ||
 +
Use Broadwell-DE Integrated UART ports @3F8h and 2F8h.
  
If unsure, say N.
+
||
 +
|- bgcolor="#eeeeee"
 +
| SERIRQ_CONTINUOUS_MODE || soc/intel/fsp_broadwell_de || bool ||  ||
 +
If you set this option to y, the serial IRQ machine will be
 +
operated in continuous mode.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_TRACE || toplevel || bool || Trace all opcodes ||  
+
| FSP_FILE || soc/intel/fsp_broadwell_de/fsp || string || ||  
Print _all_ opcodes that are executed by x86emu.
+
The path and filename of the Intel FSP binary for this platform.
  
WARNING: This will produce a LOT of output and take a long time.
+
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_LOC || soc/intel/fsp_broadwell_de/fsp || hex ||  ||
 +
The location in CBFS that the FSP is located. This must match the
 +
value that is set in the FSP binary.  If the FSP needs to be moved,
 +
rebase the FSP with Intel's BCT (tool).
  
Note: This option will increase the size of the coreboot image.
+
The Broadwell-DE FSP is built with a preferred base address of
 +
0xffeb0000.
  
If unsure, say N.
+
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_RAM_BASE || soc/intel/fsp_broadwell_de/fsp || hex ||  ||
 +
This address needs to match the setup performed inside FSP.
 +
On Broadwell-DE the FSP allocates temporary RAM starting at 0xfe100000.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_PNP || toplevel || bool || Log Plug&Play accesses ||  
+
| DCACHE_RAM_SIZE || soc/intel/fsp_broadwell_de/fsp || hex || ||  
Print Plug And Play accesses made by option ROMs.
+
The DCACHE is shared between FSP itself and the rest of the coreboot
 +
stages. A size of 0x8000 works fine while providing enough space for
 +
features like VBOOT in verstage. Further increase to a power of two
 +
aligned value leads to errors in FSP.
  
Note: This option will increase the size of the coreboot image.
+
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_MEMORY_DOWN || soc/intel/fsp_broadwell_de/fsp || bool || Enable Memory Down ||
 +
Load SPD data from ROM instead of trying to read from SMBus.
  
If unsure, say N.
+
If the platform has DIMM sockets, say N. If memory is down, say Y and
 +
supply the appropriate SPD data for each Channel/DIMM.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_DISK || toplevel || bool || Log Disk I/O ||  
+
| FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT || soc/intel/fsp_broadwell_de/fsp || bool || Channel 0, DIMM 0 Present ||  
Print Disk I/O related messages.
+
Select Y if Channel 0, DIMM 0 is present.
  
Note: This option will increase the size of the coreboot image.
+
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_MEMORY_DOWN_CH0DIMM0_SPD_FILE || soc/intel/fsp_broadwell_de/fsp || string || Channel 0, DIMM 0 SPD File ||
 +
Path to the file which contains the SPD data for Channel 0, DIMM 0.
  
If unsure, say N.
+
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT || soc/intel/fsp_broadwell_de/fsp || bool || Channel 0, DIMM 1 Present ||
 +
Select Y if Channel 0, DIMM 1 is present.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_PMM || toplevel || bool || Log PMM ||  
+
| FSP_MEMORY_DOWN_CH0DIMM1_SPD_FILE || soc/intel/fsp_broadwell_de/fsp || string || Channel 0, DIMM 1 SPD File ||  
Print messages related to POST Memory Manager (PMM).
+
Path to the file which contains the SPD data for Channel 0, DIMM 1.
  
Note: This option will increase the size of the coreboot image.
+
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT || soc/intel/fsp_broadwell_de/fsp || bool || Channel 1, DIMM 0 Present ||
 +
Select Y if Channel 1, DIMM 0 is present.
  
If unsure, say N.
+
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_MEMORY_DOWN_CH1DIMM0_SPD_FILE || soc/intel/fsp_broadwell_de/fsp || string || Channel 1, DIMM 0 SPD File ||
 +
Path to the file which contains the SPD data for Channel 1, DIMM 0.
  
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT || soc/intel/fsp_broadwell_de/fsp || bool || Channel 1, DIMM 1 Present ||
 +
Select Y if Channel 1, DIMM 1 is present.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_VBE || toplevel || bool || Debug VESA BIOS Extensions ||  
+
| FSP_MEMORY_DOWN_CH1DIMM1_SPD_FILE || soc/intel/fsp_broadwell_de/fsp || string || Channel 1, DIMM 1 SPD File ||  
Print messages related to VESA BIOS Extension (VBE) functions.
+
Path to the file which contains the SPD data for Channel 1, DIMM 1.
  
Note: This option will increase the size of the coreboot image.
+
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_HYPERTHREADING || soc/intel/fsp_broadwell_de/fsp || bool || Enable Hyper-Threading ||
 +
Enable Intel(r) Hyper-Threading Technology for the Broadwell-DE SoC.
  
If unsure, say N.
+
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_EHCI1_ENABLE || soc/intel/fsp_broadwell_de/fsp || bool || EHCI1 Enable ||
 +
Enable EHCI controller 1
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_INT10 || toplevel || bool || Redirect INT10 output to console ||  
+
| FSP_EHCI2_ENABLE || soc/intel/fsp_broadwell_de/fsp || bool || EHCI2 Enable ||  
Let INT10 (i.e. character output) calls print messages to debug output.
+
Enable EHCI controller 2
  
Note: This option will increase the size of the coreboot image.
+
||
  
If unsure, say N.
+
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_QUARK || soc/intel/quark || bool ||  ||
 +
Intel Quark support
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_INTERRUPTS || toplevel || bool || Log intXX calls ||  
+
| ENABLE_BUILTIN_HSUART0 || soc/intel/quark || bool || Enable built-in HSUART0 ||  
Print messages related to interrupt handling.
+
The Quark SoC has two HSUART. Choose this option to configure the pads
 +
and enable HSUART0, which can be used for the debug console.
  
Note: This option will increase the size of the coreboot image.
+
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_BUILTIN_HSUART1 || soc/intel/quark || bool || Enable built-in HSUART1 ||
 +
The Quark SoC has two HSUART. Choose this option to configure the pads
 +
and enable HSUART1, which can be used for the debug console.
  
If unsure, say N.
+
||
 +
|- bgcolor="#eeeeee"
 +
| TTYS0_BASE || soc/intel/quark || hex || HSUART Base Address ||
 +
Memory mapped MMIO of HSUART.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_DEBUG_LED || soc/intel/quark || bool ||  ||
 +
Enable the use of the SD LED for early debugging before serial output
 +
is available.  Setting this LED indicates that control has reached the
 +
desired check point.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_DEBUG_LED_ESRAM || soc/intel/quark || bool || SD LED indicates ESRAM initialized ||
 +
Indicate that ESRAM has been successfully initialized.  If the SD LED
 +
does not light then the ESRAM initialization needs to be debugged.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_DEBUG_LED_FINDFSP || soc/intel/quark || bool || SD LED indicates fsp.bin file was found ||
 +
Indicate that fsp.bin was found.  If the SD LED does not light then
 +
the code between ESRAM initialization through find_fsp needs to
 +
debugged.  Start by verifying that the correct fsp.bin is in the
 +
image.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_CHECK_VMEM_ACCESS || toplevel || bool || Log special memory accesses ||  
+
| ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY || soc/intel/quark || bool || SD LED indicates bootblock.c successfully entered ||  
Print messages related to accesses to certain areas of the virtual
+
Indicate that bootblock_c_entry was entered.  If the SD LED does not
memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
+
light then debug the code between ESRAM and bootblock_c_entry.  For
 +
FSP 1.1, use ENABLE_DEBUG_LED_FINDFSP to split this code.
  
Note: This option will increase the size of the coreboot image.
+
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY || soc/intel/quark || bool || SD LED indicates bootblock_soc_early_init successfully entered ||
 +
Indicate that bootblock_soc_early_init was entered.  If the SD LED
 +
does not light then debug the code in bootblock_main_with_timestamp.
  
If unsure, say N.
+
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_DEBUG_LED_SOC_EARLY_INIT_EXIT || soc/intel/quark || bool || SD LED indicates bootblock_soc_early_init successfully exited ||
 +
Indicate that bootblock_soc_early_init exited.  If the SD LED does not
 +
light then debug the scripts in bootblock_soc_early_init.
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_MEM || toplevel || bool || Log all memory accesses ||  
+
| ENABLE_DEBUG_LED_SOC_INIT_ENTRY || soc/intel/quark || bool || SD LED indicates bootblock_soc_init successfully entered ||  
Print memory accesses made by option ROM.
+
Indicate that bootblock_soc_init was entered. If the SD LED does not
Note: This also includes accesses to fetch instructions.
+
light then debug the code in bootblock_mainboard_early_init and
 +
console_init.  If the SD LED does light but there is no serial then
 +
debug the serial port configuration and initialization.
  
Note: This option will increase the size of the coreboot image.
+
||
 +
|- bgcolor="#eeeeee"
 +
| DISPLAY_ESRAM_LAYOUT || soc/intel/quark || bool || Display ESRAM layout ||
 +
Select this option to display coreboot's use of ESRAM.
  
If unsure, say N.
+
||
 +
|- bgcolor="#eeeeee"
 +
| CBFS_SIZE || soc/intel/quark || hex ||  ||
 +
Specify the size of the coreboot file system in the read-only (recovery)
 +
portion of the flash part.  On Quark systems the firmware image stores
 +
more than just coreboot, including:
 +
- The chipset microcode (RMU) binary file located at 0xFFF00000
 +
- Intel Trusted Execution Engine firmware
  
 
||
 
||
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| X86EMU_DEBUG_IO || toplevel || bool || Log IO accesses ||  
+
| ADD_FSP_RAW_BIN || soc/intel/quark || bool || Add the Intel FSP binary to the flash image without relocation ||
 +
Select this option to add an Intel FSP binary to
 +
the resulting coreboot image.
 +
 
 +
Note: Without this binary, coreboot builds relying on the FSP
 +
will not boot
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_FILE || soc/intel/quark || string || Intel FSP binary path and filename ||
 +
The path and filename of the Intel FSP binary for this platform.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_LOC || soc/intel/quark || hex ||  ||
 +
The location in CBFS that the FSP is located. This must match the
 +
value that is set in the FSP binary.  If the FSP needs to be moved,
 +
rebase the FSP with Intel's BCT (tool).
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_ESRAM_LOC || soc/intel/quark || hex ||  ||
 +
The location in ESRAM where a copy of the FSP binary is placed.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RELOCATE_FSP_INTO_DRAM || soc/intel/quark || bool || Relocate FSP into DRAM ||
 +
Relocate the FSP binary into DRAM before the call to SiliconInit.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ADD_RMU_FILE || soc/intel/quark || bool || Should the RMU binary be added to the flash image? ||
 +
The RMU file is required to get the chip out of reset.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RMU_FILE || soc/intel/quark || string ||  ||
 +
The path and filename of the Intel Quark RMU binary.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RMU_LOC || soc/intel/quark || hex ||  ||
 +
The location in CBFS that the RMU is located. It must match the
 +
strap-determined base address.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| STORAGE_TEST || soc/intel/quark || bool || Test SD/MMC/eMMC card or device access ||
 +
Read block 0 from each parition of the storage device.  User
 +
must also enable one or both of COMMONLIB_STORAGE_SD or
 +
COMMONLIB_STORAGE_MMC.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| I2C_DEBUG || soc/intel/quark || bool || Enable I2C debugging ||
 +
Display the I2C segments and controller errors
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_SKYLAKE || soc/intel/skylake || bool ||  ||
 +
Intel Skylake support
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_KABYLAKE || soc/intel/skylake || bool ||  ||
 +
Intel Kabylake support
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_RAM_SIZE || soc/intel/skylake || hex ||  ||
 +
The size of the cache-as-ram region required during bootblock
 +
and/or romstage.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_BSP_STACK_SIZE || soc/intel/skylake || hex ||  ||
 +
The amount of anticipated stack usage in CAR by bootblock and
 +
other stages.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EXCLUDE_NATIVE_SD_INTERFACE || soc/intel/skylake || bool ||  ||
 +
If you set this option to n, will not use native SD controller.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PCR_BASE_ADDRESS || soc/intel/skylake || hex ||  ||
 +
This option allows you to select MMIO Base Address of sideband bus.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SERIRQ_CONTINUOUS_MODE || soc/intel/skylake || bool ||  ||
 +
If you set this option to y, the serial IRQ machine will be
 +
operated in continuous mode.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| UART_FOR_CONSOLE || soc/intel/skylake || int || Index for LPSS UART port to use for console ||
 +
Index for LPSS UART port to use for console:
 +
0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SKYLAKE_SOC_PCH_H || soc/intel/skylake || bool ||  ||
 +
Choose this option if you have a PCH-H chipset.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NHLT_DMIC_2CH || soc/intel/skylake || bool ||  ||
 +
Include DSP firmware settings for 2 channel DMIC array.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NHLT_DMIC_4CH || soc/intel/skylake || bool ||  ||
 +
Include DSP firmware settings for 4 channel DMIC array.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NHLT_NAU88L25 || soc/intel/skylake || bool ||  ||
 +
Include DSP firmware settings for nau88l25 headset codec.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NHLT_MAX98357 || soc/intel/skylake || bool ||  ||
 +
Include DSP firmware settings for max98357 amplifier.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NHLT_MAX98373 || soc/intel/skylake || bool ||  ||
 +
Include DSP firmware settings for max98373 amplifier.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NHLT_SSM4567 || soc/intel/skylake || bool ||  ||
 +
Include DSP firmware settings for ssm4567 smart amplifier.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NHLT_RT5514 || soc/intel/skylake || bool ||  ||
 +
Include DSP firmware settings for rt5514 DSP.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NHLT_RT5663 || soc/intel/skylake || bool ||  ||
 +
Include DSP firmware settings for rt5663 headset codec.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NHLT_MAX98927 || soc/intel/skylake || bool ||  ||
 +
Include DSP firmware settings for max98927 amplifier.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NHLT_DA7219 || soc/intel/skylake || bool ||  ||
 +
Include DSP firmware settings for DA7219 headset codec.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NHLT_DA7219 || soc/intel/skylake || bool || Cache-as-ram implementation ||
 +
This option allows you to select how cache-as-ram (CAR) is set up.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USE_SKYLAKE_CAR_NEM_ENHANCED || soc/intel/skylake || bool || Enhanced Non-evict mode ||
 +
A current limitation of NEM (Non-Evict mode) is that code and data
 +
sizes are derived from the requirement to not write out any modified
 +
cache line. With NEM, if there is no physical memory behind the
 +
cached area, the modified data will be lost and NEM results will be
 +
inconsistent. ENHANCED NEM guarantees that modified data is always
 +
kept in cache while clean data is replaced.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USE_SKYLAKE_FSP_CAR || soc/intel/skylake || bool || Use FSP CAR ||
 +
Use FSP APIs to initialize and tear down the Cache-As-Ram.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SKIP_FSP_CAR || soc/intel/skylake || bool || Skip cache as RAM setup in FSP ||
 +
Skip Cache as RAM setup in FSP.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NO_FADT_8042 || soc/intel/skylake || bool ||  ||
 +
Choose this option if you want to disable 8042 Keyboard
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON || soc/intel/common || bool ||  ||
 +
common code for Intel SOCs
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Intel SoC Common Code ||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK || soc/intel/common/block || bool ||  ||
 +
SoC driver for intel common IP code
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Intel SoC Common IP Code ||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_TIMER || soc/intel/common/block/timer || bool ||  ||
 +
Intel Processor common TIMER support
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_XDCI || soc/intel/common/block/xdci || bool ||  ||
 +
Intel Processor common XDCI support
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_SCS || soc/intel/common/block/scs || bool ||  ||
 +
Intel Processor common storage and communication subsystem support
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_SATA || soc/intel/common/block/sata || bool ||  ||
 +
Intel Processor common SATA support
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_AHCI_PORT_IMPLEMENTED_INVERT || soc/intel/common/block/sata || bool ||  ||
 +
SATA PCI configuration space offset 0x92 Port
 +
implement register bit 0-2 represents respective
 +
SATA port enable status as in 0 = Disable; 1 = Enable.
 +
If this option is selected then port enable status will be
 +
inverted as in 0 = Enable; 1 = Disable.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_LPC || soc/intel/common/block/lpc || bool ||  ||
 +
Use common LPC code for platform. Only soc specific code needs to
 +
be implemented as per requirement.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE || soc/intel/common/block/lpc || bool ||  ||
 +
By default COMA range to LPC is enable. COMB range to LPC is optional
 +
and should select based on platform dedicated selection.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_SPI || soc/intel/common/block/spi || bool ||  ||
 +
Intel Processor common SPI support
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_P2SB || soc/intel/common/block/p2sb || bool ||  ||
 +
Intel Processor common P2SB driver
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_SMM || soc/intel/common/block/smm || bool ||  ||
 +
Intel Processor common SMM support
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP || soc/intel/common/block/smm || bool ||  ||
 +
Intel Processor trap flag if it is supported
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS || soc/intel/common/block/smm || int ||  ||
 +
Time in milliseconds that SLP_SMI for S5 waits for before
 +
enabling sleep. This is required to avoid any race between
 +
SLP_SMI and PWRBTN SMI.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_SA || soc/intel/common/block/systemagent || bool ||  ||
 +
Intel Processor common System Agent support
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SA_PCIEX_LENGTH || soc/intel/common/block/systemagent || hex ||  ||
 +
This option allows you to select length of PCIEX region.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SA_ENABLE_IMR || soc/intel/common/block/systemagent || bool ||  ||
 +
This option allows you to add the isolated memory ranges (IMRs).
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SA_ENABLE_DPR || soc/intel/common/block/systemagent || bool ||  ||
 +
This option allows you to add the DMA Protected Range (DPR).
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_HDA || soc/intel/common/block/hda || bool ||  ||
 +
Intel Processor common High Definition Audio driver support
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_LPSS || soc/intel/common/block/lpss || bool ||  ||
 +
Intel Processor common LPSS support
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_FAST_SPI || soc/intel/common/block/fast_spi || bool ||  ||
 +
Intel Processor common FAST_SPI support
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FAST_SPI_DISABLE_WRITE_STATUS || soc/intel/common/block/fast_spi || bool || Disable write status SPI opcode ||
 +
Disable the write status SPI opcode in Intel Fast SPI block.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_UART || soc/intel/common/block/uart || bool ||  ||
 +
Intel Processor common UART support
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_M_VAL || soc/intel/common/block/uart || hex ||  ||
 +
Clock m-divisor value for m/n divider
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_N_VAL || soc/intel/common/block/uart || hex ||  ||
 +
Clock m-divisor value for m/n divider
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_GSPI || soc/intel/common/block/gspi || bool ||  ||
 +
Intel Processor Common GSPI support
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ || soc/intel/common/block/gspi || int ||  ||
 +
The input clock speed into the SPI controller IP block, in MHz.
 +
No default is set here as this is an SOC-specific value
 +
and must be provided by the SOC.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_GSPI_MAX || soc/intel/common/block/gspi || int ||  ||
 +
Maximum number of GSPI controllers supported by the PCH. SoC
 +
must define this config if SOC_INTEL_COMMON_BLOCK_GSPI is
 +
selected.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 || soc/intel/common/block/gspi || bool ||  ||
 +
Intel Processor Common GSPI support with quirks to handle
 +
SPI_CS_CONTROL changes introduced in CNL.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_XHCI || soc/intel/common/block/xhci || bool ||  ||
 +
Intel Processor common XHCI support
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_PCIE || soc/intel/common/block/pcie || bool ||  ||
 +
Intel Processor common PCIE support
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PCIE_DEBUG_INFO || soc/intel/common/block/pcie || bool ||  ||
 +
Enable debug logs in PCIe module. Allows debug information on memory
 +
base and limit, prefetchable memory base and limit, prefetchable memory
 +
base upper 32 bits and prefetchable memory limit upper 32 bits.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_PCR || soc/intel/common/block/pcr || bool ||  ||
 +
Intel Processor common Private configuration registers (PCR)
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PCR_COMMON_IOSF_1_0 || soc/intel/common/block/pcr || bool ||  ||
 +
The mapping of addresses via the SBREG_BAR assumes the IOSF-SB
 +
agents are using 32-bit aligned accesses for their configuration
 +
registers. For IOSF versions greater than 1_0, IOSF-SB
 +
agents can use any access (8/16/32 bit aligned) for their
 +
configuration registers
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_ACPI || soc/intel/common/block/acpi || bool ||  ||
 +
Intel Processor common code for ACPI
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_RTC || soc/intel/common/block/rtc || bool ||  ||
 +
Intel Processor common RTC support
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_CPU || soc/intel/common/block/cpu || bool ||  ||
 +
This option selects Intel Common CPU Model support code
 +
which provides various CPU related APIs which are common
 +
between all Intel Processor families. Common CPU code is supported
 +
for SOCs starting from SKL,KBL,APL, and future.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_CPU_MPINIT || soc/intel/common/block/cpu || bool ||  ||
 +
This option selects Intel Common CPU MP Init code. In
 +
this common MP Init mechanism, the MP Init is occurring before
 +
calling FSP Silicon Init. Hence, MP Init will be pulled to
 +
BS_DEV_INIT_CHIPS Entry. And on Exit of BS_DEV_INIT, it is
 +
ensured that all MTRRs are re-programmed based on the DRAM
 +
resource settings.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_CAR || soc/intel/common/block/cpu || bool ||  ||
 +
This option allows you to select how cache-as-ram (CAR) is set up.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| INTEL_CAR_NEM || soc/intel/common/block/cpu || bool ||  ||
 +
Traditionally, CAR is set up by using Non-Evict mode. This method
 +
does not allow CAR and cache to co-exist, because cache fills are
 +
blocked in NEM.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| INTEL_CAR_CQOS || soc/intel/common/block/cpu || bool ||  ||
 +
Cache Quality of Service allows more fine-grained control of cache
 +
usage. As result, it is possible to set up a portion of L2 cache for
 +
CAR and use the remainder for actual caching.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| INTEL_CAR_NEM_ENHANCED || soc/intel/common/block/cpu || bool ||  ||
 +
A current limitation of NEM (Non-Evict mode) is that code and data sizes
 +
are derived from the requirement to not write out any modified cache line.
 +
With NEM, if there is no physical memory behind the cached area,
 +
the modified data will be lost and NEM results will be inconsistent.
 +
ENHANCED NEM guarantees that modified data is always
 +
kept in cache while clean data is replaced.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_CSE || soc/intel/common/block/cse || bool ||  ||
 +
Driver for communication with Converged Security Engine (CSE)
 +
over Host Embedded Controller Interface (HECI)
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_EBDA || soc/intel/common/block/ebda || bool ||  ||
 +
Intel Processor common EBDA library support
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_PMC || soc/intel/common/block/pmc || bool ||  ||
 +
Intel Processor common code for Power Management controller(PMC)
 +
subsystem
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| POWER_STATE_OFF_AFTER_FAILURE || soc/intel/common/block/pmc || bool || S5 Soft Off ||
 +
Choose this option if you want to keep system into
 +
S5 after reapplying power after failure
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| POWER_STATE_ON_AFTER_FAILURE || soc/intel/common/block/pmc || bool || S0 Full On ||
 +
Choose this option if you want to keep system into
 +
S0 after reapplying power after failure
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| POWER_STATE_PREVIOUS_AFTER_FAILURE || soc/intel/common/block/pmc || bool || Keep Previous State ||
 +
Choose this option if you want to keep system into
 +
same power state as before failure even after reapplying
 +
power
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PMC_INVALID_READ_AFTER_WRITE || soc/intel/common/block/pmc || bool ||  ||
 +
Enable this for PMC devices where a read back of ACPI BAR and
 +
IO access bit does not return the previously written value.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_SMBUS || soc/intel/common/block/smbus || bool ||  ||
 +
Intel Processor common SMBus support
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_GPIO || soc/intel/common/block/gpio || bool ||  ||
 +
Intel Processor common GPIO support
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_SOC_COMMON_BLOCK_GPIO || soc/intel/common/block/gpio || bool || Output verbose GPIO debug messages ||
 +
This option enables GPIO debug messages
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_SGX || soc/intel/common/block/sgx || bool ||  ||
 +
Software Guard eXtension(SGX) Feature. Intel SGX is a set of new CPU
 +
instructions that can be used by applications to set aside private
 +
regions of code and data.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_DSP || soc/intel/common/block/dsp || bool ||  ||
 +
Intel Processor common DSP support
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_I2C || soc/intel/common/block/i2c || bool ||  ||
 +
Intel Processor Common I2C support
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_I2C_DEBUG || soc/intel/common/block/i2c || bool || Enable debug output for LPSS I2C transactions ||
 +
Enable debug output for I2C transactions.  This can be useful
 +
when debugging I2C drivers.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_SRAM || soc/intel/common/block/sram || bool ||  ||
 +
Intel Processor common SRAM support
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_ITSS || soc/intel/common/block/itss || bool ||  ||
 +
Intel Processor common interrupt timer subsystem support
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_INTEL_COMMON_BLOCK_GRAPHICS || soc/intel/common/block/graphics || bool ||  ||
 +
Intel Processor common Graphics support
 +
 
 +
||
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ACPI_CONSOLE || soc/intel/common || bool ||  ||
 +
Provide a mechanism for serial console based ACPI debug.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MMA || soc/intel/common || bool || Enable MMA (Memory Margin Analysis) support for Intel Core ||
 +
Set this option to y to enable MMA (Memory Margin Analysis) support
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TPM_TIS_ACPI_INTERRUPT || soc/intel/common || int ||  ||
 +
acpi_get_gpe() is used to provide interrupt status to TPM layer.
 +
This option specifies the GPE number.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_AMD_STONEYRIDGE_FP4 || soc/amd/stoneyridge || bool ||  ||
 +
AMD Stoney Ridge FP4 support
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_AMD_STONEYRIDGE_FT4 || soc/amd/stoneyridge || bool ||  ||
 +
AMD Stoney Ridge FT4 support
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_BSP_STACK_SIZE || soc/amd/stoneyridge || hex ||  ||
 +
The amount of anticipated stack usage in CAR by bootblock and
 +
other stages.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PRERAM_CBMEM_CONSOLE_SIZE || soc/amd/stoneyridge || hex ||  ||
 +
Increase this value if preram cbmem console is getting truncated
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOTTOMIO_POSITION || soc/amd/stoneyridge || hex || Bottom of 32-bit IO space ||
 +
If PCI peripherals with big BARs are connected to the system
 +
the bottom of the IO must be decreased to allocate such
 +
devices.
 +
 
 +
Declare the beginning of the 128MB-aligned MMIO region.  This
 +
option is useful when PCI peripherals requesting large address
 +
ranges are present.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_ID || soc/amd/stoneyridge || string ||  ||
 +
The default VGA BIOS PCI vendor/device ID should be set to the
 +
result of the map_oprom_vendev() function in northbridge.c.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| STONEYRIDGE_XHCI_ENABLE || soc/amd/stoneyridge || bool || Enable Stoney Ridge XHCI Controller ||
 +
The XHCI controller must be enabled and the XHCI firmware
 +
must be added in order to have USB 3.0 support configured
 +
by coreboot. The OS will be responsible for enabling the XHCI
 +
controller if the the XHCI firmware is available but the
 +
XHCI controller is not enabled by coreboot.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| STONEYRIDGE_XHCI_FWM || soc/amd/stoneyridge || bool || Add xhci firmware ||
 +
Add Stoney Ridge XHCI Firmware to support the onboard USB 3.0
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| STONEYRIDGE_IMC_FWM || soc/amd/stoneyridge || bool || Add IMC firmware ||
 +
Add Stoney Ridge IMC Firmware to support the onboard fan control
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| STONEYRIDGE_GEC_FWM || soc/amd/stoneyridge || bool ||  ||
 +
Add Stoney Ridge GEC Firmware to support the onboard gigabit Ethernet MAC.
 +
Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| STONEYRIDGE_SATA_MODE || soc/amd/stoneyridge || int || SATA Mode ||
 +
Select the mode in which SATA should be driven.
 +
The default is NATIVE.
 +
0: NATIVE mode does not require a ROM.
 +
2: AHCI may work with or without AHCI ROM. It depends on the payload support.
 +
For example, seabios does not require the AHCI ROM.
 +
3: LEGACY IDE
 +
4: IDE to AHCI
 +
5: AHCI7804: ROM Required, and AMD driver required in the OS.
 +
6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || NATIVE ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || AHCI ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || LEGACY IDE ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || IDE to AHCI ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || AHCI7804 ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || IDE to AHCI7804 ||
 +
|- bgcolor="#eeeeee"
 +
| STONEYRIDGE_LEGACY_FREE || soc/amd/stoneyridge || bool || System is legacy free ||
 +
Select y if there is no keyboard controller in the system.
 +
This sets variables in AGESA and ACPI.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SERIRQ_CONTINUOUS_MODE || soc/amd/stoneyridge || bool ||  ||
 +
Set this option to y for serial IRQ in continuous mode.
 +
Otherwise it is in quiet mode.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| STONEYRIDGE_ACPI_IO_BASE || soc/amd/stoneyridge || hex ||  ||
 +
Base address for the ACPI registers.
 +
This value must match the hardcoded value of AGESA.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| STONEYRIDGE_UART || soc/amd/stoneyridge || bool || UART controller on Stoney Ridge ||
 +
There are two UART controllers in Stoney Ridge.
 +
The UART registers are memory-mapped. UART
 +
controller 0 registers range from FEDC_6000h
 +
to FEDC_6FFFh. UART controller 1 registers
 +
range from FEDC_8000h to FEDC_8FFFh.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USE_PSPSCUREOS || soc/amd/stoneyridge || bool || Include PSP SecureOS blobs in AMD firmware ||
 +
Include the PspSecureOs, PspTrustlet and TrustletKey binaries
 +
in the amdfw section.
 +
 
 +
If unsure, answer 'y'
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AMDFW_OUTSIDE_CBFS || soc/amd/stoneyridge || bool || The AMD firmware is outside CBFS ||
 +
The AMDFW (PSP) is typically locatable in cbfs.  Select this
 +
option to manually attach the generated amdfw.rom outside of
 +
cbfs.  The location is selected by the FWM position.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AMD_FWM_POSITION_INDEX || soc/amd/stoneyridge || int || Firmware Directory Table location (0 to 5) ||
 +
Typically this is calculated by the ROM size, but there may
 +
be situations where you want to put the firmware directory
 +
table in a different location.
 +
0: 512 KB - 0xFFFA0000
 +
1: 1 MB  - 0xFFF20000
 +
2: 2 MB  - 0xFFE20000
 +
3: 4 MB  - 0xFFC20000
 +
4: 8 MB  - 0xFF820000
 +
5: 16 MB  - 0xFF020000
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || AMD Firmware Directory Table set to location for 512KB ROM ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || AMD Firmware Directory Table set to location for 1MB ROM ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || AMD Firmware Directory Table set to location for 2MB ROM ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || AMD Firmware Directory Table set to location for 4MB ROM ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || AMD Firmware Directory Table set to location for 8MB ROM ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || AMD Firmware Directory Table set to location for 16MB ROM ||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_POWER_RESTORE || soc/amd/stoneyridge || int ||  ||
 +
This option determines what state to go to once power is restored
 +
after having been lost in S0.  Select this option to automatically
 +
return to S0.  Otherwise the system will remain in S5 once power
 +
is restored.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VENDORCODE_FULL_SUPPORT || soc/amd/stoneyridge || int ||  ||
 +
This option determines if all files under
 +
vendorcode/amd/pi/00670F00/ will be compiled or only
 +
selected procedures of source files (minimum required).
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_AMD_COMMON || soc/amd/common || bool ||  ||
 +
common code for AMD SOCs
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_AMD_COMMON_BLOCK || soc/amd/common/block || bool ||  ||
 +
SoC driver for AMD common IP code
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || AMD SoC Common IP Code ||
 +
|- bgcolor="#eeeeee"
 +
| SOC_AMD_COMMON_BLOCK_S3 || soc/amd/common/block/s3 || bool ||  ||
 +
Select this option to add S3 related functions to the build.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_AMD_COMMON_BLOCK_PI || soc/amd/common/block/pi || bool ||  ||
 +
This option builds functions that interface AMD's AGESA.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_AMD_COMMON_BLOCK_PCI || soc/amd/common/block/pci || bool ||  ||
 +
This option builds functions used to program PCI interrupt
 +
routing, both PIC and APIC modes.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_AMD_COMMON_BLOCK_CAR || soc/amd/common/block/cpu || bool ||  ||
 +
This option allows the SOC to use a standard AMD cache-as-ram (CAR)
 +
implementation.  CAR setup is built into bootblock and teardown is
 +
in postcar.  The teardown procedure does not preserve the stack so
 +
it may not be appropriate for a romstage implementation without
 +
additional consideration.  If this option is not used, the SOC must
 +
implement these functions separately.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_AMD_COMMON_BLOCK_PSP || soc/amd/common/block/psp || bool ||  ||
 +
This option builds in the Platform Security Processor initialization
 +
functions.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_AMD_PSP_SELECTABLE_SMU_FW || soc/amd/common/block/psp || bool ||  ||
 +
Some PSP implementations allow storing SMU firmware into cbfs and
 +
calling the PSP to load the blobs at the proper time.
 +
 
 +
The soc/<codename> should select this if its PSP supports the feature
 +
and each mainboard can choose to select an appropriate fanless or
 +
fanned set of blobs.  Ask your AMD representative whether your APU
 +
is considered fanless.
 +
 
 +
||
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE || soc/broadcom/cygnus || bool || Enable DDR auto self-refresh ||
 +
Warning: M0 expects that auto self-refresh is enabled. Modify
 +
with caution.
 +
 
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_DRAM || soc/mediatek/mt8173 || bool || Output verbose DRAM related debug messages ||
 +
This option enables additional DRAM related debug messages.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_I2C || soc/mediatek/mt8173 || bool || Output verbose I2C related debug messages ||
 +
This option enables I2C related debug messages.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_PMIC || soc/mediatek/mt8173 || bool || Output verbose PMIC related debug messages ||
 +
This option enables PMIC related debug messages.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DEBUG_PMIC_WRAP || soc/mediatek/mt8173 || bool || Output verbose PMIC WRAP related debug messages ||
 +
This option enables PMIC WRAP related debug messages.
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CONSOLE_SERIAL_MVMAP2315_UART_ADDRESS || soc/marvell/mvmap2315 || hex ||  ||
 +
Map the UART to the respective MMIO address
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TTYS0_BAUD || soc/marvell/mvmap2315 || int ||  ||
 +
Baud rate for the UART
 +
||
 +
|- bgcolor="#eeeeee"
 +
| IPQ_QFN_PART || soc/qualcomm/ipq40xx || bool ||  ||
 +
Is the SoC a QFN part (as opposed to a BGA part)
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SBL_ELF || soc/qualcomm/ipq40xx || string || file name of the QCA SBL ELF ||
 +
The path and filename of the binary blob containing
 +
ipq40xx early initialization code, as supplied by the
 +
vendor.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SBL_UTIL_PATH || soc/qualcomm/ipq40xx || string || Path for utils to combine SBL_ELF and bootblock ||
 +
Path for utils to combine SBL_ELF and bootblock
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SBL_BLOB || soc/qualcomm/ipq806x || string || file name of the Qualcomm SBL blob ||
 +
The path and filename of the binary blob containing
 +
ipq806x early initialization code, as supplied by the
 +
vendor.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RK3399_SPREAD_SPECTRUM_DDR || soc/rockchip/rk3399 || bool || Spread-spectrum DDR clock ||
 +
Select Spread Spectrum Modulator (SSMOD) is a fully-digital circuit
 +
used to modulate the frequency of the Silicon Creations' Fractional
 +
PLL in order to reduce EMI.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || CPU ||
 +
|- bgcolor="#eeeeee"
 +
| RESET_ON_INVALID_RAMSTAGE_CACHE || cpu/intel/haswell || bool || Reset the system on S3 wake when ramstage cache invalid. ||
 +
The haswell romstage code caches the loaded ramstage program
 +
in SMM space. On S3 wake the romstage will copy over a fresh
 +
ramstage that was cached in the SMM space. This option determines
 +
the action to take when the ramstage cache is invalid. If selected
 +
the system will reset otherwise the ramstage will be reloaded from
 +
cbfs.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_INTEL_FIRMWARE_INTERFACE_TABLE || cpu/intel/fit || None ||  ||
 +
This option selects building a Firmware Interface Table (FIT).
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_INTEL_NUM_FIT_ENTRIES || cpu/intel/fit || int ||  ||
 +
This option selects the number of empty entries in the FIT table.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED || cpu/intel/turbo || None ||  ||
 +
This option indicates that the turbo mode setting is not package
 +
scoped. i.e. enable_turbo() needs to be called on not just the bsp
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SET_VMX_LOCK_BIT || cpu/intel/common || bool || Set lock bit after configuring VMX ||
 +
Although the Intel manual says you must set the lock bit in addition
 +
to the VMX bit in order for VMX to work, this isn't strictly true, so
 +
we have the option to leave it unlocked and allow the OS (e.g. Linux)
 +
to manage things itself. This is beneficial for testing purposes as
 +
there is no need to reflash the firmware just to toggle the lock bit.
 +
However, leaving the lock bit unset will break Windows' detection of
 +
VMX support and built-in virtualization features like Hyper-V.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| GEODE_VSA_FILE || cpu/amd/geode_lx || bool || Add a VSA image ||
 +
Select this option if you have an AMD Geode LX vsa that you would
 +
like to add to your ROM.
 +
 
 +
You will be able to specify the location and file name of the
 +
image later.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VSA_FILENAME || cpu/amd/geode_lx || string || AMD Geode LX VSA path and filename ||
 +
The path and filename of the file to use as VSA.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| XIP_ROM_SIZE || cpu/amd/agesa || hex ||  ||
 +
Overwride the default write through caching size as 1M Bytes.
 +
On some AMD platforms, one socket supports 2 or more kinds of
 +
processor family, compiling several CPU families agesa code
 +
will increase the romstage size.
 +
In order to execute romstage in place on the flash ROM,
 +
more space is required to be set as write through caching.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_MRC_CACHE || cpu/amd/agesa || bool || Use cached memory configuration ||
 +
Try to restore memory training results
 +
from non-volatile memory.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FORCE_AM1_SOCKET_SUPPORT || cpu/amd/agesa/family16kb || bool ||  ||
 +
Force AGESA to ignore package type mismatch between CPU and northbridge
 +
in memory code. This enables Socket AM1 support with current AGESA
 +
version for Kabini platform.
 +
Enable this option only if you have Socket AM1 board.
 +
Note that the AGESA release shipped with coreboot does not officially
 +
support the AM1 socket. Selecting this option might damage your hardware.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| XIP_ROM_SIZE || cpu/amd/pi || hex ||  ||
 +
Overwride the default write through caching size as 1M Bytes.
 +
On some AMD platforms, one socket supports 2 or more kinds of
 +
processor family, compiling several CPU families agesa code
 +
will increase the romstage size.
 +
In order to execute romstage in place on the flash ROM,
 +
more space is required to be set as write through caching.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PARALLEL_MP || cpu/x86 || bool ||  ||
 +
This option uses common MP infrastructure for bringing up APs
 +
in parallel. It additionally provides a more flexible mechanism
 +
for sequencing the steps of bringing up the APs.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PARALLEL_MP_AP_WORK || cpu/x86 || bool ||  ||
 +
Allow APs to do other work after initialization instead of going
 +
to sleep.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| LAPIC_MONOTONIC_TIMER || cpu/x86 || bool ||  ||
 +
Expose monotonic time using the local APIC.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TSC_CONSTANT_RATE || cpu/x86 || bool ||  ||
 +
This option asserts that the TSC ticks at a known constant rate.
 +
Therefore, no TSC calibration is required.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TSC_MONOTONIC_TIMER || cpu/x86 || bool ||  ||
 +
Expose monotonic time using the TSC.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TSC_SYNC_LFENCE || cpu/x86 || bool ||  ||
 +
The CPU driver should select this if the CPU needs
 +
to execute an lfence instruction in order to synchronize
 +
rdtsc. This is true for all modern AMD CPUs.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| TSC_SYNC_MFENCE || cpu/x86 || bool ||  ||
 +
The CPU driver should select this if the CPU needs
 +
to execute an mfence instruction in order to synchronize
 +
rdtsc. This is true for all modern Intel CPUs.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NO_FIXED_XIP_ROM_SIZE || cpu/x86 || bool ||  ||
 +
The XIP_ROM_SIZE Kconfig variable is used globally on x86
 +
with the assumption that all chipsets utilize this value.
 +
For the chipsets which do not use the variable it can lead
 +
to unnecessary alignment constraints in cbfs for romstage.
 +
Therefore, allow those chipsets a path to not be burdened.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SMM_MODULE_HEAP_SIZE || cpu/x86 || hex ||  ||
 +
This option determines the size of the heap within the SMM handler
 +
modules.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SERIALIZED_SMM_INITIALIZATION || cpu/x86 || bool ||  ||
 +
On some CPUs, there is a race condition in SMM.
 +
This can occur when both hyperthreads change SMM state
 +
variables in parallel without coordination.
 +
Setting this option serializes the SMM initialization
 +
to avoid an ugly hang in the boot process at the cost
 +
of a slightly longer boot time.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| X86_AMD_FIXED_MTRRS || cpu/x86 || bool ||  ||
 +
This option informs the MTRR code to use the RdMem and WrMem fields
 +
in the fixed MTRR MSRs.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PLATFORM_USES_FSP1_0 || cpu/x86 || bool ||  ||
 +
Selected for Intel processors/platform combinations that use the
 +
Intel Firmware Support Package (FSP) 1.0 for initialization.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING || cpu/x86 || bool ||  ||
 +
On certain platforms a boot speed gain can be realized if mirroring
 +
the payload data stored in non-volatile storage. On x86 systems the
 +
payload would typically live in a memory-mapped SPI part. Copying
 +
the SPI contents to RAM before performing the load can speed up
 +
the boot process.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOC_SETS_MSRS || cpu/x86 || bool ||  ||
 +
The SoC requires different access methods for reading and writing
 +
the MSRs.  Use SoC specific routines to handle the MSR access.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NO_CAR_GLOBAL_MIGRATION || cpu || bool ||  ||
 +
This option is selected if there is no need to migrate CAR globals.
 +
All stages which use CAR globals can directly access the variables
 +
from their linked addresses.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SMP || cpu || bool ||  ||
 +
This option is used to enable certain functions to make coreboot
 +
work correctly on symmetric multi processor (SMP) systems.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AP_SIPI_VECTOR || cpu || hex ||  ||
 +
This must equal address of ap_sipi_vector from bootblock build.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MMX || cpu || bool ||  ||
 +
Select MMX in your socket or model Kconfig if your CPU has MMX
 +
streaming SIMD instructions. ROMCC can build more efficient
 +
code if it can spill to MMX registers.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SSE || cpu || bool ||  ||
 +
Select SSE in your socket or model Kconfig if your CPU has SSE
 +
streaming SIMD instructions. ROMCC can build more efficient
 +
code if it can spill to SSE (aka XMM) registers.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SSE2 || cpu || bool ||  ||
 +
Select SSE2 in your socket or model Kconfig if your CPU has SSE2
 +
streaming SIMD instructions. Some parts of coreboot can be built
 +
with more efficient code if SSE2 instructions are available.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USES_MICROCODE_HEADER_FILES || cpu || bool ||  ||
 +
This is selected by a board or chipset to set the default for the
 +
microcode source choice to a list of external microcode headers
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_MICROCODE_CBFS_GENERATE || cpu || bool || Generate from tree ||
 +
Select this option if you want microcode updates to be assembled when
 +
building coreboot and included in the final image as a separate CBFS
 +
file. Microcode will not be hard-coded into ramstage.
 +
 
 +
The microcode file may be removed from the ROM image at a later
 +
time with cbfstool, if desired.
 +
 
 +
If unsure, select this option.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_MICROCODE_CBFS_EXTERNAL_HEADER || cpu || bool || Include external microcode header files ||
 +
Select this option if you want to include external c header files
 +
containing the CPU microcode. This will be included as a separate
 +
file in CBFS.
 +
 
 +
A word of caution: only select this option if you are sure the
 +
microcode that you have is newer than the microcode shipping with
 +
coreboot.
 +
 
 +
The microcode file may be removed from the ROM image at a later
 +
time with cbfstool, if desired.
 +
 
 +
If unsure, select "Generate from tree"
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_MICROCODE_CBFS_NONE || cpu || bool || Do not include microcode updates ||
 +
Select this option if you do not want CPU microcode included in CBFS.
 +
Note that for some CPUs, the microcode is hard-coded into the source
 +
tree and is not loaded from CBFS. In this case, microcode will still
 +
be updated. There is a push to move all microcode to CBFS, but this
 +
change is not implemented for all CPUs.
 +
 
 +
This option currently applies to:
 +
- Intel SandyBridge/IvyBridge
 +
- VIA Nano
 +
 
 +
Microcode may be added to the ROM image at a later time with cbfstool,
 +
if desired.
 +
 
 +
If unsure, select "Generate from tree"
 +
 
 +
The GOOD:
 +
Microcode updates intend to solve issues that have been discovered
 +
after CPU production. The expected effect is that systems work as
 +
intended with the updated microcode, but we have also seen cases where
 +
issues were solved by not applying microcode updates.
 +
 
 +
The BAD:
 +
Note that some operating system include these same microcode patches,
 +
so you may need to also disable microcode updates in your operating
 +
system for this option to have an effect.
 +
 
 +
The UGLY:
 +
A word of CAUTION: some CPUs depend on microcode updates to function
 +
correctly. Not updating the microcode may leave the CPU operating at
 +
less than optimal performance, or may cause outright hangups.
 +
There are CPUs where coreboot cannot properly initialize the CPU
 +
without microcode updates
 +
For example, if running with the factory microcode, some Intel
 +
SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs
 +
will hang when changing the frequency.
 +
 
 +
Make sure you have a way of flashing the ROM externally before
 +
selecting this option.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_MICROCODE_MULTIPLE_FILES || cpu || bool ||  ||
 +
Select this option to install separate microcode container files into
 +
CBFS instead of using the traditional monolithic microcode file format.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_MICROCODE_HEADER_FILES || cpu || string || List of space separated microcode header files with the path ||
 +
A list of one or more microcode header files with path from the
 +
coreboot directory.  These should be separated by spaces.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_UCODE_BINARIES || cpu || string || Microcode binary path and filename ||
 +
Some platforms have microcode in the blobs directory, and these can
 +
be hardcoded in the makefiles.  For platforms with microcode
 +
binaries that aren't in the makefile, set this option to pull
 +
in the microcode.
 +
 
 +
This should contain the full path of the file for one or more
 +
microcode binary files to include, separated by spaces.
 +
 
 +
If unsure, leave this blank.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Northbridge ||
 +
|- bgcolor="#eeeeee"
 +
| I945_LVDS || northbridge/intel/i945 || string ||  ||
 +
Selected by mainboards that use native graphics initialization
 +
for the LVDS port. A linear framebuffer is only supported for
 +
LVDS.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| OVERRIDE_CLOCK_DISABLE || northbridge/intel/i945 || bool ||  ||
 +
Usually system firmware turns off system memory clock
 +
signals to unused SO-DIMM slots to reduce EMI and power
 +
consumption.
 +
However, some boards do not like unused clock signals to
 +
be disabled.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAXIMUM_SUPPORTED_FREQUENCY || northbridge/intel/i945 || int ||  ||
 +
If non-zero, this designates the maximum DDR frequency
 +
the board supports, despite what the chipset should be
 +
capable of.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CHECK_SLFRCS_ON_RESUME || northbridge/intel/i945 || int ||  ||
 +
On some boards it may be neccessary to hard reset early
 +
during resume from S3 if the SLFRCS register indicates that
 +
a memory channel is not guaranteed to be in self-refresh.
 +
On other boards the check always creates a false positive,
 +
effectively making it impossible to resume.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USE_NATIVE_RAMINIT || northbridge/intel/sandybridge || bool || Use native raminit ||
 +
Select if you want to use coreboot implementation of raminit rather than
 +
System Agent/MRC.bin. You should answer Y.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES || northbridge/intel/sandybridge || bool || Ignore vendor programmed fuses that limit max. DRAM frequency ||
 +
Ignore the mainboard's vendor programmed fuses that might limit the
 +
maximum DRAM frequency. By selecting this option the fuses will be
 +
ignored and the only limits on DRAM frequency are set by RAM's SPD and
 +
hard fuses in southbridge's clockgen.
 +
Disabled by default as it might causes system instability.
 +
Handle with care!
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS || northbridge/intel/sandybridge || bool || Ignore XMP profile max DIMMs per channel ||
 +
Ignore the max DIMMs per channel restriciton defined in XMP profiles.
 +
Disabled by default as it might cause system instability.
 +
Handle with care!
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MMCONF_BASE_ADDRESS || northbridge/intel/sandybridge || hex ||  ||
 +
The MRC blob requires it to be at 0xf0000000.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MRC_FILE || northbridge/intel/sandybridge || string || Intel System Agent path and filename ||
 +
The path and filename of the file to use as System Agent
 +
binary.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_RAM_SIZE || northbridge/intel/haswell || hex ||  ||
 +
The size of the cache-as-ram region required during bootblock
 +
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
 +
must add up to a power of 2.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_RAM_MRC_VAR_SIZE || northbridge/intel/haswell || hex ||  ||
 +
The amount of cache-as-ram region required by the reference code.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| DCACHE_RAM_ROMSTAGE_STACK_SIZE || northbridge/intel/haswell || hex ||  ||
 +
The amount of anticipated stack usage from the data cache
 +
during pre-ram ROM stage execution.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_MRC || northbridge/intel/haswell || bool || Add a System Agent binary ||
 +
Select this option to add a System Agent binary to
 +
the resulting coreboot image.
 +
 
 +
Note: Without this binary coreboot will not work
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MRC_FILE || northbridge/intel/haswell || string || Intel System Agent path and filename ||
 +
The path and filename of the file to use as System Agent
 +
binary.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PRE_GRAPHICS_DELAY || northbridge/intel/haswell || int || Graphics initialization delay in ms ||
 +
On some systems, coreboot boots so fast that connected monitors
 +
(mostly TVs) won't be able to wake up fast enough to talk to the
 +
VBIOS. On those systems we need to wait for a bit before executing
 +
the VBIOS.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_ID || northbridge/intel/fsp_sandybridge || string ||  ||
 +
This is the default PCI ID for the sandybridge/ivybridge graphics
 +
devices.  This string names the vbios ROM in cbfs.  The following
 +
PCI IDs will be remapped to load this ROM:
 +
0x80860102, 0x8086010a, 0x80860112, 0x80860116
 +
0x80860122, 0x80860126, 0x80860166
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_FILE || northbridge/intel/fsp_sandybridge/fsp || string ||  ||
 +
The path and filename of the Intel FSP binary for this platform.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_LOC || northbridge/intel/fsp_sandybridge/fsp || hex || Intel FSP Binary location in CBFS ||
 +
The location in CBFS that the FSP is located. This must match the
 +
value that is set in the FSP binary.  If the FSP needs to be moved,
 +
rebase the FSP with the Intel's BCT (tool).
 +
 
 +
The Ivy Bridge Processor/Panther Point FSP is built with a preferred
 +
base address of 0xFFF80000
 +
 
 +
||
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SDRAMPWR_4DIMM || northbridge/intel/i440bx || bool ||  ||
 +
This option affects how the SDRAMC register is programmed.
 +
Memory clock signals will not be routed properly if this option
 +
is set wrong.
 +
 
 +
If your board has 4 DIMM slots, you must use select this option, in
 +
your Kconfig file of the board. On boards with 3 DIMM slots,
 +
do _not_ select this option.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SET_TSEG_1MB || northbridge/intel/fsp_rangeley || bool || 1 MB ||
 +
Set the TSEG area to 1 MB.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SET_TSEG_2MB || northbridge/intel/fsp_rangeley || bool || 2 MB ||
 +
Set the TSEG area to 2 MB.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SET_TSEG_4MB || northbridge/intel/fsp_rangeley || bool || 4 MB ||
 +
Set the TSEG area to 4 MB.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SET_TSEG_8MB || northbridge/intel/fsp_rangeley || bool || 8 MB ||
 +
Set the TSEG area to 8 MB.
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_FILE || northbridge/intel/fsp_rangeley/fsp || string ||  ||
 +
The path and filename of the Intel FSP binary for this platform.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_LOC || northbridge/intel/fsp_rangeley/fsp || hex ||  ||
 +
The location in CBFS that the FSP is located. This must match the
 +
value that is set in the FSP binary.  If the FSP needs to be moved,
 +
rebase the FSP with Intel's BCT (tool).
 +
 
 +
The Rangeley FSP is built with a preferred base address of 0xFFF80000
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOTTOMIO_POSITION || northbridge/amd/pi || hex || Bottom of 32-bit IO space ||
 +
If PCI peripherals with big BARs are connected to the system
 +
the bottom of the IO must be decreased to allocate such
 +
devices.
 +
 
 +
Declare the beginning of the 128MB-aligned MMIO region.  This
 +
option is useful when PCI peripherals requesting large address
 +
ranges are present.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_ID || northbridge/amd/pi/00630F01 || string ||  ||
 +
The default VGA BIOS PCI vendor/device ID should be set to the
 +
result of the map_oprom_vendev() function in northbridge.c.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_ID || northbridge/amd/pi/00730F01 || string ||  ||
 +
The default VGA BIOS PCI vendor/device ID should be set to the
 +
result of the map_oprom_vendev() function in northbridge.c.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_ID || northbridge/amd/pi/00660F01 || string ||  ||
 +
The default VGA BIOS PCI vendor/device ID should be set to the
 +
result of the map_oprom_vendev() function in northbridge.c.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| REDIRECT_NBCIMX_TRACE_TO_SERIAL || northbridge/amd/cimx/rd890 || bool || Redirect AMD Northbridge CIMX Trace to serial console ||
 +
This Option allows you to redirect the AMD Northbridge CIMX
 +
Trace debug information to the serial console.
 +
 
 +
Warning: Only enable this option when debuging or tracing AMD CIMX code.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NO_MMCONF_SUPPORT || northbridge/amd/amdk8 || bool ||  ||
 +
If you want to remove this, you need to make sure any access to CPU
 +
nodes 0:18.0, 0:19.0, ...  continue to use PCI IO config access.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_ID || northbridge/amd/agesa/family16kb || string ||  ||
 +
The default VGA BIOS PCI vendor/device ID should be set to the
 +
result of the map_oprom_vendev() function in northbridge.c.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SVI_HIGH_FREQ || northbridge/amd/amdfam10 || bool ||  ||
 +
Select this for boards with a Voltage Regulator able to operate
 +
at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.
 +
 
 +
||
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: HyperTransport setup || || || ||
 +
|- bgcolor="#eeeeee"
 +
| SVI_HIGH_FREQ || northbridge/amd/amdfam10 || bool || HyperTransport downlink width ||
 +
This option sets the maximum permissible HyperTransport
 +
downlink width.
 +
 
 +
Use of this option will only limit the autodetected HT width.
 +
It will not (and cannot) increase the width beyond the autodetected
 +
limits.
 +
 
 +
This is primarily used to work around poorly designed or laid out HT
 +
traces on certain motherboards.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| LIMIT_HT_DOWN_WIDTH_16 || northbridge/amd/amdfam10 || bool || HyperTransport uplink width ||
 +
This option sets the maximum permissible HyperTransport
 +
uplink width.
 +
 
 +
Use of this option will only limit the autodetected HT width.
 +
It will not (and cannot) increase the width beyond the autodetected
 +
limits.
 +
 
 +
This is primarily used to work around poorly designed or laid out HT
 +
traces on certain motherboards.
 +
 
 +
||
 +
 
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Southbridge ||
 +
|- bgcolor="#eeeeee"
 +
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/ibexpeak || bool ||  ||
 +
If you set this option to y, the serial IRQ machine will be
 +
operated in continuous mode.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| INTEL_LYNXPOINT_LP || southbridge/intel/lynxpoint || bool ||  ||
 +
Set this option to y for Lynxpont LP (Haswell ULT).
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/lynxpoint || bool ||  ||
 +
If you set this option to y, the serial IRQ machine will be
 +
operated in continuous mode.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ME_MBP_CLEAR_LATE || southbridge/intel/lynxpoint || bool || Defer wait for ME MBP Cleared ||
 +
If you set this option to y, the Management Engine driver
 +
will defer waiting for the MBP Cleared indicator until the
 +
finalize step.  This can speed up boot time if the ME takes
 +
a long time to indicate this status.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FINALIZE_USB_ROUTE_XHCI || southbridge/intel/lynxpoint || bool || Route all ports to XHCI controller in finalize step ||
 +
If you set this option to y, the USB ports will be routed
 +
to the XHCI controller during the finalize SMM callback.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/bd82x6x || bool ||  ||
 +
If you set this option to y, the serial IRQ machine will be
 +
operated in continuous mode.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| LOCK_SPI_FLASH_RO || southbridge/intel/bd82x6x || bool || Write-protect all flash sections ||
 +
Select this if you want to write-protect the whole firmware flash
 +
chip. The locking will take place during the chipset lockdown, which
 +
is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set)
 +
or has to be triggered later (e.g. by the payload or the OS).
 +
 
 +
NOTE: If you trigger the chipset lockdown unconditionally,
 +
you won't be able to write to the flash chip using the
 +
internal programmer any more.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| LOCK_SPI_FLASH_NO_ACCESS || southbridge/intel/bd82x6x || bool || Write-protect all flash sections and read-protect non-BIOS sections ||
 +
Select this if you want to protect the firmware flash against all
 +
further accesses (with the exception of the memory mapped BIOS re-
 +
gion which is always readable). The locking will take place during
 +
the chipset lockdown, which is either triggered by coreboot (when
 +
INTEL_CHIPSET_LOCKDOWN is set) or has to be triggered later (e.g.
 +
by the payload or the OS).
 +
 
 +
NOTE: If you trigger the chipset lockdown unconditionally,
 +
you won't be able to write to the flash chip using the
 +
internal programmer any more.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/fsp_bd82x6x || bool ||  ||
 +
If you set this option to y, the serial IRQ machine will be
 +
operated in continuous mode.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| INTEL_CHIPSET_LOCKDOWN || southbridge/intel/common || bool || Lock down chipset in coreboot ||
 +
Some registers within host bridge on particular chipsets should be
 +
locked down on each normal boot path (done by either coreboot or payload)
 +
and S3 resume (always done by coreboot). Select this to let coreboot
 +
to do this on normal boot path.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/fsp_rangeley || bool ||  ||
 +
If you set this option to y, the serial IRQ machine will be
 +
operated in continuous mode.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| IFD_BIN_PATH || southbridge/intel/fsp_rangeley || string ||  ||
 +
The path and filename to the descriptor.bin file.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/fsp_i89xx || bool ||  ||
 +
If you set this option to y, the serial IRQ machine will be
 +
operated in continuous mode.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_XHCI_ENABLE || southbridge/amd/pi/hudson || bool || Enable Hudson XHCI Controller ||
 +
The XHCI controller must be enabled and the XHCI firmware
 +
must be added in order to have USB 3.0 support configured
 +
by coreboot. The OS will be responsible for enabling the XHCI
 +
controller if the the XHCI firmware is available but the
 +
XHCI controller is not enabled by coreboot.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_XHCI_FWM || southbridge/amd/pi/hudson || bool || Add xhci firmware ||
 +
Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_IMC_FWM || southbridge/amd/pi/hudson || bool || Add IMC firmware ||
 +
Add Hudson 2/3/4 IMC Firmware to support the onboard fan control
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_GEC_FWM || southbridge/amd/pi/hudson || bool ||  ||
 +
Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC.
 +
Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_SATA_MODE || southbridge/amd/pi/hudson || int || SATA Mode ||
 +
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
 +
The default is NATIVE.
 +
0: NATIVE mode does not require a ROM.
 +
1: RAID mode must have the two ROM files.
 +
2: AHCI may work with or without AHCI ROM. It depends on the payload support.
 +
For example, seabios does not require the AHCI ROM.
 +
3: LEGACY IDE
 +
4: IDE to AHCI
 +
5: AHCI7804: ROM Required, and AMD driver required in the OS.
 +
6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || NATIVE ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || RAID ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || AHCI ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || LEGACY IDE ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || IDE to AHCI ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || AHCI7804 ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || IDE to AHCI7804 ||
 +
|- bgcolor="#eeeeee"
 +
| RAID_ROM_ID || southbridge/amd/pi/hudson || string || RAID device PCI IDs ||
 +
1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RAID_MISC_ROM_POSITION || southbridge/amd/pi/hudson || hex || RAID Misc ROM Position ||
 +
The RAID ROM requires that the MISC ROM is located between the range
 +
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
 +
The CONFIG_ROM_SIZE must be larger than 0x100000.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_LEGACY_FREE || southbridge/amd/pi/hudson || bool || System is legacy free ||
 +
Select y if there is no keyboard controller in the system.
 +
This sets variables in AGESA and ACPI.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AZ_PIN || southbridge/amd/pi/hudson || hex ||  ||
 +
bit 1,0 - pin 0
 +
bit 3,2 - pin 1
 +
bit 5,4 - pin 2
 +
bit 7,6 - pin 3
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AMDFW_OUTSIDE_CBFS || southbridge/amd/pi/hudson || hex ||  ||
 +
The AMDFW (PSP) is typically locatable in cbfs.  Select this
 +
option to manually attach the generated amdfw.rom at an
 +
offset of 0x20000 from the bottom of the coreboot ROM image.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SERIRQ_CONTINUOUS_MODE || southbridge/amd/pi/hudson || bool ||  ||
 +
Set this option to y for serial IRQ in continuous mode.
 +
Otherwise it is in quiet mode.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_ACPI_IO_BASE || southbridge/amd/pi/hudson || hex ||  ||
 +
Base address for the ACPI registers.
 +
This value must match the hardcoded value of AGESA.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_UART || southbridge/amd/pi/hudson || bool || UART controller on Kern ||
 +
There are two UART controllers in Kern.
 +
The UART registers are memory-mapped. UART
 +
controller 0 registers range from FEDC_6000h
 +
to FEDC_6FFFh. UART controller 1 registers
 +
range from FEDC_8000h to FEDC_8FFFh.
 +
 
 +
||
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_IDE_COMBINED_MODE || southbridge/amd/cimx/sb800 || bool || Enable SATA IDE combined mode ||
 +
If Combined Mode is enabled. IDE controller is exposed and
 +
SATA controller has control over Port0 through Port3,
 +
IDE controller has control over Port4 and Port5.
 +
 
 +
If Combined Mode is disabled, IDE controller is hidden and
 +
SATA controller has full control of all 6 Ports when operating in non-IDE mode.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| IDE_COMBINED_MODE || southbridge/amd/cimx/sb800 || hex || SATA Mode ||
 +
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
 +
The default is AHCI.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_SATA_IDE || southbridge/amd/cimx/sb800 || bool || NATIVE ||
 +
NATIVE does not require a ROM.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_SATA_AHCI || southbridge/amd/cimx/sb800 || bool || AHCI ||
 +
AHCI is the default and may work with or without AHCI ROM. It depends on the payload support.
 +
For example, seabios does not require the AHCI ROM.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_SATA_RAID || southbridge/amd/cimx/sb800 || bool || RAID ||
 +
sb800 RAID mode must have the two required ROM files.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RAID_ROM_ID || southbridge/amd/cimx/sb800 || string || RAID device PCI IDs ||
 +
1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RAID_MISC_ROM_POSITION || southbridge/amd/cimx/sb800 || hex || RAID Misc ROM Position ||
 +
The RAID ROM requires that the MISC ROM is located between the range
 +
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
 +
The CONFIG_ROM_SIZE must larger than 0x100000.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_IMC_FWM || southbridge/amd/cimx/sb800 || bool || Add IMC firmware ||
 +
Add SB800 / Hudson 1 IMC Firmware to support the onboard fan control.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_FWM_AT_FFFA0000 || southbridge/amd/cimx/sb800 || bool || 0xFFFA0000 ||
 +
The IMC and GEC ROMs requires a 'signature' located at one of several
 +
fixed locations in memory.  The location used shouldn't matter, just
 +
select an area that doesn't conflict with anything else.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_FWM_AT_FFF20000 || southbridge/amd/cimx/sb800 || bool || 0xFFF20000 ||
 +
The IMC and GEC ROMs requires a 'signature' located at one of several
 +
fixed locations in memory.  The location used shouldn't matter, just
 +
select an area that doesn't conflict with anything else.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_FWM_AT_FFE20000 || southbridge/amd/cimx/sb800 || bool || 0xFFE20000 ||
 +
The IMC and GEC ROMs requires a 'signature' located at one of several
 +
fixed locations in memory.  The location used shouldn't matter, just
 +
select an area that doesn't conflict with anything else.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_FWM_AT_FFC20000 || southbridge/amd/cimx/sb800 || bool || 0xFFC20000 ||
 +
The IMC and GEC ROMs requires a 'signature' located at one of several
 +
fixed locations in memory.  The location used shouldn't matter, just
 +
select an area that doesn't conflict with anything else.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_FWM_AT_FF820000 || southbridge/amd/cimx/sb800 || bool || 0xFF820000 ||
 +
The IMC and GEC ROMs requires a 'signature' located at one of several
 +
fixed locations in memory.  The location used shouldn't matter, just
 +
select an area that doesn't conflict with anything else.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EHCI_BAR || southbridge/amd/cimx/sb800 || hex || Fan Control ||
 +
Select the method of SB800 fan control to be used.  None would be
 +
for either fixed maximum speed fans connected to the SB800 or for
 +
an external chip controlling the fan speeds.  Manual control sets
 +
up the SB800 fan control registers.  IMC fan control uses the SB800
 +
IMC to actively control the fan speeds.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_NO_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || None ||
 +
No SB800 Fan control - Do not set up the SB800 fan control registers.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_MANUAL_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || Manual ||
 +
Configure the SB800 fan control registers in devicetree.cb.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SB800_IMC_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || IMC Based ||
 +
Set up the SB800 to use the IMC based Fan controller.  This requires
 +
the IMC ROM from AMD.  Configure the registers in devicetree.cb.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SATA_CONTROLLER_MODE || southbridge/amd/cimx/sb900 || hex ||  ||
 +
0x0 = Native IDE mode.
 +
0x1 = RAID mode.
 +
0x2 = AHCI mode.
 +
0x3 = Legacy IDE mode.
 +
0x4 = IDE->AHCI mode.
 +
0x5 = AHCI mode as 7804 ID (AMD driver).
 +
0x6 = IDE->AHCI mode as 7804 ID (AMD driver).
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PCIB_ENABLE || southbridge/amd/cimx/sb900 || bool ||  ||
 +
n = Disable PCI Bridge Device 14 Function 4.
 +
y = Enable PCI Bridge Device 14 Function 4.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ACPI_SCI_IRQ || southbridge/amd/cimx/sb900 || hex ||  ||
 +
Set SCI IRQ to 9.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EXT_CONF_SUPPORT || southbridge/amd/sr5650 || bool || Enable PCI-E MMCONFIG support ||
 +
Select to enable PCI-E MMCONFIG support on the SR5650.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EXT_CONF_SUPPORT || southbridge/amd/rs690 || bool ||  ||
 +
Select if RS690 should be setup to support MMCONF.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_XHCI_ENABLE || southbridge/amd/agesa/hudson || bool || Enable Hudson XHCI Controller ||
 +
The XHCI controller must be enabled and the XHCI firmware
 +
must be added in order to have USB 3.0 support configured
 +
by coreboot. The OS will be responsible for enabling the XHCI
 +
controller if the the XHCI firmware is available but the
 +
XHCI controller is not enabled by coreboot.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_XHCI_FWM || southbridge/amd/agesa/hudson || bool || Add xhci firmware ||
 +
Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_IMC_FWM || southbridge/amd/agesa/hudson || bool || Add imc firmware ||
 +
Add Hudson 2/3/4 IMC Firmware to support the onboard fan control
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_GEC_FWM || southbridge/amd/agesa/hudson || bool ||  ||
 +
Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC.
 +
Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_SATA_MODE || southbridge/amd/agesa/hudson || int || SATA Mode ||
 +
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
 +
The default is NATIVE.
 +
0: NATIVE mode does not require a ROM.
 +
1: RAID mode must have the two ROM files.
 +
2: AHCI may work with or without AHCI ROM. It depends on the payload support.
 +
For example, seabios does not require the AHCI ROM.
 +
3: LEGACY IDE
 +
4: IDE to AHCI
 +
5: AHCI7804: ROM Required, and AMD driver required in the OS.
 +
6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || NATIVE ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || RAID ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || AHCI ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || LEGACY IDE ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || IDE to AHCI ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || AHCI7804 ||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || IDE to AHCI7804 ||
 +
|- bgcolor="#eeeeee"
 +
| RAID_ROM_ID || southbridge/amd/agesa/hudson || string || RAID device PCI IDs ||
 +
1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RAID_MISC_ROM_POSITION || southbridge/amd/agesa/hudson || hex || RAID Misc ROM Position ||
 +
The RAID ROM requires that the MISC ROM is located between the range
 +
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
 +
The CONFIG_ROM_SIZE must be larger than 0x100000.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HUDSON_LEGACY_FREE || southbridge/amd/agesa/hudson || bool || System is legacy free ||
 +
Select y if there is no keyboard controller in the system.
 +
This sets variables in AGESA and ACPI.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AZ_PIN || southbridge/amd/agesa/hudson || hex ||  ||
 +
bit 1,0 - pin 0
 +
bit 3,2 - pin 1
 +
bit 5,4 - pin 2
 +
bit 7,6 - pin 3
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOUTHBRIDGE_AMD_SB700_33MHZ_SPI || southbridge/amd/sb700 || bool || Enable high speed SPI clock ||
 +
When set, the SPI clock will run at 33MHz instead
 +
of the compatibility mode 16.5MHz.  Note that not
 +
all ROMs are capable of 33MHz operation, so you
 +
will need to verify this option is appropriate for
 +
the ROM you are using.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NO_EARLY_SMBUS || southbridge/amd/cs5536 || bool ||  ||
 +
Skip the CS5536 early SMBUS initialization.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EHCI_BAR || southbridge/amd/sb600 || hex || SATA Mode ||
 +
Select the mode in which SATA should be driven. IDE or AHCI.
 +
The default is IDE.
 +
 
 +
config SATA_MODE_IDE
 +
bool "IDE"
 +
 
 +
config SATA_MODE_AHCI
 +
bool "AHCI"
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Super I/O ||
 +
|- bgcolor="#eeeeee"
 +
| SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG || superio/ite/common || bool ||  ||
 +
Enable extended, 16-bit wide tacho counters.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SUPERIO_ITE_ENV_CTRL_8BIT_PWM || superio/ite/common || bool ||  ||
 +
PWM duty cycles are set in 8-bit registers (instead of 7 bit).
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 || superio/ite/common || bool ||  ||
 +
The second FAN controller has a separate frequency setting.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Embedded Controllers ||
 +
|- bgcolor="#eeeeee"
 +
| EC_ACPI || ec/acpi || bool ||  ||
 +
ACPI Embedded Controller interface. Mostly found in laptops.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC || ec/google/chromeec || bool ||  ||
 +
Google's Chrome EC
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_ACPI_MEMMAP || ec/google/chromeec || bool ||  ||
 +
When defined, ACPI accesses EC memmap data on ports 66h/62h. When
 +
not defined, the memmap data is instead accessed on 900h-9ffh via
 +
the LPC bus.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_BOARDID || ec/google/chromeec || bool ||  ||
 +
Provides common routine for reading boardid from Chrome EC.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_I2C || ec/google/chromeec || bool ||  ||
 +
Google's Chrome EC via I2C bus.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_I2C_PROTO3 || ec/google/chromeec || bool ||  ||
 +
Use only proto3 for i2c EC communication.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_LPC || ec/google/chromeec || bool ||  ||
 +
Google Chrome EC via LPC bus.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_MEC || ec/google/chromeec || bool ||  ||
 +
Microchip EC variant for LPC register access.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_PD || ec/google/chromeec || bool ||  ||
 +
Indicates that Google's Chrome USB PD chip is present.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_SPI || ec/google/chromeec || bool ||  ||
 +
Google's Chrome EC via SPI bus.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US || ec/google/chromeec || int ||  ||
 +
Force delay after asserting /CS to allow EC to wakeup.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_BOARDNAME || ec/google/chromeec || string || Chrome EC board name for EC ||
 +
The board name used in the Chrome EC code base to build
 +
the EC firmware.  If set, the coreboot build with also
 +
build the EC firmware and add it to the image.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_PD_BOARDNAME || ec/google/chromeec || string || Chrome EC board name for PD ||
 +
The board name used in the Chrome EC code base to build
 +
the PD firmware.  If set, the coreboot build with also
 +
build the EC firmware and add it to the image.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_RTC || ec/google/chromeec || bool || Enable Chrome OS EC RTC ||
 +
Enable support for the real-time clock on the Chrome OS EC. This
 +
uses the EC_CMD_RTC_GET_VALUE command to read the current time.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_FIRMWARE_NONE || ec/google/chromeec || bool || No EC firmware is included ||
 +
Disable building and including any EC firmware in the image.
 +
 
 +
config EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL
 +
bool "External EC firmware is included"
 +
help
 +
Include EC firmware binary in the image from an external source.
 +
It is expected to be built externally.
 +
 
 +
config EC_GOOGLE_CHROMEEC_FIRMWARE_BUILTIN
 +
bool "Builtin EC firmware is included"
 +
help
 +
Build and include EC firmware binary in the image.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_FIRMWARE_FILE || ec/google/chromeec || string || Chrome EC firmware path and filename ||
 +
The path and filename of the EC firmware file to use.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_PD_FIRMWARE_NONE || ec/google/chromeec || bool || No PD firmware is included ||
 +
Disable building and including any PD firmware in the image.
 +
 
 +
config EC_GOOGLE_CHROMEEC_PD_FIRMWARE_EXTERNAL
 +
bool "External PD firmware is included"
 +
help
 +
Include PD firmware binary in the image from an external source.
 +
It is expected to be built externally.
 +
 
 +
config EC_GOOGLE_CHROMEEC_PD_FIRMWARE_BUILTIN
 +
bool "Builtin PD firmware is included"
 +
help
 +
Build and include PD firmware binary in the image.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_PD_FIRMWARE_FILE || ec/google/chromeec || string || Chrome EC firmware path and filename for PD ||
 +
The path and filename of the PD firmware file to use.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_GOOGLE_CHROMEEC_SWITCHES || ec/google/chromeec || bool ||  ||
 +
Enable support for Chrome OS mode switches provided by the Chrome OS
 +
EC.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_QUANTA_IT8518 || ec/quanta/it8518 || bool ||  ||
 +
Interface to QUANTA IT8518 Embedded Controller.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_QUANTA_ENE_KB3940Q || ec/quanta/ene_kb3940q || bool ||  ||
 +
Interface to QUANTA ENE KB3940Q Embedded Controller.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_HP_KBC1126 || ec/hp/kbc1126 || bool ||  ||
 +
Interface to SMSC KBC1126 embedded controller in HP laptops.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Please select the following otherwise your laptop cannot be powered on. ||
 +
|- bgcolor="#eeeeee"
 +
| KBC1126_FIRMWARE || ec/hp/kbc1126 || bool || Add firmware images for KBC1126 EC ||
 +
Select this option to add the two firmware blobs for KBC1126.
 +
You need these two blobs to power on your machine.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| KBC1126_FW1 || ec/hp/kbc1126 || string || KBC1126 firmware #1 path and filename ||
 +
The path and filename of the file to use as KBC1126 firmware #1.
 +
You can use util/kbc1126/kbc1126_ec_dump to dump it from the
 +
vendor firmware.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| KBC1126_FW2 || ec/hp/kbc1126 || string || KBC1126 filename #2 path and filename ||
 +
The path and filename of the file to use as KBC1126 firmware #2.
 +
You can use util/kbc1126/kbc1126_ec_dump to dump it from the
 +
vendor firmware.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| H8_BEEP_ON_DEATH || ec/lenovo/h8 || bool || Beep on fatal error ||
 +
Beep when encountered a fatal error.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| H8_FLASH_LEDS_ON_DEATH || ec/lenovo/h8 || bool || Flash LEDs on fatal error ||
 +
Flash all LEDs when encountered a fatal error.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| H8_SUPPORT_BT_ON_WIFI || ec/lenovo/h8 || bool || Support bluetooth on wifi cards ||
 +
Disable BDC detection and assume bluetooth is installed. Required for
 +
bluetooth on wifi cards, as it's not possible to detect it in coreboot.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_RODA_IT8518 || ec/roda/it8518 || bool ||  ||
 +
Interface to IT8518 embedded controller in Roda notebooks.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_SMSC_MEC1308 || ec/smsc/mec1308 || bool ||  ||
 +
Shared memory mailbox interface to SMSC MEC1308 Embedded Controller.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_PURISM_LIBREM || ec/purism/librem || bool ||  ||
 +
Purism Librem EC
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_COMPAL_ENE932 || ec/compal/ene932 || bool ||  ||
 +
Interface to COMPAL ENE932 Embedded Controller.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EC_KONTRON_IT8516E || ec/kontron/it8516e || bool ||  ||
 +
Kontron uses an ITE IT8516E on the KTQM77. Its firmware might
 +
come from Fintek (mentioned as Finte*c* somewhere in their Linux
 +
driver).
 +
The KTQM77 is an embedded board and the IT8516E seems to be
 +
only used for fan control and GPIO.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Intel FSP ||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_FSP_BIN || drivers/intel/fsp1_0 || bool || Use Intel Firmware Support Package ||
 +
Select this option to add an Intel FSP binary to
 +
the resulting coreboot image.
 +
 
 +
Note: Without this binary, coreboot builds relying on the FSP
 +
will not boot
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_FILE || drivers/intel/fsp1_0 || string || Intel FSP binary path and filename ||
 +
The path and filename of the Intel FSP binary for this platform.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_LOC || drivers/intel/fsp1_0 || hex || Intel FSP Binary location in CBFS ||
 +
The location in CBFS that the FSP is located. This must match the
 +
value that is set in the FSP binary.  If the FSP needs to be moved,
 +
rebase the FSP with Intel's BCT (tool).
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_FSP_FAST_BOOT || drivers/intel/fsp1_0 || bool || Enable Fast Boot ||
 +
Enabling this feature will force the MRC data to be cached in NV
 +
storage to be used for speeding up boot time on future reboots
 +
and/or power cycles.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ENABLE_MRC_CACHE || drivers/intel/fsp1_0 || bool ||  ||
 +
Enabling this feature will cause MRC data to be cached in NV storage.
 +
This can either be used for fast boot, or just because the FSP wants
 +
it to be saved.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MRC_CACHE_FMAP || drivers/intel/fsp1_0 || bool || Use MRC Cache in FMAP ||
 +
Use the region "RW_MRC_CACHE" in FMAP instead of "mrc.cache" in CBFS.
 +
You must define a region in your FMAP named "RW_MRC_CACHE".
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MRC_CACHE_SIZE || drivers/intel/fsp1_0 || hex || Fast Boot Data Cache Size ||
 +
This is the amount of space in NV storage that is reserved for the
 +
fast boot data cache storage.
 +
 
 +
WARNING: Because this area will be erased and re-written, the size
 +
should be a full sector of the flash ROM chip and nothing else should
 +
be included in CBFS in any sector that the fast boot cache data is in.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VIRTUAL_ROM_SIZE || drivers/intel/fsp1_0 || hex || Virtual ROM Size ||
 +
This is used to calculate the offset of the MRC data cache in NV
 +
Storage for fast boot.  If in doubt, leave this set to the default
 +
which sets the virtual size equal to the ROM size.
 +
 
 +
Example: Cougar Canyon 2 has two 8 MB SPI ROMs.  When the SPI ROMs are
 +
loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB.  When
 +
the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM
 +
size is 16 MB.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CACHE_ROM_SIZE_OVERRIDE || drivers/intel/fsp1_0 || hex || Cache ROM Size ||
 +
This is the size of the cachable area that is passed into the FSP in
 +
the early initialization.  Typically this should be the size of the CBFS
 +
area, but the size must be a power of 2 whereas the CBFS size does not
 +
have this limitation.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USE_GENERIC_FSP_CAR_INC || drivers/intel/fsp1_0 || bool ||  ||
 +
The chipset can select this to use a generic cache_as_ram.inc file
 +
that should be good for all FSP based platforms.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FSP_USES_UPD || drivers/intel/fsp1_0 || bool ||  ||
 +
If this FSP uses UPD/VPD data regions, select this in the chipset Kconfig.
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_INTEL_FIRMWARE || southbridge/intel/common/firmware || bool ||  ||
 +
Chipset uses the Intel Firmware Descriptor to describe the
 +
layout of the SPI ROM chip.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Intel Firmware ||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_IFD_BIN || southbridge/intel/common/firmware || bool || Add Intel descriptor.bin file ||
 +
The descriptor binary
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EM100 || southbridge/intel/common/firmware || bool || Configure IFD for EM100 usage ||
 +
Set SPI frequency to 20MHz and disable Dual Output Fast Read Support
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_ME_BIN || southbridge/intel/common/firmware || bool || Add Intel ME/TXE firmware ||
 +
The Intel processor in the selected system requires a special firmware
 +
for an integrated controller.  This might be called the Management
 +
Engine (ME), the Trusted Execution Engine (TXE) or something else
 +
depending on the chip. This firmware might or might not be available
 +
in coreboot's 3rdparty/blobs repository. If it is not and if you don't
 +
have access to the firmware from elsewhere, you can still build
 +
coreboot without it. In this case however, you'll have to make sure
 +
that you don't overwrite your ME/TXE firmware on your flash ROM.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CHECK_ME || southbridge/intel/common/firmware || bool || Verify the integrity of the supplied ME/TXE firmware ||
 +
Verify the integrity of the supplied Intel ME/TXE firmware before
 +
proceeding with the build, in order to prevent an accidental loading
 +
of a corrupted ME/TXE image.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USE_ME_CLEANER || southbridge/intel/common/firmware || bool || Strip down the Intel ME/TXE firmware ||
 +
Use me_cleaner to remove all the non-fundamental code from the Intel
 +
ME/TXE firmware.
 +
The resulting Intel ME/TXE firmware will have only the code
 +
responsible for the very basic hardware initialization, leaving the
 +
ME/TXE subsystem essentially in a disabled state.
 +
 
 +
Don't flash a modified ME/TXE firmware and a new coreboot image at the
 +
same time, test them in two different steps.
 +
 
 +
WARNING: this tool isn't based on any official Intel documentation but
 +
only on reverse engineering and trial & error.
 +
 
 +
See the project's page
 +
https://github.com/corna/me_cleaner
 +
or the wiki
 +
https://github.com/corna/me_cleaner/wiki/How-to-apply-me_cleaner
 +
https://github.com/corna/me_cleaner/wiki/How-does-it-work%3F
 +
https://github.com/corna/me_cleaner/wiki/me_cleaner-status
 +
for more info about this tool
 +
 
 +
If unsure, say N.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| || || (comment) || || Please test the modified ME/TXE firmware and coreboot in two steps ||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_GBE_BIN || southbridge/intel/common/firmware || bool || Add gigabit ethernet firmware ||
 +
The integrated gigabit ethernet controller needs a firmware file.
 +
Select this if you are going to use the PCH integrated controller
 +
and have the firmware.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_EC_BIN || southbridge/intel/common/firmware || bool || Add EC firmware ||
 +
The embedded controller needs a firmware file.
 +
 
 +
Select this if you are going to use the PCH integrated controller
 +
and have the EC firmware. EC firmware will be added to final image
 +
through ifdtool.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BUILD_WITH_FAKE_IFD || southbridge/intel/common/firmware || bool || Build with a fake IFD ||
 +
If you don't have an Intel Firmware Descriptor (descriptor.bin) for your
 +
board, you can select this option and coreboot will build without it.
 +
The resulting coreboot.rom will not contain all parts required
 +
to get coreboot running on your board. You can however write only the
 +
BIOS section to your board's flash ROM and keep the other sections
 +
untouched. Unfortunately the current version of flashrom doesn't
 +
support this yet. But there is a patch pending [1].
 +
 
 +
WARNING: Never write a complete coreboot.rom to your flash ROM if it
 +
was built with a fake IFD. It just won't work.
 +
 
 +
[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| IFD_BIOS_SECTION || southbridge/intel/common/firmware || string || BIOS Region Starting:Ending addresses within the ROM ||
 +
The BIOS region is typically the size of the CBFS area, and is located
 +
at the end of the ROM space.
 +
 
 +
For an 8MB ROM with a 3MB CBFS area, this would look like:
 +
0x00500000:0x007fffff
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| IFD_ME_SECTION || southbridge/intel/common/firmware || string || ME/TXE Region Starting:Ending addresses within the ROM ||
 +
The ME/TXE region typically starts at around 0x1000 and often fills the
 +
ROM space not used by CBFS.
 +
 
 +
For an 8MB ROM with a 3MB CBFS area, this might look like:
 +
0x00001000:0x004fffff
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| IFD_GBE_SECTION || southbridge/intel/common/firmware || string || GBE Region Starting:Ending addresses within the ROM ||
 +
The Gigabit Ethernet ROM region is used when an Intel NIC is built into
 +
the Southbridge/SOC and the platform uses this device instead of an external
 +
PCIe NIC.  It will be located between the ME/TXE and the BIOS region.
 +
 
 +
Leave this empty if you're unsure.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| IFD_PLATFORM_SECTION || southbridge/intel/common/firmware || string || Platform Region Starting:Ending addresses within the Rom ||
 +
The Platform region is used for platform specific data.
 +
It will be located between the ME/TXE and the BIOS region.
 +
 
 +
Leave this empty if you're unsure.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| LOCK_MANAGEMENT_ENGINE || southbridge/intel/common/firmware || bool || Lock ME/TXE section ||
 +
The Intel Firmware Descriptor supports preventing write accesses
 +
from the host to the ME or TXE section in the firmware
 +
descriptor. If the section is locked, it can only be overwritten
 +
with an external SPI flash programmer. You will want this if you
 +
want to increase security of your ROM image once you are sure
 +
that the ME/TXE firmware is no longer going to change.
 +
 
 +
If unsure, say N.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CBFS_SIZE || southbridge/intel/common/firmware || hex ||  ||
 +
Reduce CBFS size to give room to the IFD blobs.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| UDK_VERSION || vendorcode/intel || int ||  ||
 +
UEFI Development Kit version for Platform
 +
 
 +
||
 +
||
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: AMD Platform Initialization || || || ||
 +
|- bgcolor="#eeeeee"
 +
| None || vendorcode/amd || None || AGESA source ||
 +
Select the method for including the AMD Platform Initialization
 +
code into coreboot.  Platform Initialization code is required for
 +
all AMD processors.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_AMD_AGESA_BINARY_PI || vendorcode/amd || bool || binary PI ||
 +
Use a binary PI package.  Generally, these will be stored in the
 +
"3rdparty/blobs" directory.  For some processors, these must be obtained
 +
directly from AMD Embedded Processors Group
 +
(http://www.amdcom/embedded).
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CPU_AMD_AGESA_OPENSOURCE || vendorcode/amd || bool || open-source AGESA ||
 +
Build the PI package ("AGESA") from source code in the "vendorcode"
 +
directory.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AGESA_BINARY_PI_VENDORCODE_PATH || vendorcode/amd/pi || string || AGESA PI directory path ||
 +
Specify where to find the AGESA header files
 +
for AMD platform initialization.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AGESA_BINARY_PI_FILE || vendorcode/amd/pi || string || AGESA PI binary file name ||
 +
Specify the binary file to use for AMD platform initialization.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AGESA_BINARY_PI_AS_STAGE || vendorcode/amd/pi || bool || AGESA Binary PI is added as stage to CBFS. ||
 +
AGESA will be added as a stage utilizing --xip cbfstool options
 +
as needed relocating the image to the proper location in memory-mapped
 +
cpu address space. It's required that the file be in ELF format
 +
containing the relocations necessary for relocating at runtime.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AGESA_SPLIT_MEMORY_FILES || vendorcode/amd/pi || bool || Split AGESA Binary PI into pre- and post-memory files. ||
 +
Specifies that AGESA is split into two binaries for pre- and
 +
post-memory.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AGESA_PRE_MEMORY_BINARY_PI_FILE || vendorcode/amd/pi || string ||  ||
 +
Specify the binary file to use for pre-memory AMD platform
 +
initialization.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AGESA_POST_MEMORY_BINARY_PI_FILE || vendorcode/amd/pi || string ||  ||
 +
Specify the binary file to use for post-memory AMD platform
 +
initialization.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| AGESA_BINARY_PI_LOCATION || vendorcode/amd/pi || hex || AGESA PI binary address in ROM ||
 +
Specify the ROM address at which to store the binary Platform
 +
Initialization code.
 +
 
 +
||
 +
 
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: ChromeOS || || || ||
 +
|- bgcolor="#eeeeee"
 +
| CHROMEOS || vendorcode/google/chromeos || bool || Build for ChromeOS ||
 +
Enable ChromeOS specific features like the GPIO sub table in
 +
the coreboot table. NOTE: Enabling this option on an unsupported
 +
board will most likely break your build.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NO_TPM_RESUME || vendorcode/google/chromeos || bool ||  ||
 +
On some boards the TPM stays powered up in S3. On those
 +
boards, booting Windows will break if the TPM resume command
 +
is sent during an S3 resume.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_REGULATORY_DOMAIN || vendorcode/google/chromeos || bool || Add regulatory domain methods ||
 +
This option is needed to add ACPI regulatory domain methods
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME || vendorcode/google/chromeos || bool ||  ||
 +
Disable the platform heirarchy on resume path if the firmware
 +
is involved in resume. The hierarchy is disabled prior to jumping
 +
to the OS.  Note that this option is sepcific to TPM2 boards.
 +
This option is auto selected if CHROMEOS because it matches with
 +
vboot_reference model which disables the platform hierarchy in
 +
the boot loader. However, those operations need to be symmetric
 +
on normal boot as well as resume and coreboot is only involved
 +
in the resume piece w.r.t. the platform hierarchy.
 +
 
 +
||
 +
 
 +
|- bgcolor="#eeeeee"
 +
| GOOGLE_SMBIOS_MAINBOARD_VERSION || vendorcode/google || bool ||  ||
 +
Provide a common implementation for mainboard version,
 +
which returns a formatted 'rev%d' board_id() string.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ARCH_RISCV_COMPRESSED || arch/riscv || bool ||  ||
 +
Enable this option if your RISC-V processor supports compressed
 +
instructions (RVC). Currently, this enables RVC for all stages.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ARCH_ARMV8_EXTENSION || arch/arm64/armv8 || int ||  ||
 +
Specify ARMv8 extension, for example '1' for ARMv8.1, to control the
 +
'-march' option passed into the compiler. Defaults to 0 for vanilla
 +
ARMv8 but may be overridden in the SoC's Kconfig.
 +
 
 +
All ARMv8 implementations are downwards-compatible, so this does not
 +
need to be changed unless specific features (e.g. new instructions)
 +
are used by the SoC's coreboot code.
 +
 
 +
||
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ARM64_SECURE_OS_FILE || arch/arm64 || string || Secure OS binary file ||
 +
Secure OS binary file.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ARM64_A53_ERRATUM_843419 || arch/arm64 || bool ||  ||
 +
Some early Cortex-A53 revisions had a hardware bug that results in
 +
incorrect address calculations in rare cases. This option enables a
 +
linker workaround to avoid those cases if your toolchain supports it.
 +
Should be selected automatically by SoCs that are affected.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USE_MARCH_586 || arch/x86 || bool ||  ||
 +
Allow a platform or processor to select to be compiled using
 +
the '-march=i586' option instead of the typical '-march=i686'
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| CBMEM_TOP_BACKUP || arch/x86 || bool ||  ||
 +
Platform implements non-volatile storage to cache cbmem_top()
 +
over stage transitions and optionally also over S3 suspend.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| LATE_CBMEM_INIT || arch/x86 || bool ||  ||
 +
Enable this in chipset's Kconfig if northbridge does not implement
 +
early cbmem_top() call for romstage. CBMEM tables will be allocated
 +
late in ramstage, after PCI devices resources are known.
 +
 
 +
WARNING: Late CBMEM initialization is deprecated. Platforms that
 +
don't support early CBMEM initialization will be removed after
 +
the release of coreboot 4.7.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PRERAM_CBMEM_CONSOLE_SIZE || arch/x86 || hex ||  ||
 +
Increase this value if preram cbmem console is getting truncated
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EARLY_EBDA_INIT || arch/x86 || bool ||  ||
 +
Initialize BIOS EBDA area early in romstage to allow bootloader to
 +
use this region for storing data which can be available across
 +
various stages. If user is selecting this option then its users
 +
responsibility to perform EBDA initialization call during romstage.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOTBLOCK_DEBUG_SPINLOOP || arch/x86 || bool ||  ||
 +
Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait
 +
for a JTAG debugger to break into the execution sequence.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP || arch/x86 || bool ||  ||
 +
Select this value to provide a routine to save the BIST and timestamp
 +
values.  The default code places the BIST value in MM0 and the
 +
timestamp value in MM2:MM1.  Another file is necessary when the CPU
 +
does not support the MMx register set.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VERSTAGE_DEBUG_SPINLOOP || arch/x86 || bool ||  ||
 +
Add a spin (JMP .) in assembly_entry.S during early verstage to wait
 +
for a JTAG debugger to break into the execution sequence.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ROMSTAGE_DEBUG_SPINLOOP || arch/x86 || bool ||  ||
 +
Add a spin (JMP .) in assembly_entry.S during early romstage to wait
 +
for a JTAG debugger to break into the execution sequence.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SKIP_MAX_REBOOT_CNT_CLEAR || arch/x86 || bool || Do not clear reboot count after successful boot ||
 +
Do not clear the reboot count immediately after successful boot.
 +
Set to allow the payload to control normal/fallback image recovery.
 +
Note that it is the responsibility of the payload to reset the
 +
normal boot bit to 1 after each successsful boot.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ACPI_CPU_STRING || arch/x86 || string ||  ||
 +
Sets the ACPI name string in the processor scope as written by
 +
the acpigen function. Default is \_PR.CPxx. Note that you need
 +
the \ escape character in the string.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| COLLECT_TIMESTAMPS_NO_TSC || arch/x86 || bool ||  ||
 +
Use a non-TSC platform-dependent source for timestamps.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| COLLECT_TIMESTAMPS_TSC || arch/x86 || bool ||  ||
 +
Use the TSC as the timestamp source.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PAGING_IN_CACHE_AS_RAM || arch/x86 || bool ||  ||
 +
Chipsets scan select this option to preallocate area in cache-as-ram
 +
for storing paging data structures. PAE paging is currently the
 +
only thing being supported.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NUM_CAR_PAGE_TABLE_PAGES || arch/x86 || int ||  ||
 +
The number of 4KiB pages that should be pre-allocated for page tables.
 +
 
 +
||
 +
 
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: Devices || || || ||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_VGA_TEXT_FRAMEBUFFER || device || bool ||  ||
 +
Selected by graphics drivers that support legacy VGA text mode.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_VBE_LINEAR_FRAMEBUFFER || device || bool ||  ||
 +
Selected by graphics drivers that can set up a VBE linear-framebuffer
 +
mode.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_LINEAR_FRAMEBUFFER || device || bool ||  ||
 +
Selected by graphics drivers that can set up a generic linear
 +
framebuffer.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| HAVE_FSP_GOP || device || bool ||  ||
 +
Selected by drivers that support to run a blob that implements
 +
the Graphics Output Protocol (GOP).
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_HAS_NATIVE_VGA_INIT || device || bool ||  ||
 +
Selected by mainboards / drivers that provide native graphics
 +
init within coreboot.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_FORCE_NATIVE_VGA_INIT || device || bool ||  ||
 +
Selected by mainboards / chipsets whose graphics driver can't or
 +
shouldn't be disabled.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_HAS_LIBGFXINIT || device || bool ||  ||
 +
Selected by mainboards that implement support for `libgfxinit`.
 +
Usually this requires a list of ports to be probed for displays.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_DO_NATIVE_VGA_INIT || device || bool || Use native graphics init ||
 +
Some mainboards, such as the Google Link, allow initializing the
 +
display without the need of a binary only VGA OPROM. Enabling this
 +
option may be faster, but also lacks flexibility in setting modes.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| MAINBOARD_USE_LIBGFXINIT || device || bool || Use libgfxinit ||
 +
Use the SPARK library `libgfxinit` for the native graphics
 +
initialization. This requires an Ada toolchain.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_ROM_RUN || device || bool || Run VGA Option ROMs ||
 +
Execute VGA Option ROMs in coreboot if found. This can be used
 +
to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS
 +
payload.
 +
 
 +
When using a SeaBIOS payload it runs all option ROMs with much
 +
more complete BIOS interrupt services available than coreboot,
 +
which some option ROMs require in order to function correctly.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| RUN_FSP_GOP || device || bool || Run a GOP driver ||
 +
Some platforms (e.g. Intel Braswell and Skylake/Kaby Lake) support
 +
to run a GOP blob. This option enables graphics initialization with
 +
such a blob.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| NO_GFX_INIT || device || bool || None ||
 +
Select this to not perform any graphics initialization in
 +
coreboot. This is useful if the payload (e.g. SeaBIOS) can
 +
initialize graphics or if pre-boot graphics are not required.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| S3_VGA_ROM_RUN || device || bool || Re-run VGA Option ROMs on S3 resume ||
 +
Execute VGA Option ROMs in coreboot when resuming from S3 suspend.
 +
 
 +
When using a SeaBIOS payload it runs all option ROMs with much
 +
more complete BIOS interrupt services available than coreboot,
 +
which some option ROMs require in order to function correctly.
 +
 
 +
If unsure, say N when using SeaBIOS as payload, Y otherwise.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ALWAYS_LOAD_OPROM || device || bool ||  ||
 +
Always load option ROMs if any are found. The decision to run
 +
the ROM is still determined at runtime, but the distinction
 +
between loading and not running comes into play for CHROMEOS.
 +
 
 +
An example where this is required is that VBT (Video BIOS Tables)
 +
are needed for the kernel's display driver to know how a piece of
 +
hardware is configured to be used.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ALWAYS_RUN_OPROM || device || bool ||  ||
 +
Always uncondtionally run the option regardless of other
 +
policies.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ON_DEVICE_ROM_LOAD || device || bool || Load Option ROMs on PCI devices ||
 +
Load Option ROMs stored on PCI/PCIe/AGP VGA devices in coreboot.
 +
 
 +
If disabled, only Option ROMs stored in CBFS will be executed by
 +
coreboot. If you are concerned about security, you might want to
 +
disable this option, but it might leave your system in a state of
 +
degraded functionality.
 +
 
 +
When using a SeaBIOS payload it runs all option ROMs with much
 +
more complete BIOS interrupt services available than coreboot,
 +
which some option ROMs require in order to function correctly.
 +
 
 +
If unsure, say N when using SeaBIOS as payload, Y otherwise.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PCI_OPTION_ROM_RUN_REALMODE || device || bool || Native mode ||
 +
If you select this option, PCI Option ROMs will be executed
 +
natively on the CPU in real mode. No CPU emulation is involved,
 +
so this is the fastest, but also the least secure option.
 +
(only works on x86/x64 systems)
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PCI_OPTION_ROM_RUN_YABEL || device || bool || Secure mode ||
 +
If you select this option, the x86emu CPU emulator will be used to
 +
execute PCI Option ROMs.
 +
 
 +
This option prevents Option ROMs from doing dirty tricks with the
 +
system (such as installing SMM modules or hypervisors), but it is
 +
also significantly slower than the native Option ROM initialization
 +
method.
 +
 
 +
This is the default choice for non-x86 systems.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| YABEL_PCI_ACCESS_OTHER_DEVICES || device || bool || Allow Option ROMs to access other devices ||
 +
Per default, YABEL only allows Option ROMs to access the PCI device
 +
that they are associated with. However, this causes trouble for some
 +
onboard graphics chips whose Option ROM needs to reconfigure the
 +
north bridge.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG || device || bool || Fake success on writing other device's config space ||
 +
By default, YABEL aborts when the Option ROM tries to write to other
 +
devices' config spaces. With this option enabled, the write doesn't
 +
follow through, but the Option ROM is allowed to go on.
 +
This can create issues such as hanging Option ROMs (if it depends on
 +
that other register changing to the written value), so test for
 +
impact before using this option.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| YABEL_VIRTMEM_LOCATION || device || hex || Location of YABEL's virtual memory ||
 +
YABEL requires 1MB memory for its CPU emulation. This memory is
 +
normally located at 16MB.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| YABEL_DIRECTHW || device || bool || Direct hardware access ||
 +
YABEL consists of two parts: It uses x86emu for the CPU emulation and
 +
additionally provides a PC system emulation that filters bad device
 +
and memory access (such as PCI config space access to other devices
 +
than the initialized one).
 +
 
 +
When choosing this option, x86emu will pass through all hardware
 +
accesses to memory and I/O devices to the underlying memory and I/O
 +
addresses. While this option prevents Option ROMs from doing dirty
 +
tricks with the CPU (such as installing SMM modules or hypervisors),
 +
they can still access all devices in the system.
 +
Enable this option for a good compromise between security and speed.
 +
 
 +
||
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: Display || || || ||
 +
|- bgcolor="#eeeeee"
 +
| FRAMEBUFFER_SET_VESA_MODE || device || bool || Set framebuffer graphics resolution ||
 +
Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console)
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| FRAMEBUFFER_SET_VESA_MODE || device || bool || framebuffer graphics resolution ||
 +
This option sets the resolution used for the coreboot framebuffer (and
 +
bootsplash screen).
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| BOOTSPLASH || device || bool || Show graphical bootsplash ||
 +
This option shows a graphical bootsplash screen. The graphics are
 +
loaded from the CBFS file bootsplash.jpg.
 +
 
 +
You can either specify the location and file name of the
 +
image in the 'General' section or add it manually to CBFS, using,
 +
for example, cbfstool.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_TEXT_FRAMEBUFFER || device || bool || Legacy VGA text mode ||
 +
If this option is enabled, coreboot will initialize graphics in
 +
legacy VGA text mode or, if a VGA BIOS is used and a VESA mode set,
 +
switch to text mode before handing control to a payload.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VBE_LINEAR_FRAMEBUFFER || device || bool || VESA framebuffer ||
 +
This option keeps the framebuffer mode set after coreboot finishes
 +
execution. If this option is enabled, coreboot will pass a
 +
framebuffer entry in its coreboot table and the payload will need a
 +
compatible driver.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| GENERIC_LINEAR_FRAMEBUFFER || device || bool || Linear \"high-resolution\" framebuffer ||
 +
This option enables a high-resolution, linear framebuffer. If this
 +
option is enabled, coreboot will pass a framebuffer entry in its
 +
coreboot table and the payload will need a compatible driver.
 +
 
 +
||
 +
 
 +
|- bgcolor="#eeeeee"
 +
| PCIEXP_COMMON_CLOCK || device || bool || Enable PCIe Common Clock ||
 +
Detect and enable Common Clock on PCIe links.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PCIEXP_ASPM || device || bool || Enable PCIe ASPM ||
 +
Detect and enable ASPM (Active State Power Management) on PCIe links.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PCIEXP_CLK_PM || device || bool || Enable PCIe Clock Power Management ||
 +
Detect and enable Clock Power Management on PCIe.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| PCIEXP_L1_SUB_STATE || device || bool || Enable PCIe ASPM L1 SubState ||
 +
Detect and enable ASPM on PCIe links.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| EARLY_PCI_BRIDGE || device || bool || Early PCI bridge ||
 +
While coreboot is executing code from ROM, the coreboot resource
 +
allocator has not been running yet. Hence PCI devices living behind
 +
a bridge are not yet visible to the system.
 +
 
 +
This option enables static configuration for a single pre-defined
 +
PCI bridge function on bus 0.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SUBSYSTEM_VENDOR_ID || device || hex || Override PCI Subsystem Vendor ID ||
 +
This config option will override the devicetree settings for
 +
PCI Subsystem Vendor ID.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SUBSYSTEM_DEVICE_ID || device || hex || Override PCI Subsystem Device ID ||
 +
This config option will override the devicetree settings for
 +
PCI Subsystem Device ID.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS || device || bool || Add a VGA BIOS image ||
 +
Select this option if you have a VGA BIOS image that you would
 +
like to add to your ROM.
 +
 
 +
You will be able to specify the location and file name of the
 +
image later.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_FILE || device || string || VGA BIOS path and filename ||
 +
The path and filename of the file to use as VGA BIOS.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| VGA_BIOS_ID || device || string || VGA device PCI IDs ||
 +
The comma-separated PCI vendor and device ID that would associate
 +
your VGA BIOS to your video card.
 +
 
 +
Example: 1106,3230
 +
 
 +
In the above example 1106 is the PCI vendor ID (in hex, but without
 +
the "0x" prefix) and 3230 specifies the PCI device ID of the
 +
video card (also in hex, without "0x" prefix).
 +
 
 +
Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| INTEL_GMA_ADD_VBT_DATA_FILE || device || bool || Add a Video Bios Table (VBT) binary to CBFS ||
 +
Add a VBT data file to CBFS. The VBT describes the integrated
 +
GPU and connections, and is needed by the GOP driver integrated into
 +
FSP and the OS driver in order to initialize the display.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| INTEL_GMA_VBT_FILE || device || string || VBT binary path and filename ||
 +
The path and filename of the VBT binary.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| SOFTWARE_I2C || device || bool || Enable I2C controller emulation in software ||
 +
This config option will enable code to override the i2c_transfer
 +
routine with a (simple) software emulation of the protocol. This may
 +
be useful for debugging or on platforms where a driver for the real
 +
I2C controller is not (yet) available. The platform code needs to
 +
provide bindings to manually toggle I2C lines.
 +
 
 +
||
 +
 
 +
|- bgcolor="#6699dd"
 +
! align="left" | Menu: Generic Drivers || || || ||
 +
|- bgcolor="#eeeeee"
 +
| ELOG || drivers/elog || bool || Support for flash based event log ||
 +
Enable support for flash based event logging.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ELOG_CBMEM || drivers/elog || bool || Store a copy of ELOG in CBMEM ||
 +
This option will have ELOG store a copy of the flash event log
 +
in a CBMEM region and export that address in SMBIOS to the OS.
 +
This is useful if the ELOG location is not in memory mapped flash,
 +
but it means that events added at runtime via the SMI handler
 +
will not be reflected in the CBMEM copy of the log.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ELOG_GSMI || drivers/elog || bool || SMI interface to write and clear event log ||
 +
This interface is compatible with the linux kernel driver
 +
available with CONFIG_GOOGLE_GSMI and can be used to write
 +
kernel reset/shutdown messages to the event log.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ELOG_BOOT_COUNT || drivers/elog || bool || Maintain a monotonic boot number in CMOS ||
 +
Store a monotonic boot number in CMOS and provide an interface
 +
to read the current value and increment the counter.  This boot
 +
counter will be logged as part of the System Boot event.
 +
 
 +
||
 +
|- bgcolor="#eeeeee"
 +
| ELOG_BOOT_COUNT_CMOS_OFFSET || drivers/elog || int || Offset in CMOS to store the boot count ||
 +
This value must be greater than 16 bytes so as not to interfere
 +
with the standard RTC region.  Requires 8 bytes.
 +
 
 +
||
 +
||
 +
|- bgcolor="#eeeeee"
 +
| USBDEBUG || drivers/usb || bool || USB 2.0 EHCI debug dongle support ||
 +
This option allows you to use a so-called USB EHCI Debug device
 +
(such as the Ajays NET20DC, AMIDebug RX, or a system using the
 +
Linux "EHCI Debug Device gadget" driver found in recent kernel)
 +
to retrieve the coreboot debug messages (instead, or in addition
 +
to, a serial port).
 +
 
 +
This feature is NOT supported on all chipsets in coreboot!
 +
 
 +
It also requires a USB2 controller which supports the EHCI
 +
Debug Port capability.
 +
 
 +
See https://www.coreboot.org/EHCI_Debug_Port for an up-to-date list
 +
of supported controllers.
 +
 
 +
If unsure, say N.
 +