Difference between revisions of "Coreboot Options"
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This is an automatically generated list of '''coreboot compile-time options'''. | This is an automatically generated list of '''coreboot compile-time options'''. | ||
Last update: | Last update: 2016/02/19 11:53:53. (r4.3-262-g38cd375) | ||
{| border="0" style="font-size: smaller" | {| border="0" style="font-size: smaller" | ||
|- bgcolor="#6699dd" | |- bgcolor="#6699dd" | ||
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|- bgcolor="#6699dd" | |- bgcolor="#6699dd" | ||
! align="left" | Menu: General setup || || || || | ! align="left" | Menu: General setup || || || || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| LOCALVERSION || toplevel || string || Local version string || | | LOCALVERSION || toplevel || string || Local version string || | ||
Line 52: | Line 44: | ||
This option allows you to select the compiler used for building | This option allows you to select the compiler used for building | ||
coreboot. | coreboot. | ||
You must build the coreboot crosscompiler for the board that you | |||
have selected. | |||
To build all the GCC crosscompilers (takes a LONG time), run: | |||
make crossgcc | |||
For help on individual architectures, run the command: | |||
make help_toolchain | |||
|| | || | ||
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|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| COMPILER_LLVM_CLANG || toplevel || bool || LLVM/clang || | | COMPILER_LLVM_CLANG || toplevel || bool || LLVM/clang (TESTING ONLY - Not currently working) || | ||
Use LLVM/clang to build coreboot. | Use LLVM/clang to build coreboot. To use this, you must build the | ||
coreboot version of the clang compiler. Run the command | |||
make clang | |||
Note that this option is not currently working correctly and should | |||
really only be selected if you're trying to work on getting clang | |||
operational. | |||
For details see http://clang.llvm.org. | For details see http://clang.llvm.org. | ||
Line 83: | Line 88: | ||
For details see https://ccache.samba.org. | For details see https://ccache.samba.org. | ||
|| | |||
|- bgcolor="#eeeeee" | |||
| FMD_GENPARSER || toplevel || bool || Generate flashmap descriptor parser using flex and bison || | |||
Enable this option if you are working on the flashmap descriptor | |||
parser and made changes to fmd_scanner.l or fmd_parser.y. | |||
Otherwise, say N to use the provided pregenerated scanner/parser. | |||
|| | || | ||
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| SCONFIG_GENPARSER || toplevel || bool || Generate SCONFIG parser using flex and bison || | | SCONFIG_GENPARSER || toplevel || bool || Generate SCONFIG parser using flex and bison || | ||
Enable this option if you are working on the sconfig device tree | Enable this option if you are working on the sconfig device tree | ||
parser and made changes to sconfig.l | parser and made changes to sconfig.l or sconfig.y. | ||
Otherwise, say N. | Otherwise, say N to use the provided pregenerated scanner/parser. | ||
|| | || | ||
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|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| RELOCATABLE_MODULES || toplevel || bool || | | RELOCATABLE_MODULES || toplevel || bool || || | ||
If RELOCATABLE_MODULES is selected then support is enabled for | If RELOCATABLE_MODULES is selected then support is enabled for | ||
building relocatable modules in the RAM stage. Those modules can be | building relocatable modules in the RAM stage. Those modules can be | ||
Line 184: | Line 197: | ||
The relocated ramstage is saved in an area specified by the | The relocated ramstage is saved in an area specified by the | ||
by the board and/or chipset. | by the board and/or chipset. | ||
|| | |||
|- bgcolor="#eeeeee" | |||
| FLASHMAP_OFFSET || toplevel || hex || Flash Map Offset || | |||
Offset of flash map in firmware image | |||
|| | || | ||
Line 190: | Line 208: | ||
Do not clear the reboot count immediately after successful boot. | Do not clear the reboot count immediately after successful boot. | ||
Set to allow the payload to control normal/fallback image recovery. | Set to allow the payload to control normal/fallback image recovery. | ||
Note that it is the responsibility of the payload to reset the | |||
normal boot bit to 1 after each successsful boot. | |||
|| | || | ||
Line 198: | Line 218: | ||
is a suitable file for further processing. | is a suitable file for further processing. | ||
The bootblock will not be modified. | The bootblock will not be modified. | ||
If unsure, select 'N' | |||
|| | || | ||
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|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| BOARD_ID_MANUAL || toplevel || bool || | | BOARD_ID_MANUAL || toplevel || bool || || | ||
If you want to maintain a board ID, but the hardware does not | If you want to maintain a board ID, but the hardware does not | ||
have straps to automatically determine the ID, you can say Y | have straps to automatically determine the ID, you can say Y | ||
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|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| RAM_CODE_SUPPORT || toplevel || bool || | | RAM_CODE_SUPPORT || toplevel || bool || || | ||
If enabled, coreboot discovers RAM configuration (value obtained by | If enabled, coreboot discovers RAM configuration (value obtained by | ||
reading board straps) and stores it in coreboot table. | reading board straps) and stores it in coreboot table. | ||
|| | || | ||
|- bgcolor="#eeeeee" | |||
| BOOTSPLASH_IMAGE || toplevel || bool || Add a bootsplash image || | |||
Select this option if you have a bootsplash image that you would | |||
like to add to your ROM. | |||
This will only add the image to the ROM. To actually run it check | |||
options under 'Display' section. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | BOOTSPLASH_FILE || toplevel || string || Bootsplash path and filename || | ||
The path and filename of the file to use as graphical bootsplash | |||
screen. The file format has to be jpg. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | ACPI_SATA_GENERATOR || acpi || bool || || | ||
Use acpi sata port generator. | |||
|| | || | ||
|| | || | ||
|- bgcolor="#6699dd" | |||
! align="left" | Menu: Mainboard || || || || | |||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | UART_FOR_CONSOLE || mainboard/intel/mohonpeak || int || || | ||
The Mohon Peak board uses COM2 (2f8) for the serial console. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | PAYLOAD_CONFIGFILE || mainboard/intel/mohonpeak || string || || | ||
The Avoton/Rangeley chip does not allow devices to write into the 0xe000 | |||
segment. This means that USB/SATA devices will not work in SeaBIOS unless | |||
we put the SeaBIOS buffer area down in the 0x9000 segment. | |||
|| | || | ||
|- bgcolor="# | |- bgcolor="#eeeeee" | ||
| UART_FOR_CONSOLE || mainboard/intel/littleplains || int || || | |||
The Little Plains board uses COM2 (2f8) for the serial console. | |||
|- bgcolor="# | || | ||
|- bgcolor="#eeeeee" | |||
| PAYLOAD_CONFIGFILE || mainboard/intel/littleplains || string || || | |||
The Avoton/Rangeley chip does not allow devices to write into the 0xe000 | |||
segment. This means that USB/SATA devices will not work in SeaBIOS unless | |||
we put the SeaBIOS buffer area down in the 0x9000 segment. | |||
|| | |||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | VGA_BIOS_FILE || mainboard/intel/strago || string || || | ||
The C0 version of the video bios gets computed from this name | |||
so that they can both be added. Only the correct one for the | |||
system will be run. | |||
|| | |||
|- bgcolor="#eeeeee" | |||
| VGA_BIOS_ID || mainboard/intel/strago || string || || | |||
The VGA_BIOS_ID for the C0 version of the video bios is hardcoded | |||
in soc/intel/braswell/Makefile.inc as 8086,22b1 | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | ENABLE_DP3_DAUGHTER_CARD_IN_J120 || mainboard/amd/lamar || bool || Use J120 as an additional graphics port || | ||
The PCI Express slot at J120 can be configured as an additional | |||
DisplayPort connector using an adapter card from AMD or as a normal | |||
PCI Express (x4) slot. | |||
By default, the connector is configured as a PCI Express (x4) slot. | |||
Select this option to enable the slot for use with one of AMD's | |||
passive graphics port expander cards (only available from AMD). | |||
|| | || | ||
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|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | DISPLAY_SPD_DATA || mainboard/google/cyan || bool || Display Memory Serial Presence Detect Data || | ||
When enabled displays the memory configuration data. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | VGA_BIOS_FILE || mainboard/google/cyan || string || || | ||
The C0 version of the video bios gets computed from this name | |||
so that they can both be added. Only the correct one for the | |||
system will be run. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | VGA_BIOS_ID || mainboard/google/cyan || string || || | ||
The VGA_BIOS_ID for the C0 version of the video bios is hardcoded | |||
in soc/intel/braswell/Makefile.inc as 8086,22b1 | |||
|| | || | ||
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|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | DRAM_SIZE_MB || mainboard/google/smaug || int || BCT boot media || | ||
Which boot media to configure the BCT for. | Which boot media to configure the BCT for. | ||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SMAUG_BCT_CFG_SPI || mainboard/google/smaug || bool || SPI || | ||
Configure the BCT for booting from SPI. | Configure the BCT for booting from SPI. | ||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SMAUG_BCT_CFG_EMMC || mainboard/google/smaug || bool || eMMC || | ||
Configure the BCT for booting from eMMC. | Configure the BCT for booting from eMMC. | ||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| BOOT_MEDIA_SPI_BUS || mainboard/google/ | | BOOT_MEDIA_SPI_BUS || mainboard/google/smaug || int || SPI bus with boot media ROM || | ||
Which SPI bus the boot media is connected to. | Which SPI bus the boot media is connected to. | ||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| BOOT_MEDIA_SPI_CHIP_SELECT || mainboard/google/ | | BOOT_MEDIA_SPI_CHIP_SELECT || mainboard/google/smaug || int || Chip select for SPI boot media || | ||
Which chip select to use for boot media. | Which chip select to use for boot media. | ||
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|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | MAINBOARD_PART_NUMBER || mainboard/google/nyan_big || string || BCT boot media || | ||
Which boot media to configure the BCT for. | |||
|| | |||
|- bgcolor="#eeeeee" | |||
| NYAN_BIG_BCT_CFG_SPI || mainboard/google/nyan_big || bool || SPI || | |||
Configure the BCT for booting from SPI. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | NYAN_BIG_BCT_CFG_EMMC || mainboard/google/nyan_big || bool || eMMC || | ||
Configure the BCT for booting from eMMC. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | BOOT_MEDIA_SPI_BUS || mainboard/google/nyan_big || int || SPI bus with boot media ROM || | ||
Which SPI bus the boot media is connected to. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | BOOT_MEDIA_SPI_CHIP_SELECT || mainboard/google/nyan_big || int || Chip select for SPI boot media || | ||
Which chip select to use for boot media. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | DRAM_SIZE_MB || mainboard/google/foster || int || BCT boot media || | ||
Which boot media to configure the BCT for. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | FOSTER_BCT_CFG_SPI || mainboard/google/foster || bool || SPI || | ||
Configure the BCT for booting from SPI. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | FOSTER_BCT_CFG_EMMC || mainboard/google/foster || bool || eMMC || | ||
Configure the BCT for booting from eMMC. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | BOOT_MEDIA_SPI_BUS || mainboard/google/foster || int || SPI bus with boot media ROM || | ||
Which SPI bus the boot media is connected to. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | BOOT_MEDIA_SPI_CHIP_SELECT || mainboard/google/foster || int || Chip select for SPI boot media || | ||
Which chip select to use for boot media. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | MAINBOARD_PART_NUMBER || mainboard/google/nyan || string || BCT boot media || | ||
Which boot media to configure the BCT for. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | NYAN_BCT_CFG_SPI || mainboard/google/nyan || bool || SPI || | ||
Configure the BCT for booting from SPI. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | NYAN_BCT_CFG_EMMC || mainboard/google/nyan || bool || eMMC || | ||
Configure the BCT for booting from eMMC. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | BOOT_MEDIA_SPI_BUS || mainboard/google/nyan || int || SPI bus with boot media ROM || | ||
Which SPI bus the boot media is connected to. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | BOOT_MEDIA_SPI_CHIP_SELECT || mainboard/google/nyan || int || Chip select for SPI boot media || | ||
Which chip select to use for boot media. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | BOARD_ASUS_F2A85_M_DDR3_VOLT_135 || mainboard/asus/f2a85-m || bool || 1.35V || | ||
Set DRR3 memory voltage to 1.35V | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | BOARD_ASUS_F2A85_M_DDR3_VOLT_150 || mainboard/asus/f2a85-m || bool || 1.50V || | ||
Set DRR3 memory voltage to 1.50V | |||
|| | |||
|- bgcolor="#eeeeee" | |||
| BOARD_ASUS_F2A85_M_DDR3_VOLT_165 || mainboard/asus/f2a85-m || bool || 1.65V || | |||
Set DRR3 memory voltage to 1.65V | |||
|| | |||
|- bgcolor="#eeeeee" | |||
| BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_135 || mainboard/asus/f2a85-m_le || bool || 1.35V || | |||
Set DRR3 memory voltage to 1.35V | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_150 || mainboard/asus/f2a85-m_le || bool || 1.50V || | ||
Set DRR3 memory voltage to 1.50V | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | BOARD_ASUS_F2A85_M_LE_DDR3_VOLT_165 || mainboard/asus/f2a85-m_le || bool || 1.65V || | ||
Set DRR3 memory voltage to 1.65V | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | DRIVERS_PS2_KEYBOARD || mainboard/purism/librem13 || None || || | ||
Default PS/2 Keyboard to enabled on this board. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | DRIVERS_UART_8250IO || mainboard/purism/librem13 || None || || | ||
This platform does not have any way to get standard | |||
serial output so disable it by default. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | NO_POST || mainboard/purism/librem13 || int || || | ||
This platform does not have any way to see POST codes | |||
so disable them by default. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | || || (comment) || || was acquired by ADLINK || | ||
|- bgcolor="#eeeeee" | |||
| ONBOARD_UARTS_RS485 || mainboard/lippert/spacerunner-lx || bool || Switch on-board serial ports to RS485 || | |||
board will | If selected, both on-board serial ports will operate in RS485 mode | ||
instead of RS232. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | ONBOARD_IDE_SLAVE || mainboard/lippert/spacerunner-lx || bool || Make on-board SSD act as Slave || | ||
If selected, the on-board SSD will act as IDE Slave instead of Master. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | BOARD_OLD_REVISION || mainboard/lippert/hurricane-lx || bool || Board is old pre-3.0 revision || | ||
Look on the bottom side for a number like 406-0001-30. The last 2 | |||
digits state the PCB revision (3.0 in this example). For 2.0 or older | |||
boards choose Y, for 3.0 and newer say N. | |||
Old revision boards need a jumper shorting the power button to | |||
power on automatically. You may enable the button only after this | |||
jumper has been removed. New revision boards are not restricted | |||
in this way, and always have the power button enabled. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | ONBOARD_UARTS_RS485 || mainboard/lippert/hurricane-lx || bool || Switch on-board serial ports to RS485 || | ||
If selected, both on-board serial ports will operate in RS485 mode | |||
instead of RS232. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | ONBOARD_UARTS_RS485 || mainboard/lippert/literunner-lx || bool || Switch on-board serial ports 1 & 2 to RS485 || | ||
If selected, the first two on-board serial ports will operate in RS485 | |||
mode instead of RS232. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | ONBOARD_IDE_SLAVE || mainboard/lippert/literunner-lx || bool || Make on-board CF socket act as Slave || | ||
If selected, the on-board Compact Flash card socket will act as IDE | |||
Slave instead of Master. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | ONBOARD_UARTS_RS485 || mainboard/lippert/roadrunner-lx || bool || Switch on-board serial ports to RS485 || | ||
If selected, both on-board serial ports will operate in RS485 mode | |||
instead of RS232. | |||
|| | || | ||
|- bgcolor="#6699dd" | |||
! align="left" | Menu: On-Chip Device Power Down Control || || || || | |||
|- bgcolor="#6699dd" | |||
! align="left" | Menu: Watchdog Timer setting || || || || | |||
|- bgcolor="#6699dd" | |||
! align="left" | Menu: IDE controller setting || || || || | |||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | IDE_STANDARD_COMPATIBLE || mainboard/dmp/vortex86ex || bool || Standard IDE Compatible || | ||
Built-in IDE controller PCI vendor/device ID is 17F3:1012, which | |||
is not recognized by some OSes. | |||
This option can change IDE controller PCI vendor/device ID to | |||
other value for software compatibility. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | IDE_COMPATIBLE_SELECTION || mainboard/dmp/vortex86ex || hex || IDE Compatible Selection || | ||
IDE controller PCI vendor/device ID value setting. | |||
Higher 16-bit is vendor ID, lower 16-bit is device ID. | |||
|| | || | ||
|| | |- bgcolor="#6699dd" | ||
! align="left" | Menu: GPIO setting || || || || | |||
|- bgcolor="#6699dd" | |||
! align="left" | Menu: UART setting || || || || | |||
|- bgcolor="#6699dd" | |||
! align="left" | Menu: LPT setting || || || || | |||
|- bgcolor="#eeeeee" | |||
| || || (comment) || || see under vendor LiPPERT || | |||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | BOARD_ROMSIZE_KB_16384 || mainboard || bool || ROM chip size || | ||
Select the size of the ROM chip you intend to flash coreboot on. | |||
The build system will take care of creating a coreboot.rom file | |||
of the matching size. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | COREBOOT_ROMSIZE_KB_64 || mainboard || bool || 64 KB || | ||
Choose this option if you have a 64 KB ROM chip. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | COREBOOT_ROMSIZE_KB_128 || mainboard || bool || 128 KB || | ||
Choose this option if you have a 128 KB ROM chip. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | COREBOOT_ROMSIZE_KB_256 || mainboard || bool || 256 KB || | ||
Choose this option if you have a 256 KB ROM chip. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | COREBOOT_ROMSIZE_KB_512 || mainboard || bool || 512 KB || | ||
Choose this option if you have a 512 KB ROM chip. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | COREBOOT_ROMSIZE_KB_1024 || mainboard || bool || 1024 KB (1 MB) || | ||
Choose this option if you have a 1024 KB (1 MB) ROM chip. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | COREBOOT_ROMSIZE_KB_2048 || mainboard || bool || 2048 KB (2 MB) || | ||
Choose this option if you have a 2048 KB (2 MB) ROM chip. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | COREBOOT_ROMSIZE_KB_4096 || mainboard || bool || 4096 KB (4 MB) || | ||
Choose this option if you have a 4096 KB (4 MB) ROM chip. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | COREBOOT_ROMSIZE_KB_8192 || mainboard || bool || 8192 KB (8 MB) || | ||
Choose this option if you have a 8192 KB (8 MB) ROM chip. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | COREBOOT_ROMSIZE_KB_12288 || mainboard || bool || 12288 KB (12 MB) || | ||
Choose this option if you have a 12288 KB (12 MB) ROM chip. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | COREBOOT_ROMSIZE_KB_16384 || mainboard || bool || 16384 KB (16 MB) || | ||
Choose this option if you have a 16384 KB (16 MB) ROM chip. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | ENABLE_POWER_BUTTON || mainboard || bool || Enable the power button || | ||
The selected mainboard can optionally have the power button tied | |||
to ground with a jumper so that the button appears to be | |||
constantly depressed. If this option is enabled and the jumper is | |||
installed then the board will turn on, but turn off again after a | |||
short timeout, usually 4 seconds. | |||
Select Y here if you have removed the jumper and want to use an | |||
actual power button. Select N if you have the jumper installed. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CBFS_SIZE || toplevel || hex || Size of CBFS filesystem in ROM || | ||
This is the part of the ROM actually managed by CBFS, located at the | |||
end of the ROM (passed through cbfstool -o) on x86 and at at the start | |||
of the ROM (passed through cbfstool -s) everywhere else. It defaults | |||
to span the whole ROM on all but Intel systems that use an Intel Firmware | |||
Descriptor. It can be overridden to make coreboot live alongside other | |||
components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE | |||
binaries. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | FMDFILE || toplevel || string || fmap description file in fmd format || | ||
The default | The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE, | ||
but in some cases more complex setups are required. | |||
When an fmd is specified, it overrides the default format. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CBFS_AUTOGEN_ATTRIBUTES || toplevel || bool || || | ||
If this option is selected, every file in cbfs which has a constraint | |||
regarding position or alignment will get an additional file attribute | |||
which describes this constraint. | |||
|| | || | ||
|- bgcolor="#6699dd" | |||
! align="left" | Menu: Chipset || || || || | |||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | || || (comment) || || SoC || | ||
|- bgcolor="#eeeeee" | |||
| MAINBOARD_DO_DSI_INIT || soc/nvidia/tegra210 || bool || Use dsi graphics interface || | |||
Initialize dsi display | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | MAINBOARD_DO_SOR_INIT || soc/nvidia/tegra210 || bool || Use dp graphics interface || | ||
Initialize dp display | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CONSOLE_SERIAL_TEGRA210_UARTA || soc/nvidia/tegra210 || bool || UARTA || | ||
Serial console on UART A. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CONSOLE_SERIAL_TEGRA210_UARTB || soc/nvidia/tegra210 || bool || UARTB || | ||
Serial console on UART B. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CONSOLE_SERIAL_TEGRA210_UARTC || soc/nvidia/tegra210 || bool || UARTC || | ||
Serial console on UART C. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CONSOLE_SERIAL_TEGRA210_UARTD || soc/nvidia/tegra210 || bool || UARTD || | ||
Serial console on UART D. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CONSOLE_SERIAL_TEGRA210_UARTE || soc/nvidia/tegra210 || bool || UARTE || | ||
Serial console on UART E. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| || | | CONSOLE_SERIAL_TEGRA210_UART_ADDRESS || soc/nvidia/tegra210 || hex || || | ||
Map the UART names to the respective MMIO addres. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | BOOTROM_SDRAM_INIT || soc/nvidia/tegra210 || bool || SoC BootROM does SDRAM init with full BCT || | ||
Use during Foster LPDDR4 bringup. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | TRUSTZONE_CARVEOUT_SIZE_MB || soc/nvidia/tegra210 || hex || Size of Trust Zone region || | ||
Size of Trust Zone area in MiB to reserve in memory map. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | TTB_SIZE_MB || soc/nvidia/tegra210 || hex || Size of TTB || | ||
Maximum size of Translation Table Buffer in MiB. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SEC_COMPONENT_SIZE_MB || soc/nvidia/tegra210 || hex || Size of resident EL3 components || | ||
Maximum size of resident EL3 components in MiB including BL31 and | |||
Secure OS. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | HAVE_MTC || soc/nvidia/tegra210 || bool || Add external Memory controller Training Code binary || | ||
Select this option to add emc training firmware | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | MTC_FILE || soc/nvidia/tegra210 || string || tegra mtc firmware filename || | ||
The filename of the mtc firmware | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | MTC_DIRECTORY || soc/nvidia/tegra210 || string || Directory where MTC firmware file is located || | ||
Path to directory where MTC firmware file is located. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | MTC_ADDRESS || soc/nvidia/tegra210 || hex || || | ||
The DRAM location where MTC firmware to be loaded in. This location | |||
needs to be consistent with the location defined in tegra_mtc.ld | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | MAINBOARD_DO_DSI_INIT || soc/nvidia/tegra132 || bool || Use dsi graphics interface || | ||
Initialize dsi display | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | MAINBOARD_DO_SOR_INIT || soc/nvidia/tegra132 || bool || Use dp graphics interface || | ||
Initialize dp display | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | MTS_DIRECTORY || soc/nvidia/tegra132 || string || Directory where MTS microcode files are located || | ||
Path to directory where MTS microcode files are located. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | TRUSTZONE_CARVEOUT_SIZE_MB || soc/nvidia/tegra132 || hex || Size of Trust Zone region || | ||
Size of Trust Zone area in MiB to reserve in memory map. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |||
| BOOTROM_SDRAM_INIT || soc/nvidia/tegra132 || bool || SoC BootROM does SDRAM init with full BCT || | |||
Use during Ryu LPDDR3 bringup | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SOC_INTEL_FSP_BAYTRAIL || soc/intel/fsp_baytrail || bool || || | ||
Bay Trail I part support using the Intel FSP. | |||
|| | |||
the | |- bgcolor="#eeeeee" | ||
the | | SMM_TSEG_SIZE || soc/intel/fsp_baytrail || hex || || | ||
cbfs. | This is set by the FSP | ||
|| | |||
|- bgcolor="#eeeeee" | |||
| VGA_BIOS_ID || soc/intel/fsp_baytrail || string || || | |||
This is the default PCI ID for the Bay Trail graphics | |||
devices. This string names the vbios ROM in cbfs. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | ENABLE_BUILTIN_COM1 || soc/intel/fsp_baytrail || bool || Enable built-in legacy Serial Port || | ||
The Baytrail SOC has one legacy serial port. Choose this option to | |||
configure the pads and enable it. This serial port can be used for | |||
the debug console. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | FSP_FILE || soc/intel/fsp_baytrail/fsp || string || || | ||
The path and filename of the Intel FSP binary for this platform. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | FSP_LOC || soc/intel/fsp_baytrail/fsp || hex || || | ||
This | The location in CBFS that the FSP is located. This must match the | ||
value that is set in the FSP binary. If the FSP needs to be moved, | |||
rebase the FSP with Intel's BCT (tool). | |||
The Bay Trail FSP is built with a preferred base address of | |||
0xFFFC0000. | |||
|| | || | ||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SOC_INTEL_BRASWELL || soc/intel/braswell || bool || || | ||
Braswell M/D part support. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |||
| DCACHE_RAM_SIZE || soc/intel/braswell || hex || Temporary RAM Size || | |||
The size of the cache-as-ram region required during bootblock | |||
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE | |||
must add up to a power of 2. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | DCACHE_RAM_ROMSTAGE_STACK_SIZE || soc/intel/braswell || hex || || | ||
The amount of anticipated stack usage from the data cache | |||
during pre-ram rom stage execution. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | RESET_ON_INVALID_RAMSTAGE_CACHE || soc/intel/braswell || bool || Reset the system on S3 wake when ramstage cache invalid. || | ||
The | The haswell romstage code caches the loaded ramstage program | ||
in SMM space. On S3 wake the romstage will copy over a fresh | |||
ramstage that was cached in the SMM space. This option determines | |||
the action to take when the ramstage cache is invalid. If selected | |||
the system will reset otherwise the ramstage will be reloaded from | |||
cbfs. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | ENABLE_BUILTIN_COM1 || soc/intel/braswell || bool || Enable builtin COM1 Serial Port || | ||
The PMC has a legacy COM1 serial port. Choose this option to | |||
configure the pads and enable it. This serial port can be used for | |||
the debug console. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SOC_INTEL_APOLLOLAKE || soc/intel/apollolake || bool || || | ||
Intel Apollolake support | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | DCACHE_RAM_SIZE || soc/intel/apollolake || hex || Length in bytes of cache-as-RAM || | ||
The size of the cache-as-ram region required during bootblock | |||
and/or romstage. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | DCACHE_BSP_STACK_SIZE || soc/intel/apollolake || hex || || | ||
The amount of anticipated stack usage in CAR by bootblock and | |||
other stages. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SOC_INTEL_BAYTRAIL || soc/intel/baytrail || bool || || | ||
Bay Trail M/D part support. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | HAVE_MRC || soc/intel/baytrail || bool || Add a Memory Reference Code binary || | ||
Select this option to add a blob containing | |||
memory reference code. | |||
Note: Without this binary coreboot will not work | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | MRC_FILE || soc/intel/baytrail || string || Intel memory refeference code path and filename || | ||
The path and filename of the file to use as System Agent | |||
binary. Note that this points to the sandybridge binary file | |||
which is will not work, but it serves its purpose to do builds. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | DCACHE_RAM_SIZE || soc/intel/baytrail || hex || || | ||
The size of the cache-as-ram region required during bootblock | |||
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE | |||
must add up to a power of 2. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | DCACHE_RAM_MRC_VAR_SIZE || soc/intel/baytrail || hex || || | ||
The amount of cache-as-ram region required by the reference code. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | DCACHE_RAM_ROMSTAGE_STACK_SIZE || soc/intel/baytrail || hex || || | ||
The amount of anticipated stack usage from the data cache | |||
during pre-RAM ROM stage execution. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | RESET_ON_INVALID_RAMSTAGE_CACHE || soc/intel/baytrail || bool || Reset the system on S3 wake when ramstage cache invalid. || | ||
This option is | The baytrail romstage code caches the loaded ramstage program | ||
in SMM space. On S3 wake the romstage will copy over a fresh | |||
ramstage that was cached in the SMM space. This option determines | |||
the action to take when the ramstage cache is invalid. If selected | |||
the system will reset otherwise the ramstage will be reloaded from | |||
cbfs. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | ENABLE_BUILTIN_COM1 || soc/intel/baytrail || bool || Enable builtin COM1 Serial Port || | ||
This | The PMC has a legacy COM1 serial port. Choose this option to | ||
configure the pads and enable it. This serial port can be used for | |||
the debug console. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | HAVE_REFCODE_BLOB || soc/intel/baytrail || bool || An external reference code blob should be put into cbfs. || | ||
The reference code blob will be placed into cbfs. | |||
code | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | REFCODE_BLOB_FILE || soc/intel/baytrail || string || Path and filename to reference code blob. || | ||
The path and filename to the file to be added to cbfs. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SOC_INTEL_QUARK || soc/intel/quark || bool || || | ||
Intel Quark support | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | ENABLE_BUILTIN_HSUART1 || soc/intel/quark || bool || Enable built-in HSUART1 || | ||
The Quark SoC has two HSUART. Choose this option to configure the pads | |||
and enable HSUART1, which can be used for the debug console. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | TTYS0_BASE || soc/intel/quark || hex || HSUART1 Base Address || | ||
Memory mapped MMIO of HSUART1. | |||
|| | |||
|- bgcolor="#eeeeee" | |||
| ENABLE_DEBUG_LED || soc/intel/quark || bool || || | |||
Enable the use of the SD LED for early debugging before serial output | |||
is available. Setting this LED indicates that control has reached the | |||
desired check point. | |||
|| | |||
|- bgcolor="#eeeeee" | |||
| ENABLE_DEBUG_LED_ESRAM || soc/intel/quark || bool || SD LED indicates ESRAM initialized || | |||
Indicate that ESRAM has been successfully initialized. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | ENABLE_DEBUG_LED_FINDFSP || soc/intel/quark || bool || SD LED indicates fsp.bin file was found || | ||
Indicate that fsp.bin was found. | |||
|| | |||
- | |- bgcolor="#eeeeee" | ||
| ENABLE_DEBUG_LED_TEMPRAMINIT || soc/intel/quark || bool || SD LED indicates TempRamInit was successful || | |||
Indicate that TempRamInit was successful. | |||
|| | |||
|- bgcolor="#eeeeee" | |||
| CBFS_SIZE || soc/intel/quark || hex || || | |||
Specify the size of the coreboot file system in the read-only (recovery) | |||
portion of the flash part. On Quark systems the firmware image stores | |||
more than just coreboot, including: | |||
- The chipset microcode (RMU) binary file located at 0xFFF00000 | |||
- Intel Trusted Execution Engine firmware | |||
|| | |||
|- bgcolor="#eeeeee" | |||
| ADD_FSP_RAW_BIN || soc/intel/quark || bool || Add the Intel FSP binary to the flash image without relocation || | |||
Select this option to add an Intel FSP binary to | |||
the resulting coreboot image. | |||
Note: Without this binary, coreboot builds relying on the FSP | |||
will not boot | |||
|| | |||
|- bgcolor="#eeeeee" | |||
| FSP_FILE || soc/intel/quark || string || Intel FSP binary path and filename || | |||
The path and filename of the Intel FSP binary for this platform. | |||
|| | |||
|- bgcolor="#eeeeee" | |||
| FSP_IMAGE_ID_STRING || soc/intel/quark || string || 8 byte platform string identifying the FSP platform || | |||
8 ASCII character byte signature string that will help match the FSP | |||
binary to a supported hardware configuration. | |||
|| | |||
|- bgcolor="#eeeeee" | |||
| FSP_LOC || soc/intel/quark || hex || || | |||
The location in CBFS that the FSP is located. This must match the | |||
value that is set in the FSP binary. If the FSP needs to be moved, | |||
rebase the FSP with Intel's BCT (tool). | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | FSP_ESRAM_LOC || soc/intel/quark || hex || || | ||
The | The location in ESRAM where a copy of the FSP binary is placed. | ||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| || | | RELOCATE_FSP_INTO_DRAM || soc/intel/quark || bool || Relocate FSP into DRAM || | ||
Relocate the FSP binary into DRAM before the call to SiliconInit. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | ADD_FSP_PDAT_FILE || soc/intel/quark || bool || Should the PDAT binary be added to the flash image? || | ||
The PDAT file is required for the FSP 1.1 binary | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | FSP_PDAT_FILE || soc/intel/quark || string || || | ||
The path and filename of the Intel | The path and filename of the Intel Galileo platform-data-patch (PDAT) | ||
binary. This binary file is generated by the platform-data-patch.py | |||
script released with the Quark BSP and contains the Ethernet address. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | FSP_PDAT_LOC || soc/intel/quark || hex || || | ||
The location in CBFS that the | The location in CBFS that the PDAT is located. It must match the | ||
PCD PcdPlatformDataBaseAddress of Quark SoC FSP. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |||
| ADD_RMU_FILE || soc/intel/quark || bool || Should the RMU binary be added to the flash image? || | |||
The RMU file is required to get the chip out of reset. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | RMU_FILE || soc/intel/quark || string || || | ||
The path and filename of the Intel Quark RMU binary. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | RMU_LOC || soc/intel/quark || hex || || | ||
The location in CBFS that the RMU is located. It must match the | |||
strap-determined base address. | |||
- | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SOC_INTEL_COMMON || soc/intel/common || bool || || | ||
common code for Intel SOCs | |||
|| | |||
|- bgcolor="#eeeeee" | |||
| SOC_SETS_MTRRS || soc/intel/common || bool || || | |||
The SoC needs uses different access methods for reading and writing | |||
the MTRRs. Use SoC specific routines to handle the MTRR access. | |||
|| | |||
|- bgcolor="#eeeeee" | |||
| MMA || soc/intel/common || bool || enable MMA (Memory Margin Analysis) support || | |||
Set this option to y to enable MMA (Memory Margin Analysis) support | |||
|| | || | ||
|- bgcolor="#eeeeee" | |||
| SOC_INTEL_BROADWELL || soc/intel/broadwell || bool || || | |||
Intel Broadwell and Haswell ULT support. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| DCACHE_RAM_SIZE || | | DCACHE_RAM_SIZE || soc/intel/broadwell || hex || || | ||
The size of the cache-as-ram region required during bootblock | The size of the cache-as-ram region required during bootblock | ||
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE | and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE | ||
Line 1,194: | Line 1,158: | ||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| DCACHE_RAM_MRC_VAR_SIZE || | | DCACHE_RAM_MRC_VAR_SIZE || soc/intel/broadwell || hex || || | ||
The amount of cache-as-ram region required by the reference code. | The amount of cache-as-ram region required by the reference code. | ||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| DCACHE_RAM_ROMSTAGE_STACK_SIZE || | | DCACHE_RAM_ROMSTAGE_STACK_SIZE || soc/intel/broadwell || hex || || | ||
The amount of anticipated stack usage from the data cache | The amount of anticipated stack usage from the data cache | ||
during pre-ram rom stage execution. | during pre-ram rom stage execution. | ||
Line 1,205: | Line 1,169: | ||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| HAVE_MRC || | | HAVE_MRC || soc/intel/broadwell || bool || Add a Memory Reference Code binary || | ||
Select this option to add a | Select this option to add a Memory Reference Code binary to | ||
the resulting coreboot image. | the resulting coreboot image. | ||
Line 1,213: | Line 1,177: | ||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| MRC_FILE || | | MRC_FILE || soc/intel/broadwell || string || Intel Memory Reference Code path and filename || | ||
The | The filename of the file to use as Memory Reference Code binary. | ||
binary. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| PRE_GRAPHICS_DELAY || soc/intel/broadwell || int || Graphics initialization delay in ms || | |||
| PRE_GRAPHICS_DELAY || | |||
On some systems, coreboot boots so fast that connected monitors | On some systems, coreboot boots so fast that connected monitors | ||
(mostly TVs) won't be able to wake up fast enough to talk to the | (mostly TVs) won't be able to wake up fast enough to talk to the | ||
Line 1,238: | Line 1,190: | ||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | RESET_ON_INVALID_RAMSTAGE_CACHE || soc/intel/broadwell || bool || Reset the system on S3 wake when ramstage cache invalid. || | ||
The romstage code caches the loaded ramstage program in SMM space. | |||
the | On S3 wake the romstage will copy over a fresh ramstage that was | ||
cached in the SMM space. This option determines the action to take | |||
when the ramstage cache is invalid. If selected the system will | |||
reset otherwise the ramstage will be reloaded from cbfs. | |||
|| | |||
|- bgcolor="#eeeeee" | |||
| SERIRQ_CONTINUOUS_MODE || soc/intel/broadwell || bool || || | |||
If you set this option to y, the serial IRQ machine will be | |||
operated in continuous mode. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | HAVE_REFCODE_BLOB || soc/intel/broadwell || bool || An external reference code blob should be put into cbfs. || | ||
The | The reference code blob will be placed into cbfs. | ||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | REFCODE_BLOB_FILE || soc/intel/broadwell || string || Path and filename to reference code blob. || | ||
The path and filename to the file to be added to cbfs. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SOC_INTEL_SKYLAKE || soc/intel/skylake || bool || || | ||
Intel Skylake support | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | DCACHE_RAM_SIZE || soc/intel/skylake || hex || Length in bytes of cache-as-RAM || | ||
The size of the cache-as-ram region required during bootblock | |||
and/or romstage. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | EXCLUDE_NATIVE_SD_INTERFACE || soc/intel/skylake || bool || || | ||
If you set this option to n, will not use native SD controller. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | MONOTONIC_TIMER_MSR || soc/intel/skylake || hex || || | ||
Provide a monotonic timer using the 24MHz MSR counter. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | PRE_GRAPHICS_DELAY || soc/intel/skylake || int || Graphics initialization delay in ms || | ||
On some systems, coreboot boots so fast that connected monitors | |||
(mostly TVs) won't be able to wake up fast enough to talk to the | |||
VBIOS. On those systems we need to wait for a bit before executing | |||
the VBIOS. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SERIRQ_CONTINUOUS_MODE || soc/intel/skylake || bool || || | ||
If you set this option to y, the serial IRQ machine will be | |||
operated in continuous mode. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | NHLT_DMIC_2CH || soc/intel/skylake || bool || || | ||
Include DSP firmware settings for 2 channel DMIC array. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | NHLT_DMIC_4CH || soc/intel/skylake || bool || || | ||
Include DSP firmware settings for 4 channel DMIC array. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | NHLT_NAU88L25 || soc/intel/skylake || bool || || | ||
Include DSP firmware settings for nau88l25 headset codec. | |||
|| | |||
|- bgcolor="#eeeeee" | |||
| NHLT_MAX98357 || soc/intel/skylake || bool || || | |||
Include DSP firmware settings for max98357 amplifier. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | NHLT_SSM4567 || soc/intel/skylake || bool || || | ||
Include DSP firmware settings for ssm4567 smart amplifier. | |||
|| | |||
|- bgcolor="#eeeeee" | |||
| SKIP_FSP_CAR || soc/intel/skylake || bool || Skip cache as RAM setup in FSP || | |||
Skip Cache as RAM setup in FSP. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE || soc/broadcom/cygnus || bool || Enable DDR auto self-refresh || | ||
Warning: M0 expects that auto self-refresh is enabled. Modify | |||
with caution. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | DEBUG_DRAM || soc/mediatek/mt8173 || bool || Output verbose DRAM related debug message || | ||
This option enables additional DRAM related debug messages. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | DEBUG_I2C || soc/mediatek/mt8173 || bool || Output verbose I2C related debug message || | ||
This option enables I2C related debug message. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | DEBUG_PMIC || soc/mediatek/mt8173 || bool || Output verbose PMIC related debug message || | ||
This option enables PMIC related debug message. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | DEBUG_PMIC_WRAP || soc/mediatek/mt8173 || bool || Output verbose PMIC WRAP related debug message || | ||
This option | This option enables PMIC WRAP related debug message. | ||
|| | |||
|- bgcolor="#eeeeee" | |||
| BOOTBLOCK_CPU_INIT || soc/marvell/armada38x || string || || | |||
CPU/SoC-specific bootblock code. This is useful if the | |||
bootblock must load microcode or copy data from ROM before | |||
searching for the bootblock. | |||
This is | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SBL_BLOB || soc/qualcomm/ipq806x || string || file name of the Qualcomm SBL blob || | ||
The path and filename of the binary blob containing | |||
ipq806x early initialization code, as supplied by the | |||
vendor. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| || || (comment) || || | | || || (comment) || || CPU || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | RESET_ON_INVALID_RAMSTAGE_CACHE || cpu/intel/haswell || bool || Reset the system on S3 wake when ramstage cache invalid. || | ||
The haswell romstage code caches the loaded ramstage program | |||
the | in SMM space. On S3 wake the romstage will copy over a fresh | ||
ramstage that was cached in the SMM space. This option determines | |||
the action to take when the ramstage cache is invalid. If selected | |||
the system will reset otherwise the ramstage will be reloaded from | |||
cbfs. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CPU_INTEL_FIRMWARE_INTERFACE_TABLE || cpu/intel/fit || None || || | ||
This option selects building a Firmware Interface Table (FIT). | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CPU_INTEL_NUM_FIT_ENTRIES || cpu/intel/fit || int || || | ||
This option selects the number of empty entries in the FIT table. | |||
|| | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED || cpu/intel/turbo || None || || | ||
This option indicates that the turbo mode setting is not package | |||
scoped. i.e. enable_turbo() needs to be called on not just the bsp | |||
to | |||
|| | |||
|| | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | GEODE_VSA_FILE || cpu/amd/geode_gx2 || bool || Add a VSA image || | ||
Select this option if you have an AMD Geode GX2 vsa that you would | |||
Select this if you | like to add to your ROM. | ||
and | |||
You will be able to specify the location and file name of the | |||
image later. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | VSA_FILENAME || cpu/amd/geode_gx2 || string || AMD Geode GX2 VSA path and filename || | ||
The | The path and filename of the file to use as VSA. | ||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | GEODE_VSA_FILE || cpu/amd/geode_lx || bool || Add a VSA image || | ||
Select this option if you have an AMD Geode LX vsa that you would | |||
like to add to your ROM. | |||
You will be able to specify the location and file name of the | |||
image later. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | VSA_FILENAME || cpu/amd/geode_lx || string || AMD Geode LX VSA path and filename || | ||
The path and filename of the file to use as VSA. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | XIP_ROM_SIZE || cpu/amd/agesa || hex || || | ||
Overwride the default write through caching size as 1M Bytes. | |||
On some AMD platforms, one socket supports 2 or more kinds of | |||
processor family, compiling several CPU families agesa code | |||
will increase the romstage size. | |||
In order to execute romstage in place on the flash ROM, | |||
more space is required to be set as write through caching. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL || cpu/amd/agesa/family10 || bool || Redirect AGESA IDS_HDT_CONSOLE to serial console || | ||
This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. | |||
Warning: Only enable this option when debuging or tracing AMD AGESA code. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CPU_AMD_SOCKET_G34 || cpu/amd/agesa/family15 || bool || || | ||
AMD G34 Socket | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CPU_AMD_SOCKET_C32 || cpu/amd/agesa/family15 || bool || || | ||
AMD C32 Socket | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CPU_AMD_SOCKET_AM3R2 || cpu/amd/agesa/family15 || bool || || | ||
AMD AM3r2 Socket | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL || cpu/amd/agesa/family15 || bool || Redirect AGESA IDS_HDT_CONSOLE to serial console || | ||
This Option allows you to redirect the AMD AGESA IDS_HDT_CONSOLE debug information to the serial console. | |||
to the | |||
Warning: Only enable this option when debuging or tracing AMD AGESA code. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | FORCE_AM1_SOCKET_SUPPORT || cpu/amd/agesa/family16kb || bool || || | ||
Force AGESA to ignore package type mismatch between CPU and northbridge | |||
in memory code. This enables Socket AM1 support with current AGESA | |||
version for Kabini platform. | |||
Enable this option only if you have Socket AM1 board. | |||
Note that the AGESA release shipped with coreboot does not officially | |||
support the AM1 socket. Selecting this option might damage your hardware. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | XIP_ROM_SIZE || cpu/amd/pi || hex || || | ||
Overwride the default write through caching size as 1M Bytes. | |||
On some AMD platforms, one socket supports 2 or more kinds of | |||
processor family, compiling several CPU families agesa code | |||
will increase the romstage size. | |||
In order to execute romstage in place on the flash ROM, | |||
more space is required to be set as write through caching. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | LAPIC_MONOTONIC_TIMER || cpu/x86 || bool || || | ||
Expose monotonic time using the local apic. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | TSC_CONSTANT_RATE || cpu/x86 || bool || || | ||
This option asserts that the TSC ticks at a known constant rate. | |||
Therefore, no TSC calibration is required. | |||
|| | |||
|- bgcolor="#eeeeee" | |||
| TSC_MONOTONIC_TIMER || cpu/x86 || bool || || | |||
Expose monotonic time using the TSC. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | TSC_SYNC_LFENCE || cpu/x86 || bool || || | ||
The CPU driver should select this if the CPU needs | |||
to execute an lfence instruction in order to synchronize | |||
rdtsc. This is true for all modern AMD CPUs. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | TSC_SYNC_MFENCE || cpu/x86 || bool || || | ||
The CPU driver should select this if the CPU needs | |||
to execute an mfence instruction in order to synchronize | |||
rdtsc. This is true for all modern Intel CPUs. | |||
to | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SMM_MODULE_HEAP_SIZE || cpu/x86 || hex || || | ||
This option determines the size of the heap within the SMM handler | |||
modules. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SERIALIZED_SMM_INITIALIZATION || cpu/x86 || bool || || | ||
On some CPUs, there is a race condition in SMM. | |||
This can occur when both hyperthreads change SMM state | |||
variables in parallel without coordination. | |||
Setting this option serializes the SMM initialization | |||
to avoid an ugly hang in the boot process at the cost | |||
of a slightly longer boot time. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | X86_AMD_FIXED_MTRRS || cpu/x86 || bool || || | ||
This option informs the MTRR code to use the RdMem and WrMem fields | |||
in the fixed MTRR MSRs. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | PLATFORM_USES_FSP1_0 || cpu/x86 || bool || || | ||
Selected for Intel processors/platform combinations that use the | |||
Intel Firmware Support Package (FSP) 1.0 for initialization. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | PARALLEL_MP || cpu/x86 || bool || || | ||
This option uses common MP infrastructure for bringing up APs | |||
in parallel. It additionally provides a more flexible mechanism | |||
for sequencing the steps of bringing up the APs. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | BACKUP_DEFAULT_SMM_REGION || cpu/x86 || bool || || | ||
The CPU support will select this option if the default SMM region | |||
needs to be backed up for suspend/resume purposes. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING || cpu/x86 || bool || || | ||
On certain platforms a boot speed gain can be realized if mirroring | |||
the payload data stored in non-volatile storage. On x86 systems the | |||
payload would typically live in a memory-mapped SPI part. Copying | |||
the SPI contents to RAM before performing the load can speed up | |||
the boot process. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | BOOT_MEDIA_SPI_BUS || cpu/x86 || int || || | ||
Most x86 systems which boot from SPI flash boot using bus 0. | |||
|| | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SMP || cpu || bool || || | ||
This | This option is used to enable certain functions to make coreboot | ||
work correctly on symmetric multi processor (SMP) systems. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | AP_SIPI_VECTOR || cpu || hex || || | ||
This must equal address of ap_sipi_vector from bootblock build. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | MMX || cpu || bool || || | ||
Select | Select MMX in your socket or model Kconfig if your CPU has MMX | ||
streaming SIMD instructions. ROMCC can build more efficient | |||
code if it can spill to MMX registers. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SSE || cpu || bool || || | ||
Select SSE in your socket or model Kconfig if your CPU has SSE | |||
streaming SIMD instructions. ROMCC can build more efficient | |||
code if it can spill to SSE (aka XMM) registers. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SSE2 || cpu || bool || || | ||
Select SSE2 in your socket or model Kconfig if your CPU has SSE2 | |||
streaming SIMD instructions. Some parts of coreboot can be built | |||
with more efficient code if SSE2 instructions are available. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | USES_MICROCODE_HEADER_FILES || cpu || bool || || | ||
This is selected by a board or chipset to set the default for the | |||
microcode source choice to a list of external microcode headers | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CPU_MICROCODE_CBFS_GENERATE || cpu || bool || Generate from tree || | ||
Select this option if you want microcode updates to be assembled when | |||
building coreboot and included in the final image as a separate CBFS | |||
file. Microcode will not be hard-coded into ramstage. | |||
The microcode file may be removed from the ROM image at a later | |||
time with cbfstool, if desired. | |||
The | |||
If unsure, select this option. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CPU_MICROCODE_CBFS_EXTERNAL_HEADER || cpu || bool || Include external microcode header files || | ||
Select this option if you want to include external c header files | |||
containing the CPU microcode. This will be included as a separate | |||
file in CBFS. | |||
A word of caution: only select this option if you are sure the | |||
microcode that you have is newer than the microcode shipping with | |||
coreboot. | |||
The microcode file may be removed from the ROM image at a later | |||
time with cbfstool, if desired. | |||
The | |||
If unsure, select "Generate from tree" | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CPU_MICROCODE_CBFS_NONE || cpu || bool || Do not include microcode updates || | ||
Select this option if you do not want CPU microcode included in CBFS. | |||
Note that for some CPUs, the microcode is hard-coded into the source | |||
tree and is not loaded from CBFS. In this case, microcode will still | |||
be updated. There is a push to move all microcode to CBFS, but this | |||
change is not implemented for all CPUs. | |||
This option currently applies to: | |||
- Intel SandyBridge/IvyBridge | |||
- VIA Nano | |||
Microcode may be added to the ROM image at a later time with cbfstool, | |||
if desired. | |||
If unsure, select "Generate from tree" | |||
The GOOD: | |||
Microcode updates intend to solve issues that have been discovered | |||
after CPU production. The expected effect is that systems work as | |||
intended with the updated microcode, but we have also seen cases where | |||
the | issues were solved by not applying microcode updates. | ||
The BAD: | |||
Note that some operating system include these same microcode patches, | |||
so you may need to also disable microcode updates in your operating | |||
system for this option to have an effect. | |||
The UGLY: | |||
A word of CAUTION: some CPUs depend on microcode updates to function | |||
correctly. Not updating the microcode may leave the CPU operating at | |||
less than optimal performance, or may cause outright hangups. | |||
There are CPUs where coreboot cannot properly initialize the CPU | |||
without microcode updates | |||
For example, if running with the factory microcode, some Intel | |||
SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs | |||
will hang when changing the frequency. | |||
Make sure you have a way of flashing the ROM externally before | |||
selecting this option. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CPU_MICROCODE_MULTIPLE_FILES || cpu || bool || || | ||
Select this option to install separate microcode container files into | |||
CBFS instead of using the traditional monolithic microcode file format. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CPU_MICROCODE_HEADER_FILES || cpu || string || List of space separated microcode header files with the path || | ||
A list of one or more microcode header files with path from the | |||
coreboot directory. These should be separated by spaces. | |||
|| | || | ||
|| | |||
|- bgcolor="#eeeeee" | |||
| || || (comment) || || Northbridge || | |||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | OVERRIDE_CLOCK_DISABLE || northbridge/intel/i945 || bool || || | ||
Usually system firmware turns off system memory clock | |||
signals to unused SO-DIMM slots to reduce EMI and power | |||
consumption. | |||
However, some boards do not like unused clock signals to | |||
be disabled. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | MAXIMUM_SUPPORTED_FREQUENCY || northbridge/intel/i945 || int || || | ||
If non-zero, this designates the maximum DDR frequency | |||
the board supports, despite what the chipset should be | |||
capable of. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CHECK_SLFRCS_ON_RESUME || northbridge/intel/i945 || int || || | ||
On some boards it may be neccessary to hard reset early | |||
during resume from S3 if the SLFRCS register indicates that | |||
a memory channel is not guaranteed to be in self-refresh. | |||
On other boards the check always creates a false positive, | |||
effectively making it impossible to resume. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | USE_NATIVE_RAMINIT || northbridge/intel/sandybridge || bool || Use native raminit || | ||
Select if you want to use coreboot implementation of raminit rather than | |||
System Agent/MRC.bin. You should answer Y. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | MRC_FILE || northbridge/intel/sandybridge || string || Intel System Agent path and filename || | ||
The path and filename of the file to use as System Agent | |||
binary. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | DCACHE_RAM_SIZE || northbridge/intel/haswell || hex || || | ||
The size of the cache-as-ram region required during bootblock | |||
a | and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE | ||
must add up to a power of 2. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | DCACHE_RAM_MRC_VAR_SIZE || northbridge/intel/haswell || hex || || | ||
The amount of cache-as-ram region required by the reference code. | |||
The | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| || | | DCACHE_RAM_ROMSTAGE_STACK_SIZE || northbridge/intel/haswell || hex || || | ||
The amount of anticipated stack usage from the data cache | |||
during pre-ram rom stage execution. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | HAVE_MRC || northbridge/intel/haswell || bool || Add a System Agent binary || | ||
Select this option to add a System Agent binary to | |||
the resulting coreboot image. | |||
Note: Without this binary coreboot will not work | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | MRC_FILE || northbridge/intel/haswell || string || Intel System Agent path and filename || | ||
The path and filename of the file to use as System Agent | |||
binary. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | PRE_GRAPHICS_DELAY || northbridge/intel/haswell || int || Graphics initialization delay in ms || | ||
On some systems, coreboot boots so fast that connected monitors | |||
(mostly TVs) won't be able to wake up fast enough to talk to the | |||
VBIOS. On those systems we need to wait for a bit before executing | |||
bit | the VBIOS. | ||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | VGA_BIOS_ID || northbridge/intel/fsp_sandybridge || string || || | ||
This is the default PCI ID for the sandybridge/ivybridge graphics | |||
devices. This string names the vbios ROM in cbfs. The following | |||
PCI IDs will be remapped to load this ROM: | |||
0x80860102, 0x8086010a, 0x80860112, 0x80860116 | |||
0x80860122, 0x80860126, 0x80860166 | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | FSP_FILE || northbridge/intel/fsp_sandybridge/fsp || string || || | ||
The path and filename of the Intel FSP binary for this platform. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | FSP_LOC || northbridge/intel/fsp_sandybridge/fsp || hex || Intel FSP Binary location in CBFS || | ||
The location in CBFS that the FSP is located. This must match the | |||
value that is set in the FSP binary. If the FSP needs to be moved, | |||
rebase the FSP with the Intel's BCT (tool). | |||
The Ivy Bridge Processor/Panther Point FSP is built with a preferred | |||
base address of 0xFFF80000 | |||
|| | || | ||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SDRAMPWR_4DIMM || northbridge/intel/i440bx || bool || || | ||
This option affects how the SDRAMC register is programmed. | |||
Memory clock signals will not be routed properly if this option | |||
is set wrong. | |||
If your board has 4 DIMM slots, you must use select this option, in | |||
your Kconfig file of the board. On boards with 3 DIMM slots, | |||
do _not_ select this option. | |||
|| | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SET_TSEG_1MB || northbridge/intel/fsp_rangeley || bool || 1 MB || | ||
Set the TSEG area to 1 MB. | |||
1 | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| || || | | SET_TSEG_2MB || northbridge/intel/fsp_rangeley || bool || 2 MB || | ||
Set the TSEG area to 2 MB. | |||
|| | |||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| || || | | SET_TSEG_4MB || northbridge/intel/fsp_rangeley || bool || 4 MB || | ||
Set the TSEG area to 4 MB. | |||
|| | |||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| || || | | SET_TSEG_8MB || northbridge/intel/fsp_rangeley || bool || 8 MB || | ||
Set the TSEG area to 8 MB. | |||
|| | |||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| || | | FSP_FILE || northbridge/intel/fsp_rangeley/fsp || string || || | ||
The path and filename of the Intel FSP binary for this platform. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | FSP_LOC || northbridge/intel/fsp_rangeley/fsp || hex || || | ||
The | The location in CBFS that the FSP is located. This must match the | ||
value that is set in the FSP binary. If the FSP needs to be moved, | |||
rebase the FSP with Intel's BCT (tool). | |||
The Rangeley FSP is built with a preferred base address of 0xFFF80000 | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | VGA_BIOS_ID || northbridge/amd/pi/00630F01 || string || || | ||
The default VGA BIOS PCI vendor/device ID should be set to the | |||
result of the map_oprom_vendev() function in northbridge.c. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | VGA_BIOS_ID || northbridge/amd/pi/00730F01 || string || || | ||
The default VGA BIOS PCI vendor/device ID should be set to the | |||
result of the map_oprom_vendev() function in northbridge.c. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| || || | | VGA_BIOS_ID || northbridge/amd/pi/00660F01 || string || || | ||
The default VGA BIOS PCI vendor/device ID should be set to the | |||
result of the map_oprom_vendev() function in northbridge.c. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | REDIRECT_NBCIMX_TRACE_TO_SERIAL || northbridge/amd/cimx/rd890 || bool || Redirect AMD Northbridge CIMX Trace to serial console || | ||
This Option allows you to redirect the AMD Northbridge CIMX | |||
Trace debug information to the serial console. | |||
Warning: Only enable this option when debuging or tracing AMD CIMX code. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | VGA_BIOS_ID || northbridge/amd/agesa/family16kb || string || || | ||
The default VGA BIOS PCI vendor/device ID should be set to the | |||
result of the map_oprom_vendev() function in northbridge.c. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SVI_HIGH_FREQ || northbridge/amd/amdfam10 || bool || || | ||
Select this for boards with a Voltage Regulator able to operate | |||
at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3. | |||
|| | || | ||
|| | |- bgcolor="#6699dd" | ||
! align="left" | Menu: HyperTransport setup || || || || | |||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SVI_HIGH_FREQ || northbridge/amd/amdfam10 || bool || HyperTransport downlink width || | ||
This option sets the maximum permissible HyperTransport | |||
downlink width. | |||
Use of this option will only limit the autodetected HT width. | |||
It will not (and cannot) increase the width beyond the autodetected | |||
limits. | |||
This is primarily used to work around poorly designed or laid out HT | |||
traces on certain motherboards. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | LIMIT_HT_DOWN_WIDTH_16 || northbridge/amd/amdfam10 || bool || HyperTransport uplink width || | ||
This option sets the maximum permissible HyperTransport | |||
not | uplink width. | ||
Use of this option will only limit the autodetected HT width. | |||
It will not (and cannot) increase the width beyond the autodetected | |||
limits. | |||
This is primarily used to work around poorly designed or laid out HT | |||
traces on certain motherboards. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | || || (comment) || || Southbridge || | ||
|- bgcolor="#eeeeee" | |||
| HAVE_CMC || southbridge/intel/sch || bool || Add a CMC state machine binary || | |||
Select this option to add a CMC state machine binary to | |||
the resulting coreboot image. | |||
Note: Without this binary coreboot will not work | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CMC_FILE || southbridge/intel/sch || string || Intel CMC path and filename || | ||
The path and filename of the file to use as CMC state machine | |||
binary. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SERIRQ_CONTINUOUS_MODE || southbridge/intel/ibexpeak || bool || || | ||
If you set this option to y, the serial IRQ machine will be | |||
operated in continuous mode. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | INTEL_LYNXPOINT_LP || southbridge/intel/lynxpoint || bool || || | ||
Set this option to y for Lynxpont LP (Haswell ULT). | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SERIRQ_CONTINUOUS_MODE || southbridge/intel/lynxpoint || bool || || | ||
If you set this option to y, the serial IRQ machine will be | |||
operated in continuous mode. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | ME_MBP_CLEAR_LATE || southbridge/intel/lynxpoint || bool || Defer wait for ME MBP Cleared || | ||
If you set this option to y, the Management Engine driver | |||
will defer waiting for the MBP Cleared indicator until the | |||
finalize step. This can speed up boot time if the ME takes | |||
a long time to indicate this status. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |||
| FINALIZE_USB_ROUTE_XHCI || southbridge/intel/lynxpoint || bool || Route all ports to XHCI controller in finalize step || | |||
If you set this option to y, the USB ports will be routed | |||
to the XHCI controller during the finalize SMM callback. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SERIRQ_CONTINUOUS_MODE || southbridge/intel/bd82x6x || bool || || | ||
If you set this option to y, the serial IRQ machine will be | |||
operated in continuous mode. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| || || | | LOCK_SPI_ON_RESUME_RO || southbridge/intel/bd82x6x || bool || Lock all flash ROM sections on S3 resume || | ||
If the flash ROM shall be protected against write accesses from the | |||
operating system (OS), the locking procedure has to be repeated after | |||
each resume from S3. Select this if you never want to update the flash | |||
ROM from within your OS. Notice: Even with this option, the write lock | |||
has still to be enabled on the normal boot path (e.g. by the payload). | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | LOCK_SPI_ON_RESUME_NO_ACCESS || southbridge/intel/bd82x6x || bool || Lock and disable reads all flash ROM sections on S3 resume || | ||
If the flash ROM shall be protected against all accesses from the | |||
operating system (OS), the locking procedure has to be repeated after | |||
each resume from S3. Select this if you never want to update the flash | |||
ROM from within your OS. Notice: Even with this option, the lock | |||
has still to be enabled on the normal boot path (e.g. by the payload). | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SERIRQ_CONTINUOUS_MODE || southbridge/intel/fsp_bd82x6x || bool || || | ||
If you set this option to y, the serial IRQ machine will be | |||
operated in continuous mode. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SERIRQ_CONTINUOUS_MODE || southbridge/intel/fsp_rangeley || bool || || | ||
If you set this option to y, the serial IRQ machine will be | |||
operated in continuous mode. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | IFD_BIN_PATH || southbridge/intel/fsp_rangeley || string || || | ||
The path and filename to the descriptor.bin file. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SERIRQ_CONTINUOUS_MODE || southbridge/intel/fsp_i89xx || bool || || | ||
If you set this option to y, the serial IRQ machine will be | |||
operated in continuous mode. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | HUDSON_XHCI_ENABLE || southbridge/amd/pi/hudson || bool || Enable Hudson XHCI Controller || | ||
The XHCI controller must be enabled and the XHCI firmware | |||
must be added in order to have USB 3.0 support configured | |||
by coreboot. The OS will be responsible for enabling the XHCI | |||
controller if the the XHCI firmware is available but the | |||
XHCI controller is not enabled by coreboot. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | HUDSON_XHCI_FWM || southbridge/amd/pi/hudson || bool || Add xhci firmware || | ||
Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0 | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | HUDSON_IMC_FWM || southbridge/amd/pi/hudson || bool || Add IMC firmware || | ||
Add Hudson 2/3/4 IMC Firmware to support the onboard fan control | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | HUDSON_GEC_FWM || southbridge/amd/pi/hudson || bool || || | ||
Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC. | |||
Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | HUDSON_FWM_POSITION || southbridge/amd/pi/hudson || hex || Hudson Firmware ROM Position || | ||
Hudson requires the firmware MUST be located at | |||
a specific address (ROM start address + 0x20000), otherwise | |||
xhci host Controller can not find or load the xhci firmware. | |||
The firmware start address is dependent on the ROM chip size. | |||
The default offset is 0x20000 from the ROM start address, namely | |||
0xFFF20000 if flash chip size is 1M | |||
0xFFE20000 if flash chip size is 2M | |||
0xFFC20000 if flash chip size is 4M | |||
0xFF820000 if flash chip size is 8M | |||
0xFF020000 if flash chip size is 16M | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | HUDSON_SATA_MODE || southbridge/amd/pi/hudson || int || SATA Mode || | ||
The | Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. | ||
The default is NATIVE. | |||
0: NATIVE mode does not require a ROM. | |||
1: RAID mode must have the two ROM files. | |||
2: AHCI may work with or without AHCI ROM. It depends on the payload support. | |||
For example, seabios does not require the AHCI ROM. | |||
3: LEGACY IDE | |||
4: IDE to AHCI | |||
5: AHCI7804: ROM Required, and AMD driver required in the OS. | |||
6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | || || (comment) || || NATIVE || | ||
|- bgcolor="#eeeeee" | |||
| || || (comment) || || RAID || | |||
|- bgcolor="#eeeeee" | |||
| || || (comment) || || AHCI || | |||
|- bgcolor="#eeeeee" | |||
| || || (comment) || || LEGACY IDE || | |||
|- bgcolor="#eeeeee" | |||
| || || (comment) || || IDE to AHCI || | |||
|- bgcolor="#eeeeee" | |||
| || || (comment) || || AHCI7804 || | |||
|- bgcolor="#eeeeee" | |||
| || || (comment) || || IDE to AHCI7804 || | |||
|- bgcolor="#eeeeee" | |||
| RAID_ROM_ID || southbridge/amd/pi/hudson || string || RAID device PCI IDs || | |||
1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | RAID_MISC_ROM_POSITION || southbridge/amd/pi/hudson || hex || RAID Misc ROM Position || | ||
The | The RAID ROM requires that the MISC ROM is located between the range | ||
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned. | |||
The CONFIG_ROM_SIZE must be larger than 0x100000. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | HUDSON_LEGACY_FREE || southbridge/amd/pi/hudson || bool || System is legacy free || | ||
Select y if there is no keyboard controller in the system. | |||
This sets variables in AGESA and ACPI. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | AZ_PIN || southbridge/amd/pi/hudson || hex || || | ||
bit 1,0 - pin 0 | |||
bit 3,2 - pin 1 | |||
- | bit 5,4 - pin 2 | ||
- | bit 7,6 - pin 3 | ||
- | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | HUDSON_UART || southbridge/amd/pi/hudson || bool || UART controller on Kern || | ||
The | There are two UART controllers in Kern. | ||
The UART registers are memory-mapped. UART | |||
controller 0 registers range from FEDC_6000h | |||
to FEDC_6FFFh. UART controller 1 registers | |||
range from FEDC_8000h to FEDC_8FFFh. | |||
|| | || | ||
|| | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SATA_CONTROLLER_MODE || southbridge/amd/cimx/sb700 || hex || || | ||
0x0 = Native IDE mode. | |||
0x1 = RAID mode. | |||
0x2 = AHCI mode. | |||
0x3 = Legacy IDE mode. | |||
0x4 = IDE->AHCI mode. | |||
0x5 = AHCI mode as 7804 ID (AMD driver). | |||
0x6 = IDE->AHCI mode as 7804 ID (AMD driver). | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | PCIB_ENABLE || southbridge/amd/cimx/sb700 || bool || || | ||
n = Disable PCI Bridge Device 14 Function 4. | |||
y = Enable PCI Bridge Device 14 Function 4. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | ACPI_SCI_IRQ || southbridge/amd/cimx/sb700 || hex || || | ||
Set SCI IRQ to 9. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | REDIRECT_SBCIMX_TRACE_TO_SERIAL || southbridge/amd/cimx/sb700 || bool || Redirect AMD Southbridge CIMX Trace to serial console || | ||
This Option allows you to redirect the AMD Southbridge CIMX Trace | |||
debug information to the serial console. | |||
Warning: Only enable this option when debuging or tracing AMD CIMX code. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | ENABLE_IDE_COMBINED_MODE || southbridge/amd/cimx/sb800 || bool || Enable SATA IDE combined mode || | ||
If Combined Mode is enabled. IDE controller is exposed and | |||
SATA controller has control over Port0 through Port3, | |||
IDE controller has control over Port4 and Port5. | |||
If Combined Mode is disabled, IDE controller is hidden and | |||
SATA controller has full control of all 6 Ports when operating in non-IDE mode. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | IDE_COMBINED_MODE || southbridge/amd/cimx/sb800 || hex || SATA Mode || | ||
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. | |||
The default is AHCI. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SB800_SATA_IDE || southbridge/amd/cimx/sb800 || bool || NATIVE || | ||
NATIVE does not require a ROM. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SB800_SATA_AHCI || southbridge/amd/cimx/sb800 || bool || AHCI || | ||
AHCI is the default and may work with or without AHCI ROM. It depends on the payload support. | |||
For example, seabios does not require the AHCI ROM. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SB800_SATA_RAID || southbridge/amd/cimx/sb800 || bool || RAID || | ||
sb800 RAID mode must have the two required ROM files. | |||
the | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | RAID_ROM_ID || southbridge/amd/cimx/sb800 || string || RAID device PCI IDs || | ||
1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | RAID_MISC_ROM_POSITION || southbridge/amd/cimx/sb800 || hex || RAID Misc ROM Position || | ||
The | The RAID ROM requires that the MISC ROM is located between the range | ||
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned. | |||
The CONFIG_ROM_SIZE must larger than 0x100000. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SB800_IMC_FWM || southbridge/amd/cimx/sb800 || bool || Add IMC firmware || | ||
Add SB800 / Hudson 1 IMC Firmware to support the onboard fan control. | |||
the | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SB800_FWM_AT_FFFA0000 || southbridge/amd/cimx/sb800 || bool || 0xFFFA0000 || | ||
The | The IMC and GEC ROMs requires a 'signature' located at one of several | ||
fixed locations in memory. The location used shouldn't matter, just | |||
select an area that doesn't conflict with anything else. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SB800_FWM_AT_FFF20000 || southbridge/amd/cimx/sb800 || bool || 0xFFF20000 || | ||
The IMC and GEC ROMs requires a 'signature' located at one of several | |||
fixed locations in memory. The location used shouldn't matter, just | |||
select an area that doesn't conflict with anything else. | |||
The | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SB800_FWM_AT_FFE20000 || southbridge/amd/cimx/sb800 || bool || 0xFFE20000 || | ||
The IMC and GEC ROMs requires a 'signature' located at one of several | |||
fixed locations in memory. The location used shouldn't matter, just | |||
select an area that doesn't conflict with anything else. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SB800_FWM_AT_FFC20000 || southbridge/amd/cimx/sb800 || bool || 0xFFC20000 || | ||
The | The IMC and GEC ROMs requires a 'signature' located at one of several | ||
fixed locations in memory. The location used shouldn't matter, just | |||
select an area that doesn't conflict with anything else. | |||
that | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SB800_FWM_AT_FF820000 || southbridge/amd/cimx/sb800 || bool || 0xFF820000 || | ||
The IMC and GEC ROMs requires a 'signature' located at one of several | |||
fixed locations in memory. The location used shouldn't matter, just | |||
select an area that doesn't conflict with anything else. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | EHCI_BAR || southbridge/amd/cimx/sb800 || hex || Fan Control || | ||
Select the method of SB800 fan control to be used. None would be | |||
for either fixed maximum speed fans connected to the SB800 or for | |||
an external chip controlling the fan speeds. Manual control sets | |||
up the SB800 fan control registers. IMC fan control uses the SB800 | |||
IMC to actively control the fan speeds. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SB800_NO_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || None || | ||
No SB800 Fan control - Do not set up the SB800 fan control registers. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SB800_MANUAL_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || Manual || | ||
Configure the SB800 fan control registers in devicetree.cb. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SB800_IMC_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || IMC Based || | ||
Set up the SB800 to use the IMC based Fan controller. This requires | |||
the IMC rom from AMD. Configure the registers in devicetree.cb. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | SATA_CONTROLLER_MODE || southbridge/amd/cimx/sb900 || hex || || | ||
0x0 = Native IDE mode. | |||
0x1 = RAID mode. | |||
0x2 = AHCI mode. | |||
0x3 = Legacy IDE mode. | |||
0x4 = IDE->AHCI mode. | |||
0x5 = AHCI mode as 7804 ID (AMD driver). | |||
0x6 = IDE->AHCI mode as 7804 ID (AMD driver). | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | PCIB_ENABLE || southbridge/amd/cimx/sb900 || bool || || | ||
n = Disable PCI Bridge Device 14 Function 4. | |||
y = Enable PCI Bridge Device 14 Function 4. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | ACPI_SCI_IRQ || southbridge/amd/cimx/sb900 || hex || || | ||
Set SCI IRQ to 9. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | EXT_CONF_SUPPORT || southbridge/amd/sr5650 || bool || Enable PCI-E MMCONFIG support || | ||
Select to enable PCI-E MMCONFIG support on the SR5650. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | EXT_CONF_SUPPORT || southbridge/amd/rs690 || bool || || | ||
Select if RS690 should be setup to support MMCONF. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | HUDSON_XHCI_ENABLE || southbridge/amd/agesa/hudson || bool || Enable Hudson XHCI Controller || | ||
The XHCI controller must be enabled and the XHCI firmware | |||
coreboot | must be added in order to have USB 3.0 support configured | ||
is | by coreboot. The OS will be responsible for enabling the XHCI | ||
controller if the the XHCI firmware is available but the | |||
XHCI controller is not enabled by coreboot. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | HUDSON_XHCI_FWM || southbridge/amd/agesa/hudson || bool || Add xhci firmware || | ||
Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0 | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| || || | | HUDSON_IMC_FWM || southbridge/amd/agesa/hudson || bool || Add imc firmware || | ||
Add Hudson 2/3/4 IMC Firmware to support the onboard fan control | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | HUDSON_GEC_FWM || southbridge/amd/agesa/hudson || bool || || | ||
Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC. | |||
Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | HUDSON_FWM_POSITION || southbridge/amd/agesa/hudson || hex || Hudson Firmware ROM Position || | ||
Hudson requires the firmware MUST be located at | |||
a specific address (ROM start address + 0x20000), otherwise | |||
xhci host Controller can not find or load the xhci firmware. | |||
The firmware start address is dependent on the ROM chip size. | |||
The default offset is 0x20000 from the ROM start address, namely | |||
0xFFF20000 if flash chip size is 1M | |||
0xFFE20000 if flash chip size is 2M | |||
0xFFC20000 if flash chip size is 4M | |||
0xFF820000 if flash chip size is 8M | |||
0xFF020000 if flash chip size is 16M | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | HUDSON_SATA_MODE || southbridge/amd/agesa/hudson || int || SATA Mode || | ||
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. | |||
The default is NATIVE. | |||
and | 0: NATIVE mode does not require a ROM. | ||
1: RAID mode must have the two ROM files. | |||
2: AHCI may work with or without AHCI ROM. It depends on the payload support. | |||
For example, seabios does not require the AHCI ROM. | |||
3: LEGACY IDE | |||
4: IDE to AHCI | |||
5: AHCI7804: ROM Required, and AMD driver required in the OS. | |||
6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | || || (comment) || || NATIVE || | ||
|- bgcolor="#eeeeee" | |||
| || || (comment) || || RAID || | |||
|| | |||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | || || (comment) || || AHCI || | ||
|| | |||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | || || (comment) || || LEGACY IDE || | ||
|| | |||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | || || (comment) || || IDE to AHCI || | ||
|| | |||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | || || (comment) || || AHCI7804 || | ||
|- bgcolor="#eeeeee" | |||
| || || (comment) || || IDE to AHCI7804 || | |||
|| | |||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | RAID_ROM_ID || southbridge/amd/agesa/hudson || string || RAID device PCI IDs || | ||
1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | RAID_MISC_ROM_POSITION || southbridge/amd/agesa/hudson || hex || RAID Misc ROM Position || | ||
The RAID ROM requires that the MISC ROM is located between the range | |||
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned. | |||
The CONFIG_ROM_SIZE must be larger than 0x100000. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | HUDSON_LEGACY_FREE || southbridge/amd/agesa/hudson || bool || System is legacy free || | ||
Select y if there is no keyboard controller in the system. | |||
This sets variables in AGESA and ACPI. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | AZ_PIN || southbridge/amd/agesa/hudson || hex || || | ||
bit 1,0 - pin 0 | |||
bit 3,2 - pin 1 | |||
bit 5,4 - pin 2 | |||
bit 7,6 - pin 3 | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | EHCI_BAR || southbridge/amd/sb600 || hex || SATA Mode || | ||
Select the mode in which SATA should be driven. IDE or AHCI. | |||
The default is IDE. | |||
config SATA_MODE_IDE | |||
bool "IDE" | |||
config SATA_MODE_AHCI | |||
bool "AHCI" | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | || || (comment) || || Super I/O || | ||
|- bgcolor="#eeeeee" | |||
| || || (comment) || || Embedded Controllers || | |||
|- bgcolor="#eeeeee" | |||
| EC_ACPI || ec/acpi || bool || || | |||
ACPI Embedded Controller interface. Mostly found in laptops. | |||
|| | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | EC_GOOGLE_CHROMEEC || ec/google/chromeec || bool || || | ||
Google's Chrome EC | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | EC_GOOGLE_CHROMEEC_ACPI_MEMMAP || ec/google/chromeec || bool || || | ||
When defined, ACPI accesses EC memmap data on ports 66h/62h. When | |||
the | not defined, the memmap data is instead accessed on 900h-9ffh via | ||
the LPC bus. | |||
|| | |||
|- bgcolor="#eeeeee" | |||
| EC_GOOGLE_CHROMEEC_I2C || ec/google/chromeec || bool || || | |||
Google's Chrome EC via I2C bus. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | EC_GOOGLE_CHROMEEC_I2C_PROTO3 || ec/google/chromeec || bool || || | ||
Use only proto3 for i2c EC communication. | |||
|| | |||
|- bgcolor="#eeeeee" | |||
| EC_GOOGLE_CHROMEEC_LPC || ec/google/chromeec || bool || || | |||
Google Chrome EC via LPC bus. | |||
|| | |||
|- bgcolor="#eeeeee" | |||
| EC_GOOGLE_CHROMEEC_MEC || ec/google/chromeec || bool || || | |||
Microchip EC variant for LPC register access. | |||
|| | |||
|- bgcolor="#eeeeee" | |||
| EC_GOOGLE_CHROMEEC_PD || ec/google/chromeec || bool || || | |||
Indicates that Google's Chrome USB PD chip is present. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | EC_GOOGLE_CHROMEEC_SPI || ec/google/chromeec || bool || || | ||
Google's Chrome EC via SPI bus. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US || ec/google/chromeec || int || || | ||
Force delay after asserting /CS to allow EC to wakeup. | |||
|| | |||
|- bgcolor="#eeeeee" | |||
| EC_EXTERNAL_FIRMWARE || ec/google/chromeec || hex || || | |||
Disable building EC firmware if it's already built externally (and | |||
added manually.) | |||
|| | |||
|- bgcolor="#eeeeee" | |||
| EC_GOOGLE_CHROMEEC_BOARDNAME || ec/google/chromeec || string || Chrome EC board name for EC || | |||
The board name used in the Chrome EC code base to build | |||
the EC firmware. If set, the coreboot build with also | |||
build the EC firmware and add it to the image. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | EC_GOOGLE_CHROMEEC_PD_BOARDNAME || ec/google/chromeec || string || Chrome EC board name for PD || | ||
The board name used in the Chrome EC code base to build | |||
the PD firmware. If set, the coreboot build with also | |||
build the EC firmware and add it to the image. | |||
|| | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | EC_QUANTA_IT8518 || ec/quanta/it8518 || bool || || | ||
Interface to QUANTA IT8518 Embedded Controller. | |||
|| | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | EC_QUANTA_ENE_KB3940Q || ec/quanta/ene_kb3940q || bool || || | ||
Interface to QUANTA ENE KB3940Q Embedded Controller. | |||
|| | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | EC_SMSC_MEC1308 || ec/smsc/mec1308 || bool || || | ||
Shared memory mailbox interface to SMSC MEC1308 Embedded Controller. | |||
|| | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | EC_PURISM_LIBREM || ec/purism/librem || bool || || | ||
Purism Librem EC | |||
|| | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | EC_COMPAL_ENE932 || ec/compal/ene932 || bool || || | ||
Interface to COMPAL ENE932 Embedded Controller. | |||
|| | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | EC_KONTRON_IT8516E || ec/kontron/it8516e || bool || || | ||
Kontron uses an ITE IT8516E on the KTQM77. Its firmware might | |||
come from Fintek (mentioned as Finte*c* somewhere in their Linux | |||
driver). | |||
The KTQM77 is an embedded board and the IT8516E seems to be | |||
only used for fan control and GPIO. | |||
|| | || | ||
|| | |||
|- bgcolor="#eeeeee" | |||
| || || (comment) || || Intel FSP || | |||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | HAVE_FSP_BIN || drivers/intel/fsp1_0 || bool || Use Intel Firmware Support Package || | ||
Select this option to add an Intel FSP binary to | |||
the resulting coreboot image. | |||
Note: Without this binary, coreboot builds relying on the FSP | |||
will not boot | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | FSP_FILE || drivers/intel/fsp1_0 || string || Intel FSP binary path and filename || | ||
The path and filename of the Intel FSP binary for this platform. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | FSP_LOC || drivers/intel/fsp1_0 || hex || Intel FSP Binary location in CBFS || | ||
This | The location in CBFS that the FSP is located. This must match the | ||
value that is set in the FSP binary. If the FSP needs to be moved, | |||
rebase the FSP with Intel's BCT (tool). | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | ENABLE_FSP_FAST_BOOT || drivers/intel/fsp1_0 || bool || Enable Fast Boot || | ||
Enabling this feature will force the MRC data to be cached in NV | |||
storage to be used for speeding up boot time on future reboots | |||
and/or power cycles. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | ENABLE_MRC_CACHE || drivers/intel/fsp1_0 || bool || || | ||
Enabling this feature will cause MRC data to be cached in NV storage. | |||
This can either be used for fast boot, or just because the FSP wants | |||
it to be saved. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | MRC_CACHE_FMAP || drivers/intel/fsp1_0 || bool || Use MRC Cache in FMAP || | ||
Use the region "RW_MRC_CACHE" in FMAP instead of "mrc.cache" in CBFS. | |||
You must define a region in your FMAP named "RW_MRC_CACHE". | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | MRC_CACHE_SIZE || drivers/intel/fsp1_0 || hex || Fast Boot Data Cache Size || | ||
This is the amount of space in NV storage that is reserved for the | |||
fast boot data cache storage. | |||
WARNING: Because this area will be erased and re-written, the size | |||
should be a full sector of the flash ROM chip and nothing else should | |||
be included in CBFS in any sector that the fast boot cache data is in. | |||
|| | |||
|- bgcolor="#eeeeee" | |||
| VIRTUAL_ROM_SIZE || drivers/intel/fsp1_0 || hex || Virtual ROM Size || | |||
This is used to calculate the offset of the MRC data cache in NV | |||
Storage for fast boot. If in doubt, leave this set to the default | |||
which sets the virtual size equal to the ROM size. | |||
Example: Cougar Canyon 2 has two 8 MB SPI ROMs. When the SPI ROMs are | |||
loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB. When | |||
the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM | |||
size is 16 MB. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CACHE_ROM_SIZE_OVERRIDE || drivers/intel/fsp1_0 || hex || Cache ROM Size || | ||
This is the size of the cachable area that is passed into the FSP in | |||
the early initialization. Typically this should be the size of the CBFS | |||
area, but the size must be a power of 2 whereas the CBFS size does not | |||
have this limitation. | |||
|| | |||
|- bgcolor="#eeeeee" | |||
| USE_GENERIC_FSP_CAR_INC || drivers/intel/fsp1_0 || bool || || | |||
The chipset can select this to use a generic cache_as_ram.inc file | |||
that should be good for all FSP based platforms. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | FSP_USES_UPD || drivers/intel/fsp1_0 || bool || || | ||
If this FSP uses UPD/VPD data regions, select this in the chipset Kconfig. | |||
|| | |||
|- bgcolor="#eeeeee" | |||
| HAVE_INTEL_FIRMWARE || southbridge/intel/common/firmware || bool || || | |||
Chipset uses the Intel Firmware Descriptor to describe the | |||
layout of the SPI ROM chip. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | || || (comment) || || Intel Firmware || | ||
|- bgcolor="#eeeeee" | |||
| HAVE_IFD_BIN || southbridge/intel/common/firmware || bool || Add Intel descriptor.bin file || | |||
The descriptor binary | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | EM100 || southbridge/intel/common/firmware || bool || Configure IFD for EM100 usage || | ||
Set SPI frequency to 20MHz and disable Dual Output Fast Read Support | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | HAVE_ME_BIN || southbridge/intel/common/firmware || bool || Add Intel ME/TXE firmware || | ||
The | The Intel processor in the selected system requires a special firmware | ||
your | for an integrated controller. This might be called the Management | ||
Engine (ME), the Trusted Execution Engine (TXE) or something else | |||
depending on the chip. This firmware might or might not be available | |||
in coreboot's 3rdparty/blobs repository. If it is not and if you don't | |||
have access to the firmware from elsewhere, you can still build | |||
coreboot without it. In this case however, you'll have to make sure | |||
that you don't overwrite your ME/TXE firmware on your flash ROM. | |||
|| | |||
|- bgcolor="#eeeeee" | |||
| HAVE_GBE_BIN || southbridge/intel/common/firmware || bool || Add gigabit ethernet firmware || | |||
The integrated gigabit ethernet controller needs a firmware file. | |||
Select this if you are going to use the PCH integrated controller | |||
and have the firmware. | |||
|| | |||
|- bgcolor="#eeeeee" | |||
| BUILD_WITH_FAKE_IFD || southbridge/intel/common/firmware || bool || Build with a fake IFD || | |||
If you don't have an Intel Firmware Descriptor (descriptor.bin) for your | |||
board, you can select this option and coreboot will build without it. | |||
The resulting coreboot.rom will not contain all parts required | |||
to get coreboot running on your board. You can however write only the | |||
BIOS section to your board's flash ROM and keep the other sections | |||
untouched. Unfortunately the current version of flashrom doesn't | |||
support this yet. But there is a patch pending [1]. | |||
WARNING: Never write a complete coreboot.rom to your flash ROM if it | |||
was built with a fake IFD. It just won't work. | |||
[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | IFD_BIOS_SECTION || southbridge/intel/common/firmware || string || BIOS Region Starting:Ending addresses within the ROM || | ||
The BIOS region is typically the size of the CBFS area, and is located | |||
at the end of the ROM space. | |||
For an 8MB ROM with a 3MB CBFS area, this would look like: | |||
0x00500000:0x007fffff | |||
|| | || | ||
|- bgcolor="#eeeeee" | |||
| IFD_ME_SECTION || southbridge/intel/common/firmware || string || ME/TXE Region Starting:Ending addresses within the ROM || | |||
The ME/TXE region typically starts at around 0x1000 and often fills the | |||
ROM space not used by CBFS. | |||
For an 8MB ROM with a 3MB CBFS area, this might look like: | |||
0x00001000:0x004fffff | |||
|| | |||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | IFD_GBE_SECTION || southbridge/intel/common/firmware || string || GBE Region Starting:Ending addresses within the ROM || | ||
The Gigabit Ethernet ROM region is used when an Intel NIC is built into | |||
the Southbridge/SOC and the platform uses this device instead of an external | |||
PCIe NIC. It will be located between the ME/TXE and the BIOS region. | |||
Leave this empty if you're unsure. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | IFD_PLATFORM_SECTION || southbridge/intel/common/firmware || string || Platform Region Starting:Ending addresses within the Rom || | ||
The Platform region is used for platform specific data. | |||
It will be located between the ME/TXE and the BIOS region. | |||
Leave this empty if you're unsure. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | LOCK_MANAGEMENT_ENGINE || southbridge/intel/common/firmware || bool || Lock ME/TXE section || | ||
The Intel Firmware Descriptor supports preventing write accesses | |||
from the host to the ME or TXE section in the firmware | |||
descriptor. If the section is locked, it can only be overwritten | |||
with an external SPI flash programmer. You will want this if you | |||
want to increase security of your ROM image once you are sure | |||
that the ME/TXE firmware is no longer going to change. | |||
If unsure, say N. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CBFS_SIZE || southbridge/intel/common/firmware || hex || || | ||
Reduce CBFS size to give room to the IFD blobs. | |||
|| | || | ||
|- bgcolor="#6699dd" | |- bgcolor="#6699dd" | ||
! align="left" | Menu: | ! align="left" | Menu: AMD Platform Initialization || || || || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | None || vendorcode/amd || None || AGESA source || | ||
Select | Select the method for including the AMD Platform Initialization | ||
code into coreboot. Platform Initialization code is required for | |||
all AMD processors. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CPU_AMD_AGESA_BINARY_PI || vendorcode/amd || bool || binary PI || | ||
Use a binary PI package. Generally, these will be stored in the | |||
"3rdparty/blobs" directory. For some processors, these must be obtained | |||
directly from AMD Embedded Processors Group | |||
(http://www.amdcom/embedded). | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CPU_AMD_AGESA_OPENSOURCE || vendorcode/amd || bool || open-source AGESA || | ||
Build the PI package ("AGESA") from source code in the "vendorcode" | |||
directory. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | AGESA_BINARY_PI_VENDORCODE_PATH || vendorcode/amd/pi || string || AGESA PI directory path || | ||
Specify where to find the AGESA header files | |||
for AMD platform initialization. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | AGESA_BINARY_PI_FILE || vendorcode/amd/pi || string || AGESA PI binary file name || | ||
Specify the binary file to use for AMD platform initialization. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | AGESA_BINARY_PI_LOCATION || vendorcode/amd/pi || string || AGESA PI binary address in ROM || | ||
Specify the ROM address at which to store the binary Platform | |||
Initialization code. | |||
|| | || | ||
|- bgcolor="#6699dd" | |||
! align="left" | Menu: ChromeOS || || || || | |||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CHROMEOS || vendorcode/google/chromeos || bool || Build for ChromeOS || | ||
Enable ChromeOS specific features like the GPIO sub table in | |||
the coreboot table. NOTE: Enabling this option on an unsupported | |||
board will most likely break your build. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | VBNV_OFFSET || vendorcode/google/chromeos || hex || || | ||
CMOS offset for VbNv data. This value must match cmos.layout | |||
in the mainboard directory, minus 14 bytes for the RTC. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CHROMEOS_VBNV_CMOS || vendorcode/google/chromeos || bool || Vboot non-volatile storage in CMOS. || | ||
VBNV is stored in CMOS | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CHROMEOS_VBNV_CMOS_BACKUP_TO_FLASH || vendorcode/google/chromeos || bool || Back up Vboot non-volatile storage from CMOS to flash. || | ||
Vboot non-volatile storage data will be backed up from CMOS to flash | |||
and restored from flash if the CMOS is invalid due to power loss. | |||
|| | || | ||
|- bgcolor="#eeeeee" | |- bgcolor="#eeeeee" | ||
| | | CHROMEOS_VBNV_EC || vendorcode/google/chromeos || bool || Vboot non-volatile storage in EC. || | ||
VBNV is stored in |