Difference between revisions of "Cpu:allwinner/a10"

From coreboot
Jump to navigation Jump to search
(Created page with "This is meant as a quick might-need-to-know page for Allwinner A10 (and potentially A13 and later) SoCs == Clock structure ==")
 
 
(2 intermediate revisions by the same user not shown)
Line 2: Line 2:


== Clock structure ==
== Clock structure ==
  ___________              ___________              ___________                ____________
|          |  AXI Div  |          |  AHB Div  |          |  APB0 Div  |            |
| CPU clock |------------>| AXI clock |------------>| AHB clock |------------->| APB0 clock |
|          |  1,2,3,4  | 350M max  |  1,2,4,8  | 250M max  |  2,2,4,8    |  150M max  |
|___________|            |___________|            |___________|              |____________|
=== Notes ===
* APB1 clock is sourced independently, unlike APB0, which is derived from AHB clock

Latest revision as of 02:09, 11 January 2014

This is meant as a quick might-need-to-know page for Allwinner A10 (and potentially A13 and later) SoCs

Clock structure

 ___________               ___________               ___________                ____________
|           |   AXI Div   |           |   AHB Div   |           |   APB0 Div   |            |
| CPU clock |------------>| AXI clock |------------>| AHB clock |------------->| APB0 clock |
|           |   1,2,3,4   | 350M max  |   1,2,4,8   | 250M max  |   2,2,4,8    |  150M max  |
|___________|             |___________|             |___________|              |____________|

Notes

  • APB1 clock is sourced independently, unlike APB0, which is derived from AHB clock