Cpu:allwinner/a10
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The wiki is being retired!
Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!
This is meant as a quick might-need-to-know page for Allwinner A10 (and potentially A13 and later) SoCs
Clock structure
___________ ___________ ___________ ____________ | | AXI Div | | AHB Div | | APB0 Div | | | CPU clock |------------>| AXI clock |------------>| AHB clock |------------->| APB0 clock | | | 1,2,3,4 | 350M max | 1,2,4,8 | 250M max | 2,2,4,8 | 150M max | |___________| |___________| |___________| |____________|
Notes
- APB1 clock is sourced independently, unlike APB0, which is derived from AHB clock