Creating A devicetree.cb

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Revision as of 10:42, 18 February 2014 by Eocallaghan (talk | contribs) (Keywords)
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The wiki is being retired!

Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!

This article should help people who are writting a devicetree.cb for their system.

What you will need

  • lspci -nvvv output

Introduction

The mainboard's devicetree.cb file contains many build and platform configuration settings. One of the most important items is the mainboard device list.

A device needs to be listed in the mainboard devicetree.cb if it requires more setup than standard PCI initialization (resource allocation). Typically, that includes the CPU, northbridge, southbridge, and Super I/O. These devices are usually required for system specific configuration as well as indicate the system bus structure (pci_domain).

When a device in devicetree.cb is found during the coreboot PCI/system scan process the functions to do customized initialization are called via the device_operations and the chip_operations structures. You will find these structures in the devices source files.

Keywords

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pci, chip, device, register, on, off, end, io, irq, drq

Syntax

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Grammar

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Examples

NorthBridge

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Super I/O

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This file is licensed under Creative Commons Attribution 2.5 License.
In short: you are free to distribute and modify the file as long as you attribute its author(s) or licensor(s).