Developer Manual/RAM init
The wiki is being retired!
Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!
One of the most important tasks of coreboot is to initialize your system RAM.
This initialization depends on the type of RAM in your motherboard. To detect the type of RAM the SPD (Serial Presence Detect) must be read for each DIMM. This reading is done using I2C communication using one of the [I2C] buses on the motherboard. The exact method of reading depends on the motherboard.
There are a number of steps you have to perform to properly initialize SDRAM. This depends on the chipset, as well as the DIMMs which are inserted into the mainboard (and their properties, such as CAS latencies, and so on).
Sample northbridge datasheets:
Sample SDRAM datasheets:
- JEDEC DDR SPD Standard (PDF)
- Understanding DDR Serial Presence Detect (SPD) Table
- Micron DDR400 Datasheet
Note: Micron lists SPD values for all the memory they produce. This really helps when trying to trouble shoot memory and SPD values. Micron SPD Lookup.