Difference between revisions of "EHCI Debug Port"

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(Made explicit section for controllers lacking debug port, and minor wording changes.)
(Controllers verified to have the Debug port capability)
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* 8086:24dd Intel ICH5
 
* 8086:24dd Intel ICH5
 
* 8086:265c Intel ICH6
 
* 8086:265c Intel ICH6
 +
* 8086:27cc Intel ICH7
  
 
= Controllers verified to lack the Debug port capability =
 
= Controllers verified to lack the Debug port capability =

Revision as of 09:29, 24 July 2006

Serial ports have been the primary means of early debugging of new LinuxBIOS ports. New hardware doesn't always have a serial port and another method for early debugging is needed.

What is this debug port and why is it special?

The EHCI Debug Port is an optional capability of EHCI controllers. All USB2 host controllers are EHCI controllers. The debug port provides a mode of operation that requires neither RAM nor a full USB stack. A handful of registers in the EHCI controller PCI configuration and BAR address space are used for all communication. All three transfer types are supported (OUT/SETUP/IN) but transfers can only be a maximum of 8 bytes and only one specific physical USB port can be used. A Debug Class compliant device is the only supported USB function that can be communicated with.

Debug Class Device

While the Debug Class functional spec describes a device communicating over USB also with the debugging host (aka remote) it would be very possible to make a Debug Class device with a regular serial port on the other end. One thing to watch out for is that such a device might not be able to handle the same throughput as the debug port itself and hence may lose data unless it can do some buffering.

Considerations in LinuxBIOS

We'll use Mode 1 since a full USB stack and EHCI driver isn't running when we're using the debug port. We get early two-way communication from PCI memory write accesses. printf() should transmit also to the debug port on any (all?) EHCI controllers sporting the capability. Linux already supports this and we could probably copy code or headers from the kernel.

Hardware capability

The Debug Port is optional, please check if EHCI controllers near you support it:

# lspci -vs $(lspci|grep EHCI|cut -f1 -d' ')
00:1d.7 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller (rev 03) (prog-if 20 [EHCI])
Subsystem: IBM Unknown device 0566
Flags: bus master, medium devsel, latency 0, IRQ 5
Memory at b0000000 (32-bit, non-prefetchable) [size=1K]
Capabilities: [50] Power Management version 2
Capabilities: [58] Debug port

Look for a line like the last one above.

Please include the PCI device id too:

# lspci -ns $(lspci|grep EHCI|cut -f1 -d' ')
00:1d.7 0c03: 8086:265c (rev 03)

If your controller isn't already listed below then please add it or send an email to the Mailinglist if you don't have a wiki account yet and want one, or want us to add your controller to the page.

Controllers verified to have the Debug port capability

  • 8086:24dd Intel ICH5
  • 8086:265c Intel ICH6
  • 8086:27cc Intel ICH7

Controllers verified to lack the Debug port capability

Links

The Debug Port is described in Appendix C.

This is what has to be connected to the EHCI controller.