EHCI Debug Port
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Serial ports have been the primary means of early debugging of new coreboot ports. New hardware doesn't always have a serial port and another method for early debugging is needed.
The EHCI Debug Port is an optional capability of EHCI controllers. All USB2 host controllers are EHCI controllers. The debug port provides a mode of operation that requires neither RAM nor a full USB stack. A handful of registers in the EHCI controller PCI configuration and BAR address space are used for all communication. All three transfer types are supported (OUT/SETUP/IN) but transfers can only be a maximum of 8 bytes and only one specific physical USB port can be used. A Debug Class compliant device is the only supported USB function that can be communicated with.
Debug Class Device
While the Debug Class functional spec describes a device communicating over USB also with the debugging host (aka remote) it would be very possible to make a Debug Class device with a regular serial port on the other end. One thing to watch out for is that such a device might not be able to handle the same throughput as the debug port itself and hence may lose data unless it can do some buffering.
Considerations in coreboot
We'll use Mode 1 since a full USB stack and EHCI driver isn't running when we're using the debug port. We get early two-way communication from PCI memory write accesses. printf() should transmit also to the debug port on any (all?) EHCI controllers sporting the capability. Linux already supports this and we could probably copy code or headers from the kernel.
The Debug Port is optional, please check if EHCI controllers near you support it:
# lspci -vs $(lspci|grep EHCI|cut -f1 -d' ') 00:1d.7 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller (rev 03) (prog-if 20 [EHCI]) Subsystem: IBM Unknown device 0566 Flags: bus master, medium devsel, latency 0, IRQ 5 Memory at b0000000 (32-bit, non-prefetchable) [size=1K] Capabilities:  Power Management version 2 Capabilities:  Debug port
Look for a line like the last one above.
Please include the PCI device id too:
# lspci -ns $(lspci|grep EHCI|cut -f1 -d' ') 00:1d.7 0c03: 8086:265c (rev 03)
If your controller isn't already listed below then please add it or send an email to the Mailinglist if you don't have a wiki account yet and want one, or want us to add your controller to the page.
Controllers verified to have the Debug port capability
- 10b9:5239 ALi Corporation USB 2.0 (USB PCI card)
- 8086:24cd Intel ICH4/ICH4-M
- 8086:24dd Intel ICH5
- 8086:265c Intel ICH6
- 8086:268c Intel 631xESB/632xESB/3100 Chipset (rev 09) (in Dell PE 1950)
- 8086:27cc Intel ICH7
- 8086:2836 Intel ICH8
- 8086:283a Intel ICH8
- 8086:293a Intel ICH9 (rev 2)
- 10de:0088 NVIDIA MCP2A (rev a2)
- 10de:005b NVIDIA CK804 (rev a3)
- 10de:026e NVIDIA MCP51 (rev a3)
- 10de:036d NVIDIA MCP55 (rev a2)
- 10de:03f2 NVIDIA MCP61 (rev a3)
- 1002:4386 ATI/AMD SB600
- 1106:3104 VIA VX800 (rev 90)
Controllers verified to lack the Debug port capability
- 1033:00e0 NEC Corporation EHCI (rev 02) (Compaq part)
- 1106:3104 VIA Technologies EHCI (rev 82, rev 63, rev 86)
- 1002:4373 ATI Technologies Inc IXP SB400 USB2 Host Controller (rev 80)
- 1022:2095 Advanced Micro Devices [AMD] CS5536 [Geode companion] EHC (rev 02)
- 8086:24cd Intel Corporation 82801DB/DBM (ICH4/ICH4-M) EHCI (rev 01)
- 1039:7002 SiS EHCI (rev 00)
Where to buy
Currently there seems to be only one device which can use the EHCI Debug Port, the NET20DC.
- EHCI 1.0 spec (PDF) — The Debug Port is described in Appendix C.
- Debug Class functional spec (PDF) — This is what has to be connected to the EHCI controller.
- Intel Developer UPDATE Magazine on USB debugging (PDF)
- libusb host program for PLX NET20DC debug device
- Linux x86_64 early USB Debug Port support