GSoC

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The wiki is being retired!

Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!

Google Summer of Code 2009

Welcome to the Google Summer of Code(tm) page of the coreboot project.

Your own Projects

We've listed some ideas for projects here, but we're more than happy to entertain other ideas if you've got any. Feel free to contact us under the address below, and don't hesitate to suggest whatever you have in mind.

Possible ideas

Infrastructure for automatic code checking

We already have a build bot that builds various configurations of coreboot. It would be nice to extend it with various code validation routines, for example:

  • Validate that there's no regression in doxygen documentation (eg. are all arguments to functions still explained in @param tags, eg. after new arguments were added?)
  • Make code lint clean (and maybe extend lint to not fall into our traps), and run lint over the tree. Report regressions
  • Use LLVM's static code checking facilities, report regressions.
  • Work on code coverage support for coreboot code (dump data into ram, or via serial. Provide tools to fetch it). Analyse that data.

Links


VGA BIOS for Geode LX

This project's goal is to write a VGA BIOS (PCI option rom) for AMD Geode LX systems (such as the Linutop, Thincan or XO). There exists a free VGA BIOS but it knows nothing about real hardware. If you really want to kick the iron, this project could be enhanced to contain a complete infrastructure for including hardware initialization code for many different graphics cards.

USB Option ROM for SeaBIOS

SeaBIOS is our latest and greatest way to boot all kinds of different operating systems. It is a coreboot payload that implements 16bit BIOS interrupts as they are needed by nearly all boot loaders today. In the last year, SeaBIOS learned how to cope with coreboot ACPI, and how to boot off SCSI drives. One major feature that we're desperately lacking is USB stick booting from SeaBIOS.

TianoCore on coreboot

Tiano Core is Intel's EFI implementation. Unlike coreboot, it is not a firmware, but rather a bootloader. Last year we started porting TianoCore to run on coreboot, but there are many things left to do. Improve Tiano Core running as a coreboot payloads, or change coreboot so it can load Tiano Core as a payloads.

This project requires no hardware skills, but especially in case of TianoCore might require knowledge of Windows compilers (VC2005?)

coreboot graphical port creator

In coreboot v2, every port to a new mainboard requires that you touch a lot of source files with only minimal changes. In version 3 we try to fix this issue and pack all mainboard specific information into a configuration file that we call the Device Tree Source (DTS). This Device Tree config file is a simple text file describing what static (non-detectable and/or soldered on) devices are used on the mainbard and how they are wired (SPD-ROM, Interrupt Routing, SuperIO, Northbridge, Southbridge, Hypertransport,..). It is mostly organized as a tree (with some special cases, Hypertransport allows cycles for instance)

The idea is to create a tool, based on the [www.eclipse.org/ Eclipse IDE], Swing, or your favourite portable toolkit, which allows you to drag and drop those components together and describe how they are wired.

This would be a great help for mainboard vendors that build mainboards of already supported components. No more reading of coreboot code would be required, but rather only the understanding of the hardware, and probably the mainboard schematics.

This is a coreboot v3 project. It requires good Java and/or Eclipse skills (or whatever toolkit/language you choose)

libpayload

There are many, many "payloads" for coreboot these days: Linux, FILO, GRUB2, Tiano Core, Open Firmware, etherboot, and some more to count. All these payloads have a few functions in common that they use to read information from coreboot or change coreboot settings in NVRAM. It would be incredibly useful to unify all this code and enhance it, so that not every coreboot payload has to keep reinventing the wheel.

Summer of Code Application

Please complete the standard Google SoC 2008 application. Additionally, please provide information on the following:

  1. Who are you? What are you studying?
  2. Why are you the right person for this task?
  3. Do you have any other commitments that we should know about?
  4. List your C, Assembler or Java experience. (Depending on the project)
  5. List your history with open source projects.
  6. What is your preferred method of contact? (Phone, email, Skype, etc)

Feel free to keep your application short. A 15 page essay is no better than a 2 page summary. If you wish to write 15 pages, you are of course welcome to do so, and we will gladly put your paper up on the web page. But it is not required for the application.

The Drupal project has a great page on How to write an SOC application.

DEADLINE FOR STUDENT APPLICATIONS: Students who are interested in working on a coreboot-related GSoC project must apply between March 24, 2008 and March 30, 2008!

Contact

If you are interested in becoming a GSoC student, please contact Stefan Reinauer.

There is also an IRC channel on irc.freenode.net: #coreboot