This page is a work in progress. Entries are not in alphabetical order.
MMIO (Memory-mapped I/O) and port I/O (also called port-mapped I/O or PMIO) are two complementary methods of performing input/output between the CPU and I/O devices in a computer.
PIO (Programmed Input/Output) interface is the original method used to transfer data between the CPU (through the IDE controller) and an IDE/ATA device.
The Framebuffer is a part of RAM in a computer allocated to hold the graphics information for one frame or picture. This information typically consists of color values for every pixel on the screen. A framebuffer is either:
- Off-screen, meaning that writes to the framebuffer don't appear on the visible screen
- On-screen, meaning that the framebuffer is directly coupled to the visible display
POST (Power On Self Test) is a test to check that devices the computer will rely on are functioning, and initializes devices.
I2C - Inter-Integrated-Circuit, a bidirectional 2-wire bus for efficient inter-IC control. See 'http://www.esacademy.com/faq/i2c/index.htm' for more info.
Code examples(?): ...
VID - Vendor ID, a way of identifying the hardware manufacturer. See 'http://www.microsoft.com/whdc/system/bus/PCI/infreq.mspx' and 'http://pciids.sourceforge.net/' for more info.
A way of obtaining info for your hardware is through the 'lspci' command. Simply type 'lspci -n' in the console (or an xterm) or 'lspci -vn' for more verbose output.
DID - Device ID, a way of identifying the hardware in question. See VID (above) for more info.
DMA (Direct Memory Access) allows certain hardware subsystems within a computer to access system memory for reading and/or writing independently of the main CPU. Examples of systems that use DMA: Hard Disk Controller, Disk Drive Controller, Graphics Card, Sound Card. DMA is an essential feature of all modern computers, as it allows devices of different speeds to communicate without subjecting the CPU to a massive interrupt load.
RDMA (Remote Direct Memory Access) is a concept whereby two or more computers communicate via DMA directly from main memory of one system to the main memory of another.
The purpose of the VGAcon (VGA controller) is to isolate the details of VGA signal generation from all the other modules in a (hardware) design. It allows the pixel information to be written into its video memory using a very simple interface, while it is alone responsible for generating the required signals for displaying the pixel information on a VGA monitor. (Note: This is mostly relevant to a hardware design - the text is copied from a students fpga project)
AHCI (Advanced Host Controller Interface). Describes the register-level interface for a SATA host controller.
OHCI (Open Host Controller Interface). IEEE1394 (Firewire) and USB standard (mostly used by other companies than Intel)
UHCI (Universal Host Controller Interface). USB standard.
SPI (Serial Peripheral Interface Bus) is a very loose standard for controlling almost any digital electronics that accepts a clocked serial stream of bits.
SIO (Serial Input/Output)
PIC (Programmable Interrupt Controller) is a device to control peripheral devices, offloading the main CPU.
PLL (Phase Locked Loop) is a device to keep (electrical) signals synchronised throughout the system.
SuperIO is the chip that provides floppy, serial and parallel functionality/ports.
SPD (Serial Presence Detect). On every (?) memory module there's an eprom that provides BIOS with information on how to properly configure the memory module.
SMBus (System Management Bus) is a simple two-wire bus used for communication with low-bandwidth devices on a motherboard. It is based on (actually a subset of) I2C.
ACPI (Advanced Configuration & Power Interface) is an industry standard for letting the OS control power management.
APIC (Advanced Programmable Interrupt Controller). An advanced version of a PIC that can handle interrupts from and for multiple CPUs. Modern systems usually have several Apics: Local APICs are CPU-bound, IO-APICs are bridge-bound.
VMEBus (VERSAmodule Eurocard Bus OR Versa Module Europa Bus). A computer bus originally developed for the Motorola 68000.
PCI (Peripheral Component Interconnect).
PCI Configuration Space.
PIRQ (Pci IRQ routing table).
http://www.microsoft.com/whdc/archive/pciirq.mspx http://www.rojakpot.com/default.aspx?location=8&var1=0&var2=148 http://www.soundonsound.com/sos/jul04/articles/qa0704-1.htm Interesting tool?: https://bugzilla.redhat.com/bugzilla/attachment.cgi?id=93717&action=view
PAM (Programmable Attribute Map).
hardware registers that describe how certain memory areas are accessed. The BIOS areas have a flash chip mapped on top of a piece of memory. By changing the PAM registers accesses to these memory areas can be mapped to either the RAM or the flash device. Shadowing is implemented by setting read accesses to the flash device and write accesses to the same address space are mapped to RAM. Walking over the address space, each byte is read and immediately written from/to each address. Afterwards write accesses are ignored and read accesses are mapped to RAM. Usually the PAM registers are part of the southbridge of a system.
SMM (System Management Mode)
Processor mode that is mainly used for power management purposes.
SMRAM (System Management Random Access Memory).
MPTable (Multi Processor Table). Intel MP specification is a hardware compatibility guide for machine hardware designers and OS software writers to produce SMP-capable machines and OSes in a vendor-independent manner. v1.1 and v1.4 versions exist.
PIR (Programmable Interrupt Routing?)
DCR (Decode Control Register)
LPC (Low Pin Count). An interface aimed at replacing he ISA bus.
IDSEL/AD (Initialization Device SELect/Address and Data).
Each PCI slot has a signal called IDSEL. It is used to differentiate between the different cards?
PHY (PHY layer device). A device that provides low level access to the physical layer.
MII (Media Independent Interface). This is a chip commonly found on ethernet devices, together with a PHY.
BAR (Base Address Register)
MTRR (Memory Type Range Register). This can be used to control the way a processor accesses memory ranges.
PAT (Page Attribute Table). Can be used independently or in combination with MTRR to setup memory type access ranges. Allows more finely-grained control than MTRR.
TLB (Translation Lookaside Buffer). The TLB stores the most recently used page-directory and page-table entries, which translates into speedier access to said memory.
http://www.linuxelectrons.com/article.php/20031021142247752 For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.1
UC (strong UnCacheable). Memory type setting in MTRR/PAT.
UC- (UnCacheable). Memory type setting in MTRR/PAT.
WC (Write-Combining). Memory type setting in MTRR/PAT.
WT (Write-Through). Memory type setting in MTRR/PAT.
WB (Write-Back). Memory type setting in MTRR/PAT.
WP (Write Protected). Memory type setting in MTRR/PAT.
For more details see IA-32 Intel256 Architecture Software Developer's Manual: Vol3 Section 10.3
PAT (Performance Acceleration Technology).
AGP (Advanced Graphics Port).
AGP Aperture. The memory range that is set aside for AGP access.
GART (Graphics Address Relocation Table)
SBA (SideBand Addressing)
GATT (Graphics Aperture Translation Table)
PLCC (Plastic Leaded Chip Carrier). A square Surface-mount chip package.
LRU (Least Recently Used). A rule used in operating systems that utilises a paging system. LRU selects a page to be paged out if it has been used less recently than any other page. This may be applied to a cache system as well.
GPIO (General Purpose Input/Output).
Chip on the mainboard that is usually responsible for handling the flash device, IDE controller, ...