The wiki is being retired!
Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!
This page collects a list of projects to improve the infrastructure of coreboot-v2. Infrastructure means those parts of the code that aren't chipset or mainboard specific, but are used by all of them. The idea is to consolidate a list of things "to do" with their status and responsible developers.
SeaBIOS requires a copy of various BIOS tables outside the fseg as it overwrites that segment. Generally clean out the table generation code.
Status: Upstream, implemented on some boards. There are problems on some chipsets/boards because of incorrect CONFIG_VIDEO_MB handling. The might be other issues, too (not clear, yet).
|intel/i945||Y||Tested on Kontron 986LCD-M and Roda RK886EX|
|via/cn700||Y||Tested on VIA pc2500e.|
A filesystem-alike layout for the coreboot image, to enable systems like bayou and to clean up the system in general (eg. no more buildrom).
Upstream, pre-CBFS infrastructure removed.
There are places where using CBFS might be a good idea: Everything that makes use of external files, for example the VSA code in the Geode chipset code. VSA is converted, and tested on a couple of configurations, but untested on others.
Some boards have issues with CBFS because it requires the whole ROM to be accessible at a quite early point in time (compared to the old mechanism). The following table contains validated knowledge if the ROM mapping happens at the right time.
All boards that manage to boot in a tinybootblock configuration are capable at least for the used ROM size (it might be that larger ROMs would fail because they require mapping the larger space)
|Vendor/chipset||ROM enabled||Status / Comments|
|amd/amd8111||Y||An enable_rom() function is implemented and called failover_process(). Untested on hardware, though.|
|amd/cs5530||Y||Not tested on hardware, yet.|
|broadcom/bcm5785||Y||An enable_rom() function is implemented and called failover_process(). Untested on hardware, though.|
|intel/i82371eb||Y||Build- and runtime-tested on ASUS P2B by Uwe Hermann|
|nvidia/ck804||Y||An enable_rom() function is implemented and called failover_process(). Untested on hardware, though.|
|nvidia/mcp55||Y||An enable_rom() function is implemented and called failover_process(). Untested on hardware, though.|
|sis/sis966||Y||An enable_rom() function is implemented and called failover_process(). Untested on hardware, though.|
Developers: Stefan, Ron, Patrick, Myles, Uwe
Common payload location
Many boards in v2 have different names for the payload in targets/.../Config.lb (payload.elf, filo.elf, etherboot.elf, etc) and locations (../payload.elf, or various absolute paths which only work for one developer). The problem will be fixed with kconfig in v2 where the user specifies a payload manually in "make menuconfig".
Right now, the decision whether to use fallback or normal is in cache_as_ram_auto.c in many boards. Make that generic again (also helps with further CBFSification at some point).
Status: Available in Kconfig, works on a couple of boards. Requires per southbridge changes (and northbridge in some cases) on many boards (related to ROM enable, see CBFS section). The current massive duplication of code in cache_as_ram_auto.c can be eliminated as soon as newconfig is gone.
Unify text printing functions
There are several copies of print_* and printk_* in the code. Unify them so everything is happier than before (because the disjoint features are merged).
Every ACPI board has its own routines to compile the ACPI sources. Unify that. Also, figure out generic ACPI code and deduplicate it.
Allow (somehow) to define defaults for all CMOS fields, and create a static table from that. Use that at runtime if the CMOS checksum fails.
Unify UMA / onboard video code and config
Unify CONFIG_VIDEO_MB, CONFIG_GFXUMA, and similar options and make all code honor them.
Add / Unify / Test kconfig compile-time options and runtime CMOS options in coreboot
Some coreboot options are compile-time configurable only at the moment (Config.lb or kconfig), but should also be runtime-configurable via CMOS/NVRAM options. We should fix this.
- Make all options (where it makes sense) run-time configurable via CMOS options, in addition to having sane compile-time defaults configured via kconfig.
- This includes many options which are northbridge-specific, many southbridge-specific, and some board-specific ones.
- Example options: Enable/disable IDE channel(s) / SATA / USB / SCSI / etc., enable/disable UDMA on older boards, amount of memory used for IGP/UMA, choice between IDE or NAND flash (on CS5536 boards), IDE 40/80 pin cable selection (VT8237R boards for example), and many more.
- Some of these options are already handled in the code via CMOS options, some are compile-time only so far, so do not yet exist at all.
Port v3 Resource Allocator
The v3 resource allocator should be ported to v2.
Status: Upstream. It's limited to one area for resources, that doesn't overlap with fixed resources.
Config & Build System
The current system of generated Makefiles is non-ideal (for too many reasons for this little margin). Fix it, somehow. Use KConfig to improve the configuration management.
Status: Upstream, boards are converted. Old system is gone. All boards build. HOWEVER, not all boards have been boot-tested yet, please report any issues you encounter!
Developers: Stefan, Ron, Patrick, Uwe, Cristi