Difference between revisions of "Previous GSoC Projects"

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* http://blogs.coreboot.org/blog/2013/09/25/pencils-down/
* http://blogs.coreboot.org/blog/2013/09/25/pencils-down/
* [https://www.google-melange.com/gsoc/project/google/gsoc2013/mrnuke/5011848877309952 Final report with download]
* [https://www.google-melange.com/gsoc/project/google/gsoc2013/mrnuke/5011848877309952 Final report with download]
== Prepare for the lack of super-io UARTs and serialports on new mainboards ==
There are some common debugging problems people come across when starting a port of a new mainboard for coreboot. First is the flashchip being soldered on the mainboard and second is the lack of serial port connector. I attempt to attack both of these on some level. My primary goals are to add support for memory-mapped serial UARTs and the ECHI debug port mechanism on the commonly used payloads, and to integrate a pre-OS flash writing mechanism in the toolchain to allow easy and safe deployment of new coreboot builds.
'''Results'''
* http://blogs.coreboot.org/blog/2013/06/07/new-coreboot-debugging-solutions/
* http://blogs.coreboot.org/blog/2013/06/25/kick-starting-with-some-maintenance/
* http://blogs.coreboot.org/blog/2013/07/02/now-it-is-broken-now-it-is-not/
* http://blogs.coreboot.org/blog/2013/07/09/gsoc-early-debugging-art-of-refactor/
* http://blogs.coreboot.org/blog/2013/08/06/gsoc-early-debugging-agesa-woes/
* http://blogs.coreboot.org/blog/2013/08/20/gsoc-early-debugging-usb-submission/
* http://blogs.coreboot.org/blog/2013/08/28/gsoc-early-debugging-bridging-the-gap/
* http://blogs.coreboot.org/blog/2013/09/05/gsoc-early-debugging-more-connectivity/
* http://blogs.coreboot.org/blog/2013/09/23/gsoc-early-debugging-closure/
* [https://www.google-melange.com/gsoc/project/google/gsoc2013/kmalkki/4907670150578176 Final report with download]
== flashrom: infrastructure improvements galore ==
The plan is to tackle some long-standing infrastructure problems that have to be fixed eventually if we want to continue current and future flash chips. The expected outcome of my GSoC programming are the following new features:
* Support for multiple read/write operations
* Support for 4-byte addresses
* Improved (SPI) probing
'''Results'''
* http://blogs.coreboot.org/blog/2013/05/28/gsoc-2013-flashrom-hi-there-again/
* http://blogs.coreboot.org/blog/2013/06/26/gsoc-2013-flashrom-week-1-while1/
* http://blogs.coreboot.org/blog/2013/07/01/gsoc-2013-flashrom-week-2/
* http://blogs.coreboot.org/blog/2013/07/10/gsoc-2013-flashrom-week-3/
* http://blogs.coreboot.org/blog/2013/07/16/gsoc-2013-flashrom-week-4/
* http://blogs.coreboot.org/blog/2013/08/12/gsoc-2013-flashrom-blog-post-5/
* http://blogs.coreboot.org/blog/2013/08/29/gsoc-2013-flashrom-blog-post-6/
* http://blogs.coreboot.org/blog/2013/09/04/gsoc-2013-flashrom-blog-post-7/
* http://blogs.coreboot.org/blog/2013/09/12/gsoc-2013-flashrom-blog-post-8/
* [https://www.google-melange.com/gsoc/project/google/gsoc2013/stefant/5817378583609344 Final report with download]


= 2012 - No GSoC =
= 2012 - No GSoC =

Revision as of 22:56, 11 February 2014