Difference between revisions of "Previous GSoC Projects"

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This site lists all previous [[GSoC|Google summer of Code]] projects related to coreboot.
This site lists all previous [[GSoC|Google summer of Code]] projects related to coreboot.
= 2014 =
== Generic Interface using alternate CBFS access patterns for ARM SoCs ==
* http://blogs.coreboot.org/blog/2014/05/01/moin-a-new-beginning/
* http://blogs.coreboot.org/blog/2014/05/11/pre-gsoc-set-up-phase-i/
* http://blogs.coreboot.org/blog/2014/05/20/pre-gsoc-set-up-phase-ii/
* http://blogs.coreboot.org/blog/2014/05/29/cbfs_media-week-1/
* http://blogs.coreboot.org/blog/2014/06/09/gsoc-2014-cbfs_media-updates/
* http://blogs.coreboot.org/blog/2014/06/24/gsoc-2014cbfs_media-stage-1-mission-accomplished/
* http://blogs.coreboot.org/blog/2014/07/04/gsoc-2014-cbfs_media-stage-2/
* http://blogs.coreboot.org/blog/2014/07/17/gsoc-2014-payload-loading-success/
== Enhance early coreboot debugging ==
* http://blogs.coreboot.org/blog/2014/05/05/gsoc-early-debugging-the-very-short-introduction/
* http://blogs.coreboot.org/blog/2014/05/30/gsoc-board-status-update/
* http://blogs.coreboot.org/blog/2014/08/03/gsoc-infrastructure-along-the-way-something-went-terribly-wrong/
== flashrom ==
* http://blogs.coreboot.org/blog/2014/05/04/gsoc-2014-flashrom-do-i-need-to-introduce-myself/
* http://blogs.coreboot.org/blog/2014/06/04/gsoc-2014-flashrom-rise-like-a-phoenix/
* http://blogs.coreboot.org/blog/2014/07/30/gsoc-2014-flashrom-support-for-intel-bay-trail-rangeleyavoton-and-wildcat-point/
= 2013 =
== coreboot cheap testing rig ==
The goal of this project is to create a cheap testing rig which works with the existing board test infrastructure. We have a hardware test system since 2006:
* [http://www.coresystems.de/PDFs/LinuxBIOS-testing/Slides-LinuxBIOS-QA.pdf Quality Assurance Talk (Slides)]
* [http://www.coresystems.de/PDFs/LinuxBIOS-testing/TestIntegrationManual.pdf Test Integration Manual]
* [http://www.coresystems.de/PDFs/LinuxBIOS-testing/DevelopersManual.pdf Test Developers Manual]
* [http://www.coresystems.de/PDFs/LinuxBIOS-testing/TestSpecification.pdf Test Specification]
The initial version of our testing rig used a remote power switch and was rather expensive. With cheaper technologies such as [http://en.wikipedia.org/wiki/X10_%28industry_standard%29 X10], it's possible to drop the testing costs per board significantly.
'''Links'''
* [[InSystemFlasher]] is a cheap DIY hardware prototype for building an automated testing rig for modern SPI-based boards. This could be used as a starting point.
'''Report'''
* http://blogs.coreboot.org/blog/2013/06/20/hello/
* http://blogs.coreboot.org/blog/2013/07/01/gsoc-coreboot-progress-till-week-2/
* http://blogs.coreboot.org/blog/2013/07/19/gsoc-coreboot-week-3-and-4/
* http://blogs.coreboot.org/blog/2013/08/07/gsoc-coreboot-week-5-7-redesigning-the-test-interface-board/
* http://blogs.coreboot.org/blog/2013/09/09/gsoc-coreboot-test-interface-board-complete/
* [https://www.google-melange.com/gsoc/project/google/gsoc2013/ayush3504/5453027917955072 Final report with download]
<br/><br/>
== A universal USB-based FWH/LPC/SPI programmer ==
While flashing SPI chips can be done externally with relative ease using flashrom, hardware to program FWH and LPC chips is beyond the reach of most enthusiasts. Cortex-M processors have become well-established in the open source community due to their low cost and extensive ecosystem. This makes them an ideal candidate for a universal ROM programmer. I propose a hardware/software/firmware ecosystem for a universal ROM programmer based on Cortex-M processors.
'''Report'''
* http://blogs.coreboot.org/blog/2013/06/07/hello-world/
* http://blogs.coreboot.org/blog/2013/06/09/launch-control-and-a-brief-test-flight/
* http://blogs.coreboot.org/blog/2013/06/14/a-biology-laboratory-dissecting-the-lpc-bus/
* http://blogs.coreboot.org/blog/2013/06/23/vultureprog-meet-the-contenders/
* http://blogs.coreboot.org/blog/2013/06/29/qiprog-the-soft-side-of-vultureprog/
* http://blogs.coreboot.org/blog/2013/07/03/cooking-with-thin-spaghetti-the-hard-side-of-vultureprog/
* http://blogs.coreboot.org/blog/2013/07/20/qiprog-expanding-the-flight-range/
* http://blogs.coreboot.org/blog/2013/07/25/vultureprog-equipped-for-galactic-travel/
* http://blogs.coreboot.org/blog/2013/08/07/vultureprog-command-center/
* http://blogs.coreboot.org/blog/2013/08/14/3265/
* http://blogs.coreboot.org/blog/2013/08/20/a-brief-progress-sheet/
* http://blogs.coreboot.org/blog/2013/08/27/retrofitting-qiprog-for-the-space-age/
* http://blogs.coreboot.org/blog/2013/09/25/pencils-down/
* [https://www.google-melange.com/gsoc/project/google/gsoc2013/mrnuke/5011848877309952 Final report with download]
== Prepare for the lack of super-io UARTs and serialports on new mainboards ==
There are some common debugging problems people come across when starting a port of a new mainboard for coreboot. First is the flashchip being soldered on the mainboard and second is the lack of serial port connector. I attempt to attack both of these on some level. My primary goals are to add support for memory-mapped serial UARTs and the ECHI debug port mechanism on the commonly used payloads, and to integrate a pre-OS flash writing mechanism in the toolchain to allow easy and safe deployment of new coreboot builds.
'''Results'''
* http://blogs.coreboot.org/blog/2013/06/07/new-coreboot-debugging-solutions/
* http://blogs.coreboot.org/blog/2013/06/25/kick-starting-with-some-maintenance/
* http://blogs.coreboot.org/blog/2013/07/02/now-it-is-broken-now-it-is-not/
* http://blogs.coreboot.org/blog/2013/07/09/gsoc-early-debugging-art-of-refactor/
* http://blogs.coreboot.org/blog/2013/08/06/gsoc-early-debugging-agesa-woes/
* http://blogs.coreboot.org/blog/2013/08/20/gsoc-early-debugging-usb-submission/
* http://blogs.coreboot.org/blog/2013/08/28/gsoc-early-debugging-bridging-the-gap/
* http://blogs.coreboot.org/blog/2013/09/05/gsoc-early-debugging-more-connectivity/
* http://blogs.coreboot.org/blog/2013/09/23/gsoc-early-debugging-closure/
* [https://www.google-melange.com/gsoc/project/google/gsoc2013/kmalkki/4907670150578176 Final report with download]
== flashrom: infrastructure improvements galore ==
The plan is to tackle some long-standing infrastructure problems that have to be fixed eventually if we want to continue current and future flash chips. The expected outcome of my GSoC programming are the following new features:
* Support for multiple read/write operations
* Support for 4-byte addresses
* Improved (SPI) probing
'''Results'''
* http://blogs.coreboot.org/blog/2013/05/28/gsoc-2013-flashrom-hi-there-again/
* http://blogs.coreboot.org/blog/2013/06/26/gsoc-2013-flashrom-week-1-while1/
* http://blogs.coreboot.org/blog/2013/07/01/gsoc-2013-flashrom-week-2/
* http://blogs.coreboot.org/blog/2013/07/10/gsoc-2013-flashrom-week-3/
* http://blogs.coreboot.org/blog/2013/07/16/gsoc-2013-flashrom-week-4/
* http://blogs.coreboot.org/blog/2013/08/12/gsoc-2013-flashrom-blog-post-5/
* http://blogs.coreboot.org/blog/2013/08/29/gsoc-2013-flashrom-blog-post-6/
* http://blogs.coreboot.org/blog/2013/09/04/gsoc-2013-flashrom-blog-post-7/
* http://blogs.coreboot.org/blog/2013/09/12/gsoc-2013-flashrom-blog-post-8/
* [https://www.google-melange.com/gsoc/project/google/gsoc2013/stefant/5817378583609344 Final report with download]
= 2012 - No GSoC =
= 2012 - No GSoC =
Regretfully, coreboot was not selected for GSoC 2012.
Regretfully, coreboot was not selected for GSoC 2012.
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* [https://sites.google.com/site/pinczakko/low-cost-embedded-x86-teaching-tool-2 Low Cost Embedded x86 Teaching Tool] by Darmawan Salihun contains an Option ROM example
* [https://sites.google.com/site/pinczakko/low-cost-embedded-x86-teaching-tool-2 Low Cost Embedded x86 Teaching Tool] by Darmawan Salihun contains an Option ROM example
* Another [http://www.coresystems.de/~stepan/optionrom2.tar.bz2 Option ROM example]
* Another [http://www.coresystems.de/~stepan/optionrom2.tar.bz2 Option ROM example]
* [[USB Option ROM progess]]


=== Mentors ===
=== Mentors ===
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Currently coreboot can not boot from an arbitrary SCSI controller. There are two solutions for the problem:
Currently coreboot can not boot from an arbitrary SCSI controller. There are two solutions for the problem:
* Use Linux and Kexec. This requires to keep the SCSI driver in the flash chip.
* Use Linux and Kexec. This requires to keep the SCSI driver in the flash chip.
* Use x86emu/vm86/[[ADLO]] and the int13 method. This would allow to use the PCI option rom available on all modern SCSI controllers.
* Use x86emu/vm86/ADLO and the int13 method. This would allow to use the PCI option rom available on all modern SCSI controllers.


So we obviously need a solution based on the later. This could as well be implemented as a Linux program, as an intermediate payload, or as a shared library.
So we obviously need a solution based on the later. This could as well be implemented as a Linux program, as an intermediate payload, or as a shared library.
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* using a dedicated LinuxBIOS loader (ie. adapting [http://www.reactos.org/ ReactOS] FREELDR)
* using a dedicated LinuxBIOS loader (ie. adapting [http://www.reactos.org/ ReactOS] FREELDR)
* booting Windows on top of Linux using [http://www.xmission.com/~ebiederm/files/kexec/README kexec]/[http://kboot.sourceforge.net/ kboot]
* booting Windows on top of Linux using [http://www.xmission.com/~ebiederm/files/kexec/README kexec]/[http://kboot.sourceforge.net/ kboot]
* fixing [[ADLO]] so that it boots Vista/XP and removing the mainboard dependencies in it's code.
* fixing ADLO so that it boots Vista/XP and removing the mainboard dependencies in it's code.
* Some information on usage of bios services in Windows can be found [http://www.missl.cs.umd.edu/winint/index1.html here] and [http://www.missl.cs.umd.edu/winint/index2.html here].
* Some information on usage of bios services in Windows can be found [http://www.missl.cs.umd.edu/winint/index1.html here] and [http://www.missl.cs.umd.edu/winint/index2.html here].


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== Boot OpenSolaris, FreeBSD, NetBSD, OpenBSD or other free OSes ==
== Boot OpenSolaris, FreeBSD, NetBSD, OpenBSD or other free OSes ==


LinuxBIOS has (despite its name) been a little Linux centric. A nice project would be to analyze what it takes to get OpenSolaris, the BSDs or other free operating systems to work in LinuxBIOS, without the need for legacy emulation (ie. no [[ADLO]])
LinuxBIOS has (despite its name) been a little Linux centric. A nice project would be to analyze what it takes to get OpenSolaris, the BSDs or other free operating systems to work in LinuxBIOS, without the need for legacy emulation (ie. no ADLO)


== Improve Linux as a BIOS [http://www.coreboot.org/Build_LinuxBIOS_using_LBdistro]==
== Improve Linux as a BIOS [http://www.coreboot.org/Build_LinuxBIOS_using_LBdistro]==

Latest revision as of 23:04, 22 February 2015