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Show new changes starting from 07:48, 1 June 2016
   

1 June 2016

     07:00  Supported Motherboards‎‎ (5 changes | history) . . (0). . [BoardStatusBot‎ (5×)]
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     05:43  Board:lenovo/t420‎ (diff | hist) . . (+50). . IruCai (Talk | contribs) (dp and eSATA)

31 May 2016

     22:01  Supported Motherboards‎‎ (16 changes | history) . . (+227). . [BoardStatusBot‎ (16×)]
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     21:01  Coreboot Options‎‎ (6 changes | history) . . (+424). . [BoardStatusBot‎ (6×)]
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N    11:22  User:Jn‎‎ (2 changes | history) . . (+591). . [Jn‎ (2×)]
     11:22 (cur | prev) . . (+69). . Jn (Talk | contribs)
N    11:11 (cur | prev) . . (+522). . Jn (Talk | contribs) (Created page with "Full name: Jonathan Neuschäfer ==GSoC 2016== During this year's Google Summer of Code, I'm working on improving coreboot's support for RISC-V systems. This involves: - Get...")
N    11:05  Board:emulation/spike-riscv‎‎ (2 changes | history) . . (+113). . [Jn‎ (2×)]
     11:05 (cur | prev) . . (+16). . Jn (Talk | contribs) (Link to the RISCV.org spike tool page instead of spike's github repo)
N    11:02 (cur | prev) . . (+97). . Jn (Talk | contribs) (Created page with "[https://github.com/riscv/riscv-isa-sim SPIKE] is [https://riscv.org/ RISC-V]'s primary emulator.")
     10:18 (User creation log) . . User account Avengerf12 (Talk | contribs) was created by Zaolin (Talk | contribs) and password was sent by email ‎(Another coreboot developer)

30 May 2016

     23:01  Supported Motherboards‎‎ (11 changes | history) . . (+12). . [BoardStatusBot‎ (11×)]
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     22:19 (User creation log) . . User account Jn (Talk | contribs) was created by Zaolin (Talk | contribs) and password was sent by email ‎(New coreboot developer (GSOC))
     22:01  Coreboot Options‎‎ (3 changes | history) . . (0). . [BoardStatusBot‎ (3×)]
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29 May 2016

     16:01  Supported Motherboards‎‎ (2 changes | history) . . (0). . [BoardStatusBot‎ (2×)]
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