Supported Motherboards and Coreboot Options: Difference between pages

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__NOTOC__
This is an automatically generated list of '''coreboot compile-time options'''.
This page was automatically generated. Please do not edit, any edits will be overwritten by an
automatic utility.


= Mainboards supported by coreboot =
Last update: 4.8-38-g8a25caee05
{| border="0" style="font-size: smaller"
|- bgcolor="#6699dd"
! align="left" | Option
! align="left" | Source
! align="left" | Format
! align="left" | Short Description
! align="left" | Description
|- bgcolor="#6699dd"
! align="left" | Menu: General setup || || || ||
|- bgcolor="#eeeeee"
| LOCALVERSION || toplevel || string || Local version string ||
Append an extra string to the end of the coreboot version.
 
This can be useful if, for instance, you want to append the
respective board's hostname or some other identifying string to
the coreboot version number, so that you can easily distinguish
boot logs of different boards from each other.
 
||
|- bgcolor="#eeeeee"
| CBFS_PREFIX || toplevel || string || CBFS prefix to use ||
Select the prefix to all files put into the image. It's "fallback"
by default, "normal" is a common alternative.
 
||
|- bgcolor="#eeeeee"
| CBFS_PREFIX || toplevel || string || Compiler to use ||
This option allows you to select the compiler used for building
coreboot.
You must build the coreboot crosscompiler for the board that you
have selected.
 
To build all the GCC crosscompilers (takes a LONG time), run:
make crossgcc
 
For help on individual architectures, run the command:
make help_toolchain
 
||
|- bgcolor="#eeeeee"
| COMPILER_GCC || toplevel || bool || GCC ||
Use the GNU Compiler Collection (GCC) to build coreboot.
 
For details see http://gcc.gnu.org.
 
||
|- bgcolor="#eeeeee"
| COMPILER_LLVM_CLANG || toplevel || bool || LLVM/clang (TESTING ONLY - Not currently working) ||
Use LLVM/clang to build coreboot.  To use this, you must build the
coreboot version of the clang compiler.  Run the command
make clang
Note that this option is not currently working correctly and should
really only be selected if you're trying to work on getting clang
operational.
 
For details see http://clang.llvm.org.
 
||
|- bgcolor="#eeeeee"
| ANY_TOOLCHAIN || toplevel || bool || Allow building with any toolchain ||
Many toolchains break when building coreboot since it uses quite
unusual linker features. Unless developers explicitely request it,
we'll have to assume that they use their distro compiler by mistake.
Make sure that using patched compilers is a conscious decision.
 
||
|- bgcolor="#eeeeee"
| CCACHE || toplevel || bool || Use ccache to speed up (re)compilation ||
Enables the use of ccache for faster builds.
 
Requires the ccache utility in your system $PATH.
 
For details see https://ccache.samba.org.
 
||
|- bgcolor="#eeeeee"
| FMD_GENPARSER || toplevel || bool || Generate flashmap descriptor parser using flex and bison ||
Enable this option if you are working on the flashmap descriptor
parser and made changes to fmd_scanner.l or fmd_parser.y.
 
Otherwise, say N to use the provided pregenerated scanner/parser.
 
||
|- bgcolor="#eeeeee"
| UTIL_GENPARSER || toplevel || bool || Generate SCONFIG & BINCFG parser using flex and bison ||
Enable this option if you are working on the sconfig device tree
parser or bincfg and made changes to the .l or .y files.
 
Otherwise, say N to use the provided pregenerated scanner/parser.
 
||
|- bgcolor="#eeeeee"
| USE_OPTION_TABLE || toplevel || bool || Use CMOS for configuration values ||
Enable this option if coreboot shall read options from the "CMOS"
NVRAM instead of using hard-coded values.
 
||
|- bgcolor="#eeeeee"
| STATIC_OPTION_TABLE || toplevel || bool || Load default configuration values into CMOS on each boot ||
Enable this option to reset "CMOS" NVRAM values to default on
every boot.  Use this if you want the NVRAM configuration to
never be modified from its default values.
 
||
|- bgcolor="#eeeeee"
| COMPRESS_RAMSTAGE || toplevel || bool || Compress ramstage with LZMA ||
Compress ramstage to save memory in the flash image. Note
that decompression might slow down booting if the boot flash
is connected through a slow link (i.e. SPI).
 
||
|- bgcolor="#eeeeee"
| COMPRESS_PRERAM_STAGES || toplevel || bool || Compress romstage and verstage with LZ4 ||
Compress romstage and (if it exists) verstage with LZ4 to save flash
space and speed up boot, since the time for reading the image from SPI
(and in the vboot case verifying it) is usually much greater than the
time spent decompressing. Doesn't work for XIP stages (assume all
ARCH_X86 for now) for obvious reasons.
 
||
|- bgcolor="#eeeeee"
| INCLUDE_CONFIG_FILE || toplevel || bool || Include the coreboot .config file into the ROM image ||
Include the .config file that was used to compile coreboot
in the (CBFS) ROM image. This is useful if you want to know which
options were used to build a specific coreboot.rom image.
 
Saying Y here will increase the image size by 2-3KB.
 
You can use the following command to easily list the options:
 
grep -a CONFIG_ coreboot.rom
 
Alternatively, you can also use cbfstool to print the image
contents (including the raw 'config' item we're looking for).
 
Example:
 
$ cbfstool coreboot.rom print
coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
offset 0x0
Alignment: 64 bytes
 
Name                          Offset    Type        Size
cmos_layout.bin                0x0        cmos layout  1159
fallback/romstage              0x4c0      stage        339756
fallback/ramstage              0x53440    stage        186664
fallback/payload              0x80dc0    payload      51526
config                        0x8d740    raw          3324
(empty)                        0x8e480    null        3610440
 
||
|- bgcolor="#eeeeee"
| COLLECT_TIMESTAMPS || toplevel || bool || Create a table of timestamps collected during boot ||
Make coreboot create a table of timer-ID/timer-value pairs to
allow measuring time spent at different phases of the boot process.
 
||
|- bgcolor="#eeeeee"
| TIMESTAMPS_ON_CONSOLE || toplevel || bool || Print the timestamp values on the console ||
Print the timestamps to the debug console if enabled at level spew.
 
||
|- bgcolor="#eeeeee"
| USE_BLOBS || toplevel || bool || Allow use of binary-only repository ||
This draws in the blobs repository, which contains binary files that
might be required for some chipsets or boards.
This flag ensures that a "Free" option remains available for users.
 
||
|- bgcolor="#eeeeee"
| COVERAGE || toplevel || bool || Code coverage support ||
Add code coverage support for coreboot. This will store code
coverage information in CBMEM for extraction from user space.
If unsure, say N.
 
||
|- bgcolor="#eeeeee"
| UBSAN || toplevel || bool || Undefined behavior sanitizer support ||
Instrument the code with checks for undefined behavior. If unsure,
say N because it adds a small performance penalty and may abort
on code that happens to work in spite of the UB.
 
||
|- bgcolor="#eeeeee"
| RELOCATABLE_RAMSTAGE || toplevel || bool || Build the ramstage to be relocatable in 32-bit address space. ||
The reloctable ramstage support allows for the ramstage to be built
as a relocatable module. The stage loader can identify a place
out of the OS way so that copying memory is unnecessary during an S3
wake. When selecting this option the romstage is responsible for
determing a stack location to use for loading the ramstage.
 
||
|- bgcolor="#eeeeee"
| CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM || toplevel || bool ||  ||
The relocated ramstage is saved in an area specified by the
by the board and/or chipset.
 
||
|- bgcolor="#eeeeee"
| UPDATE_IMAGE || toplevel || bool || Update existing coreboot.rom image ||
If this option is enabled, no new coreboot.rom file
is created. Instead it is expected that there already
is a suitable file for further processing.
The bootblock will not be modified.
 
If unsure, select 'N'
 
||
|- bgcolor="#eeeeee"
| BOOTSPLASH_IMAGE || toplevel || bool || Add a bootsplash image ||
Select this option if you have a bootsplash image that you would
like to add to your ROM.
 
This will only add the image to the ROM. To actually run it check
options under 'Display' section.
 
||
|- bgcolor="#eeeeee"
| BOOTSPLASH_FILE || toplevel || string || Bootsplash path and filename ||
The path and filename of the file to use as graphical bootsplash
screen. The file format has to be jpg.
 
||
 
|- bgcolor="#6699dd"
! align="left" | Menu: Mainboard || || || ||
|- bgcolor="#eeeeee"
| || || (comment) || || Important: Run 'make distclean' before switching boards ||
|- bgcolor="#eeeeee"
| VENDOR_WINNET || mainboard/winnet.name || bool || WinNET ||
WinNET boards. Used in various thin client appliances.
 
||
||
|- bgcolor="#eeeeee"
| UART_FOR_CONSOLE || mainboard/intel/mohonpeak || int ||  ||
The Mohon Peak board uses COM2 (2f8) for the serial console.
 
||
|- bgcolor="#eeeeee"
| PAYLOAD_CONFIGFILE || mainboard/intel/mohonpeak || string ||  ||
The Avoton/Rangeley chip does not allow devices to write into the 0xe000
segment.  This means that USB/SATA devices will not work in SeaBIOS unless
we put the SeaBIOS buffer area down in the 0x9000 segment.
 
||
|- bgcolor="#eeeeee"
| ENABLE_FSP_MEMORY_DOWN || mainboard/intel/harcuvar || bool || Enable Memory Down ||
Select this option to enable Memory Down function.
 
||
|- bgcolor="#eeeeee"
| SPD_LOC || mainboard/intel/harcuvar || hex || SPD binary location in cbfs ||
Location of SPD binary for memory down function.
 
||
|- bgcolor="#eeeeee"
| VBOOT || mainboard/intel/kblrvp || None || TPM to USE ||
This option allows you to select the TPM to use.
Select whether the board does not have TPM, TPM 1.1 or TPM 2.0
 
||
|- bgcolor="#eeeeee"
| UART_FOR_CONSOLE || mainboard/intel/littleplains || int ||  ||
The Little Plains board uses COM2 (2f8) for the serial console.
 
||
|- bgcolor="#eeeeee"
| PAYLOAD_CONFIGFILE || mainboard/intel/littleplains || string ||  ||
The Avoton/Rangeley chip does not allow devices to write into the 0xe000
segment.  This means that USB/SATA devices will not work in SeaBIOS unless
we put the SeaBIOS buffer area down in the 0x9000 segment.
 
||
|- bgcolor="#eeeeee"
| GALILEO_GEN2 || mainboard/intel/galileo || bool || Board generation: GEN1 (n) or GEN2 (y) ||
The coreboot binary will configure only one generation of the Galileo
board since coreboot can not determine the board generation at
runtime.  Select which generation of the Galileo that coreboot
should initialize.
 
||
|- bgcolor="#eeeeee"
| FSP_VERSION_1_1 || mainboard/intel/galileo || bool || FSP 1.1 ||
Use FSP 1_1 binary
||
|- bgcolor="#eeeeee"
| FSP_VERSION_2_0 || mainboard/intel/galileo || bool || FSP 2.0 ||
Use FSP 2.0 binary
 
||
|- bgcolor="#eeeeee"
| FSP_BUILD_TYPE_DEBUG || mainboard/intel/galileo || bool || Debug ||
Use the debug version of FSP
||
|- bgcolor="#eeeeee"
| FSP_BUILD_TYPE_RELEASE || mainboard/intel/galileo || bool || Release ||
Use the release version of FSP
 
||
|- bgcolor="#eeeeee"
| FSP_TYPE_1_1 || mainboard/intel/galileo || bool || MemInit subroutine ||
FSP 1.1 implemented as subroutines, no EDK-II cores
||
|- bgcolor="#eeeeee"
| FSP_TYPE_1_1_PEI || mainboard/intel/galileo || bool || SEC + PEI Core + MemInit PEIM ||
FSP 1.1 implemented using SEC and PEI core
||
|- bgcolor="#eeeeee"
| FSP_TYPE_2_0 || mainboard/intel/galileo || bool || MemInit subroutine ||
FSP 2.0 implemented as subroutines, no EDK-II cores
||
|- bgcolor="#eeeeee"
| FSP_TYPE_2_0_PEI || mainboard/intel/galileo || bool || SEC + PEI Core + MemInit PEIM ||
FSP 2.0 implemented using SEC and PEI core
 
||
|- bgcolor="#eeeeee"
| FSP_DEBUG_ALL || mainboard/intel/galileo || bool || Enable all FSP debug support ||
Turn on debug support to display HOBS, MTRRS, SMM_MEMORY_MAP, UPD_DATA
also turn on FSP 2.0 debug support for ESRAM_LAYOUT,
FSP_CALLS_AND_STATUS, FSP_HEADER, POSTCAR_CONSOLE and VERIFY_HOBS
or FSP 1.1 DISPLAY_FSP_ENTRY_POINTS
 
||
|- bgcolor="#eeeeee"
| VBOOT_WITH_CRYPTO_SHIELD || mainboard/intel/galileo || bool || Verified boot using the Crypto Shield board ||
Perform a verified boot using the TPM on the Crypto Shield board.
 
||
|- bgcolor="#eeeeee"
| DRIVER_TPM_I2C_ADDR || mainboard/intel/galileo || hex || Address of the I2C TPM chip ||
I2C address of the TPM chip on the Crypto Shield board.
 
||
|- bgcolor="#eeeeee"
| FMDFILE || mainboard/intel/galileo || string || FMAP description file in fmd format ||
The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
but in some cases more complex setups are required.
 
When an FMD descriptionn file is specified, the build system uses it
instead of creating a default FMAP file.
 
||
|- bgcolor="#eeeeee"
| BASEBOARD_GLKRVP_LAPTOP || mainboard/intel/glkrvp || None || ON BOARD EC ||
This option allows you to select the on board EC to use.
Select whether the board  has Intel EC or Chrome EC
 
||
|- bgcolor="#6699dd"
! align="left" | Menu: Debugging || || || ||
|- bgcolor="#eeeeee"
| DISABLE_UART_ON_TESTPADS || mainboard/intel/dcp847ske || bool || Disable UART on testpads ||
Serial output requires soldering to the testpad next to
NCT5577D pin 18 (txd) and gnd.
 
||
 
|- bgcolor="#eeeeee"
| VGA_BIOS_FILE || mainboard/intel/strago || string ||  ||
The C0 version of the video bios gets computed from this name
so that they can both be added.  Only the correct one for the
system will be run.
 
||
|- bgcolor="#eeeeee"
| VGA_BIOS_ID || mainboard/intel/strago || string ||  ||
The VGA_BIOS_ID for the C0 version of the video bios is hardcoded
in soc/intel/braswell/Makefile.inc as 8086,22b1
 
||
|- bgcolor="#eeeeee"
| BOARD_EMULATION_SPIKE_UCB_RISCV || mainboard/emulation/spike-riscv.name || bool || SPIKE ucb riscv ||
To run coreboot in spike:
* run "make" as usual
* util/riscv/make-spike-elf.sh build/coreboot.{rom,elf}
* spike -m1024 build/coreboot.elf
 
||
||
|- bgcolor="#eeeeee"
| HUDSON_LEGACY_FREE || mainboard/bap/ode_e21XX || bool || Select DDR3 clock ||
Select your preferenced DDR3 clock setting.
 
Note: This option changes the total power consumption.
 
If unsure, use DDR3-1333.
 
||
|- bgcolor="#eeeeee"
| HUDSON_LEGACY_FREE || mainboard/bap/ode_e20XX || bool || Select DDR3 clock ||
Select your preferred DDR3 clock setting.
 
Note: This option changes the total power consumption.
 
If unsure, use DDR3-1066.
 
||
|- bgcolor="#eeeeee"
| ENABLE_DP3_DAUGHTER_CARD_IN_J120 || mainboard/amd/lamar || bool || Use J120 as an additional graphics port ||
The PCI Express slot at J120 can be configured as an additional
DisplayPort connector using an adapter card from AMD or as a normal
PCI Express (x4) slot.
 
By default, the connector is configured as a PCI Express (x4) slot.
 
Select this option to enable the slot for use with one of AMD's
passive graphics port expander cards (only available from AMD).
 
||
|- bgcolor="#eeeeee"
| || || (comment) || || Slippy ||
|- bgcolor="#eeeeee"
| || || (comment) || || Octopus ||
|- bgcolor="#eeeeee"
| || || (comment) || || Auron ||
|- bgcolor="#eeeeee"
| || || (comment) || || Gru ||
|- bgcolor="#eeeeee"
| || || (comment) || || Cyan ||
|- bgcolor="#eeeeee"
| || || (comment) || || Reef ||
|- bgcolor="#eeeeee"
| || || (comment) || || Jecht ||
|- bgcolor="#eeeeee"
| || || (comment) || || Beltino ||
|- bgcolor="#eeeeee"
| || || (comment) || || Rambi ||
|- bgcolor="#eeeeee"
| || || (comment) || || Kahlee ||
|- bgcolor="#eeeeee"
| || || (comment) || || Poppy ||
|- bgcolor="#eeeeee"
| || || (comment) || || Zoombini ||
|- bgcolor="#eeeeee"
| || || (comment) || || Veyron ||
|- bgcolor="#eeeeee"
| || || (comment) || || Oak ||
|- bgcolor="#eeeeee"
| MAINBOARD_PART_NUMBER || mainboard/google/nyan_blaze || string || BCT boot media ||
Which boot media to configure the BCT for.
 
||
|- bgcolor="#eeeeee"
| NYAN_BLAZE_BCT_CFG_SPI || mainboard/google/nyan_blaze || bool || SPI ||
Configure the BCT for booting from SPI.
 
||
|- bgcolor="#eeeeee"
| NYAN_BLAZE_BCT_CFG_EMMC || mainboard/google/nyan_blaze || bool || eMMC ||
Configure the BCT for booting from eMMC.
 
||
|- bgcolor="#eeeeee"
| BOOT_DEVICE_SPI_FLASH_BUS || mainboard/google/nyan_blaze || int || SPI bus with boot media ROM ||
Which SPI bus the boot media is connected to.
 
||
|- bgcolor="#eeeeee"
| DISPLAY_SPD_DATA || mainboard/google/cyan || bool || Display Memory Serial Presence Detect Data ||
When enabled displays the memory configuration data.
 
||
|- bgcolor="#eeeeee"
| VGA_BIOS_FILE || mainboard/google/cyan || string ||  ||
The C0 version of the video bios gets computed from this name
so that they can both be added.  Only the correct one for the
system will be run.
 
||
|- bgcolor="#eeeeee"
| VGA_BIOS_ID || mainboard/google/cyan || string ||  ||
The VGA_BIOS_ID for the C0 version of the video bios is hardcoded
in soc/intel/braswell/Makefile.inc as 8086,22b1
 
||
|- bgcolor="#eeeeee"
| FMDFILE || mainboard/google/kahlee || string ||  ||
The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
but in some cases more complex setups are required.
When an fmd is specified, it overrides the default format.
 
||
|- bgcolor="#eeeeee"
| DRAM_SIZE_MB || mainboard/google/smaug || int || BCT boot media ||
Which boot media to configure the BCT for.
 
||
|- bgcolor="#eeeeee"
| SMAUG_BCT_CFG_SPI || mainboard/google/smaug || bool || SPI ||
Configure the BCT for booting from SPI.
 
||
|- bgcolor="#eeeeee"
| SMAUG_BCT_CFG_EMMC || mainboard/google/smaug || bool || eMMC ||
Configure the BCT for booting from eMMC.
 
||
|- bgcolor="#eeeeee"
| BOOT_DEVICE_SPI_FLASH_BUS || mainboard/google/smaug || int || SPI bus with boot media ROM ||
Which SPI bus the boot media is connected to.
 
||
|- bgcolor="#eeeeee"
| MAINBOARD_PART_NUMBER || mainboard/google/nyan_big || string || BCT boot media ||
Which boot media to configure the BCT for.
 
||
|- bgcolor="#eeeeee"
| NYAN_BIG_BCT_CFG_SPI || mainboard/google/nyan_big || bool || SPI ||
Configure the BCT for booting from SPI.
 
||
|- bgcolor="#eeeeee"
| NYAN_BIG_BCT_CFG_EMMC || mainboard/google/nyan_big || bool || eMMC ||
Configure the BCT for booting from eMMC.
 
||
|- bgcolor="#eeeeee"
| BOOT_DEVICE_SPI_FLASH_BUS || mainboard/google/nyan_big || int || SPI bus with boot media ROM ||
Which SPI bus the boot media is connected to.
 
||
|- bgcolor="#eeeeee"
| DRAM_SIZE_MB || mainboard/google/foster || int || BCT boot media ||
Which boot media to configure the BCT for.
 
||
|- bgcolor="#eeeeee"
| FOSTER_BCT_CFG_SPI || mainboard/google/foster || bool || SPI ||
Configure the BCT for booting from SPI.
 
||
|- bgcolor="#eeeeee"
| FOSTER_BCT_CFG_EMMC || mainboard/google/foster || bool || eMMC ||
Configure the BCT for booting from eMMC.
 
||
|- bgcolor="#eeeeee"
| BOOT_DEVICE_SPI_FLASH_BUS || mainboard/google/foster || int || SPI bus with boot media ROM ||
Which SPI bus the boot media is connected to.
 
||
|- bgcolor="#eeeeee"
| MAINBOARD_PART_NUMBER || mainboard/google/nyan || string || BCT boot media ||
Which boot media to configure the BCT for.
 
||
|- bgcolor="#eeeeee"
| NYAN_BCT_CFG_SPI || mainboard/google/nyan || bool || SPI ||
Configure the BCT for booting from SPI.
 
||
|- bgcolor="#eeeeee"
| NYAN_BCT_CFG_EMMC || mainboard/google/nyan || bool || eMMC ||
Configure the BCT for booting from eMMC.
 
||
|- bgcolor="#eeeeee"
| BOOT_DEVICE_SPI_FLASH_BUS || mainboard/google/nyan || int || SPI bus with boot media ROM ||
Which SPI bus the boot media is connected to.
 
||
|- bgcolor="#eeeeee"
| UART_FOR_CONSOLE || mainboard/adi/rcc-dff || int ||  ||
The Mohon Peak board uses COM2 (2f8) for the serial console.
 
||
|- bgcolor="#eeeeee"
| PAYLOAD_CONFIGFILE || mainboard/adi/rcc-dff || string ||  ||
The Avoton/Rangeley chip does not allow devices to write into the 0xe000
segment.  This means that USB/SATA devices will not work in SeaBIOS unless
we put the SeaBIOS buffer area down in the 0x9000 segment.
 
||
|- bgcolor="#eeeeee"
| BOARD_ASUS_F2A85_M_DDR3_VOLT_135 || mainboard/asus/f2a85-m || bool || 1.35V ||
Set DRR3 memory voltage to 1.35V
||
|- bgcolor="#eeeeee"
| BOARD_ASUS_F2A85_M_DDR3_VOLT_150 || mainboard/asus/f2a85-m || bool || 1.50V ||
Set DRR3 memory voltage to 1.50V
||
|- bgcolor="#eeeeee"
| BOARD_ASUS_F2A85_M_DDR3_VOLT_165 || mainboard/asus/f2a85-m || bool || 1.65V ||
Set DRR3 memory voltage to 1.65V
||
|- bgcolor="#eeeeee"
| BOARD_WINNET_G170 || mainboard/winnet/g170.name || bool || WinNET G170 (Neoware CA19, IGEL 2110) ||
G170 is a board manufactured by WinNET, used in thin clients including
HP Neoware CA19 and IGEL 2110.
 
||
 
||
|- bgcolor="#eeeeee"
| BMC_INFO_LOC || mainboard/scaleway/tagada || hex || BMC information location in flash ||
Location of BMC SERIAL information.
 
||
|- bgcolor="#eeeeee"
| NO_POST || mainboard/purism/librem_skl || int ||  ||
This platform does not have any way to see POST codes
so disable them by default.
 
||
|- bgcolor="#eeeeee"
| DRIVERS_PS2_KEYBOARD || mainboard/purism/librem_bdw || string ||  ||
Default PS/2 Keyboard to enabled on this board.
 
||
|- bgcolor="#eeeeee"
| DRIVERS_UART_8250IO || mainboard/purism/librem_bdw || string ||  ||
This platform does not have any way to get standard
serial output so disable it by default.
 
||
|- bgcolor="#eeeeee"
| NO_POST || mainboard/purism/librem_bdw || int ||  ||
This platform does not have any way to see POST codes
so disable them by default.
 
||
|- bgcolor="#eeeeee"
| || || (comment) || || was acquired by ADLINK ||
|- bgcolor="#eeeeee"
| ONBOARD_UARTS_RS485 || mainboard/lippert/spacerunner-lx || bool || Switch on-board serial ports to RS485 ||
If selected, both on-board serial ports will operate in RS485 mode
instead of RS232.
 
||
|- bgcolor="#eeeeee"
| ONBOARD_IDE_SLAVE || mainboard/lippert/spacerunner-lx || bool || Make on-board SSD act as Slave ||
If selected, the on-board SSD will act as IDE Slave instead of Master.
 
||
|- bgcolor="#eeeeee"
| BOARD_OLD_REVISION || mainboard/lippert/hurricane-lx || bool || Board is old pre-3.0 revision ||
Look on the bottom side for a number like 406-0001-30.  The last 2
digits state the PCB revision (3.0 in this example).  For 2.0 or older
boards choose Y, for 3.0 and newer say N.
 
Old revision boards need a jumper shorting the power button to
power on automatically.  You may enable the button only after this
jumper has been removed.  New revision boards are not restricted
in this way, and always have the power button enabled.
 
||
|- bgcolor="#eeeeee"
| ONBOARD_UARTS_RS485 || mainboard/lippert/hurricane-lx || bool || Switch on-board serial ports to RS485 ||
If selected, both on-board serial ports will operate in RS485 mode
instead of RS232.
 
||
|- bgcolor="#eeeeee"
| ONBOARD_UARTS_RS485 || mainboard/lippert/literunner-lx || bool || Switch on-board serial ports 1 & 2 to RS485 ||
If selected, the first two on-board serial ports will operate in RS485
mode instead of RS232.
 
||
|- bgcolor="#eeeeee"
| ONBOARD_IDE_SLAVE || mainboard/lippert/literunner-lx || bool || Make on-board CF socket act as Slave ||
If selected, the on-board Compact Flash card socket will act as IDE
Slave instead of Master.
 
||
|- bgcolor="#eeeeee"
| ONBOARD_UARTS_RS485 || mainboard/lippert/roadrunner-lx || bool || Switch on-board serial ports to RS485 ||
If selected, both on-board serial ports will operate in RS485 mode
instead of RS232.
 
||
|- bgcolor="#eeeeee"
| || || (comment) || || see under vendor LiPPERT ||
|- bgcolor="#eeeeee"
| || || (comment) || || WARNING: This mainboard uses LATE_CBMEM_INIT, which is deprecated ||
|- bgcolor="#eeeeee"
| BOARD_ROMSIZE_KB_65536 || mainboard || bool || ROM chip size ||
Select the size of the ROM chip you intend to flash coreboot on.
 
The build system will take care of creating a coreboot.rom file
of the matching size.
 
||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_64 || mainboard || bool || 64 KB ||
Choose this option if you have a 64 KB ROM chip.
 
||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_128 || mainboard || bool || 128 KB ||
Choose this option if you have a 128 KB ROM chip.
 
||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_256 || mainboard || bool || 256 KB ||
Choose this option if you have a 256 KB ROM chip.
 
||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_512 || mainboard || bool || 512 KB ||
Choose this option if you have a 512 KB ROM chip.
 
||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_1024 || mainboard || bool || 1024 KB (1 MB) ||
Choose this option if you have a 1024 KB (1 MB) ROM chip.
 
||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_2048 || mainboard || bool || 2048 KB (2 MB) ||
Choose this option if you have a 2048 KB (2 MB) ROM chip.
 
||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_4096 || mainboard || bool || 4096 KB (4 MB) ||
Choose this option if you have a 4096 KB (4 MB) ROM chip.
 
||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_8192 || mainboard || bool || 8192 KB (8 MB) ||
Choose this option if you have a 8192 KB (8 MB) ROM chip.
 
||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_10240 || mainboard || bool || 10240 KB (10 MB) ||
Choose this option if you have a 10240 KB (10 MB) ROM chip.
 
||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_12288 || mainboard || bool || 12288 KB (12 MB) ||
Choose this option if you have a 12288 KB (12 MB) ROM chip.
 
||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_16384 || mainboard || bool || 16384 KB (16 MB) ||
Choose this option if you have a 16384 KB (16 MB) ROM chip.
 
||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_32768 || mainboard || bool || 32768 KB (32 MB) ||
Choose this option if you have a 32768 KB (32 MB) ROM chip.
 
||
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_65536 || mainboard || bool || 65536 KB (64 MB) ||
Choose this option if you have a 65536 KB (64 MB) ROM chip.
 
||
|- bgcolor="#eeeeee"
| ENABLE_POWER_BUTTON || mainboard || bool || Enable the power button ||
The selected mainboard can optionally have the power button tied
to ground with a jumper so that the button appears to be
constantly depressed. If this option is enabled and the jumper is
installed then the board will turn on, but turn off again after a
short timeout, usually 4 seconds.
 
Select Y here if you have removed the jumper and want to use an
actual power button. Select N if you have the jumper installed.
 
||
|- bgcolor="#eeeeee"
| DEVICETREE || toplevel || string ||  ||
This symbol allows mainboards to select a different file under their
mainboard directory for the devicetree.cb file.  This allows the board
variants that need different devicetrees to be in the same directory.
 
Examples: "devicetree.variant.cb"
"variant/devicetree.cb"
 
||
|- bgcolor="#eeeeee"
| CBFS_SIZE || toplevel || hex || Size of CBFS filesystem in ROM ||
This is the part of the ROM actually managed by CBFS, located at the
end of the ROM (passed through cbfstool -o) on x86 and at at the start
of the ROM (passed through cbfstool -s) everywhere else. It defaults
to span the whole ROM on all but Intel systems that use an Intel Firmware
Descriptor.  It can be overridden to make coreboot live alongside other
components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
binaries.
 
||
|- bgcolor="#eeeeee"
| FMDFILE || toplevel || string || fmap description file in fmd format ||
The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
but in some cases more complex setups are required.
When an fmd is specified, it overrides the default format.
 
||
 
|- bgcolor="#eeeeee"
| CBFS_AUTOGEN_ATTRIBUTES || toplevel || bool ||  ||
If this option is selected, every file in cbfs which has a constraint
regarding position or alignment will get an additional file attribute
which describes this constraint.
 
||
|- bgcolor="#6699dd"
! align="left" | Menu: Chipset || || || ||
|- bgcolor="#eeeeee"
| || || (comment) || || SoC ||
|- bgcolor="#eeeeee"
| MAINBOARD_DO_DSI_INIT || soc/nvidia/tegra210 || bool || Use dsi graphics interface ||
Initialize dsi display
 
||
|- bgcolor="#eeeeee"
| MAINBOARD_DO_SOR_INIT || soc/nvidia/tegra210 || bool || Use dp graphics interface ||
Initialize dp display
 
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_TEGRA210_UARTA || soc/nvidia/tegra210 || bool || UARTA ||
Serial console on UART A.
 
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_TEGRA210_UARTB || soc/nvidia/tegra210 || bool || UARTB ||
Serial console on UART B.
 
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_TEGRA210_UARTC || soc/nvidia/tegra210 || bool || UARTC ||
Serial console on UART C.
 
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_TEGRA210_UARTD || soc/nvidia/tegra210 || bool || UARTD ||
Serial console on UART D.
 
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_TEGRA210_UARTE || soc/nvidia/tegra210 || bool || UARTE ||
Serial console on UART E.
 
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_TEGRA210_UART_ADDRESS || soc/nvidia/tegra210 || hex ||  ||
Map the UART names to the respective MMIO addres.
 
||
|- bgcolor="#eeeeee"
| BOOTROM_SDRAM_INIT || soc/nvidia/tegra210 || bool || SoC BootROM does SDRAM init with full BCT ||
Use during Foster LPDDR4 bringup.
 
||
|- bgcolor="#eeeeee"
| TRUSTZONE_CARVEOUT_SIZE_MB || soc/nvidia/tegra210 || hex || Size of Trust Zone region ||
Size of Trust Zone area in MiB to reserve in memory map.
 
||
|- bgcolor="#eeeeee"
| TTB_SIZE_MB || soc/nvidia/tegra210 || hex || Size of TTB ||
Maximum size of Translation Table Buffer in MiB.
 
||
|- bgcolor="#eeeeee"
| SEC_COMPONENT_SIZE_MB || soc/nvidia/tegra210 || hex || Size of resident EL3 components ||
Maximum size of resident EL3 components in MiB including BL31 and
Secure OS.
 
||
|- bgcolor="#eeeeee"
| HAVE_MTC || soc/nvidia/tegra210 || bool || Add external Memory controller Training Code binary ||
Select this option to add emc training firmware
 
||
|- bgcolor="#eeeeee"
| MTC_FILE || soc/nvidia/tegra210 || string || tegra mtc firmware filename ||
The filename of the mtc firmware
 
||
|- bgcolor="#eeeeee"
| MTC_DIRECTORY || soc/nvidia/tegra210 || string || Directory where MTC firmware file is located ||
Path to directory where MTC firmware file is located.
 
||
|- bgcolor="#eeeeee"
| MTC_ADDRESS || soc/nvidia/tegra210 || hex ||  ||
The DRAM location where MTC firmware to be loaded in. This location
needs to be consistent with the location defined in tegra_mtc.ld
 
||
|- bgcolor="#eeeeee"
| SOC_INTEL_APOLLOLAKE || soc/intel/apollolake || bool ||  ||
Intel Apollolake support
 
||
|- bgcolor="#eeeeee"
| SOC_INTEL_GLK || soc/intel/apollolake || bool ||  ||
Intel GLK support
 
||
|- bgcolor="#eeeeee"
| TPM_ON_FAST_SPI || soc/intel/apollolake || bool ||  ||
TPM part is conntected on Fast SPI interface, but the LPC MMIO
TPM transactions are decoded and serialized over the SPI interface.
 
||
|- bgcolor="#eeeeee"
| PCR_BASE_ADDRESS || soc/intel/apollolake || hex ||  ||
This option allows you to select MMIO Base Address of sideband bus.
 
||
|- bgcolor="#eeeeee"
| DCACHE_RAM_SIZE || soc/intel/apollolake || hex ||  ||
The size of the cache-as-ram region required during bootblock
and/or romstage.
 
||
|- bgcolor="#eeeeee"
| DCACHE_BSP_STACK_SIZE || soc/intel/apollolake || hex ||  ||
The amount of anticipated stack usage in CAR by bootblock and
other stages.
 
||
|- bgcolor="#eeeeee"
| ROMSTAGE_ADDR || soc/intel/apollolake || hex ||  ||
The base address (in CAR) where romstage should be linked
 
||
|- bgcolor="#eeeeee"
| VERSTAGE_ADDR || soc/intel/apollolake || hex ||  ||
The base address (in CAR) where verstage should be linked
 
||
|- bgcolor="#eeeeee"
| FSP_M_ADDR || soc/intel/apollolake || hex ||  ||
The address FSP-M will be relocated to during build time
 
||
|- bgcolor="#eeeeee"
| NEED_LBP2 || soc/intel/apollolake || bool || Write contents for logical boot partition 2. ||
Write the contents from a file into the logical boot partition 2
region defined by LBP2_FMAP_NAME.
 
||
|- bgcolor="#eeeeee"
| LBP2_FMAP_NAME || soc/intel/apollolake || string || Name of FMAP region to put logical boot partition 2 ||
Name of FMAP region to write logical boot partition 2 data.
 
||
|- bgcolor="#eeeeee"
| LBP2_FILE_NAME || soc/intel/apollolake || string || Path of file to write to logical boot partition 2 region ||
Name of file to store in the logical boot partition 2 region.
 
||
|- bgcolor="#eeeeee"
| NEED_IFWI || soc/intel/apollolake || bool || Write content into IFWI region ||
Write the content from a file into IFWI region defined by
IFWI_FMAP_NAME.
 
||
|- bgcolor="#eeeeee"
| IFWI_FMAP_NAME || soc/intel/apollolake || string || Name of FMAP region to pull IFWI into ||
Name of FMAP region to write IFWI.
 
||
|- bgcolor="#eeeeee"
| IFWI_FILE_NAME || soc/intel/apollolake || string || Path of file to write to IFWI region ||
Name of file to store in the IFWI region.
 
||
|- bgcolor="#eeeeee"
| NHLT_DMIC_1CH_16B || soc/intel/apollolake || bool ||  ||
Include DSP firmware settings for 1 channel 16B DMIC array.
 
||
|- bgcolor="#eeeeee"
| NHLT_DMIC_2CH_16B || soc/intel/apollolake || bool ||  ||
Include DSP firmware settings for 2 channel 16B DMIC array.
 
||
|- bgcolor="#eeeeee"
| NHLT_DMIC_4CH_16B || soc/intel/apollolake || bool ||  ||
Include DSP firmware settings for 4 channel 16B DMIC array.
 
||
|- bgcolor="#eeeeee"
| NHLT_MAX98357 || soc/intel/apollolake || bool ||  ||
Include DSP firmware settings for headset codec.
 
||
|- bgcolor="#eeeeee"
| NHLT_DA7219 || soc/intel/apollolake || bool ||  ||
Include DSP firmware settings for headset codec.
 
||
|- bgcolor="#eeeeee"
| NHLT_RT5682 || soc/intel/apollolake || bool ||  ||
Include DSP firmware settings for headset codec.
 
||
|- bgcolor="#eeeeee"
| NHLT_RT5682 || soc/intel/apollolake || bool || Cache-as-ram implementation ||
This option allows you to select how cache-as-ram (CAR) is set up.
 
||
|- bgcolor="#eeeeee"
| CAR_NEM || soc/intel/apollolake || bool || Non-evict mode ||
Traditionally, CAR is set up by using Non-Evict mode. This method
does not allow CAR and cache to co-exist, because cache fills are
block in NEM mode.
 
||
|- bgcolor="#eeeeee"
| CAR_CQOS || soc/intel/apollolake || bool || Cache Quality of Service ||
Cache Quality of Service allows more fine-grained control of cache
usage. As result, it is possible to set up portion of L2 cache for
CAR and use remainder for actual caching.
 
||
|- bgcolor="#eeeeee"
| USE_APOLLOLAKE_FSP_CAR || soc/intel/apollolake || bool || Use FSP CAR ||
Use FSP APIs to initialize & tear down the Cache-As-Ram.
 
||
|- bgcolor="#eeeeee"
| APL_SKIP_SET_POWER_LIMITS || soc/intel/apollolake || bool ||  ||
Some Apollo Lake mainboards do not need the Running Average Power
Limits (RAPL) algorithm for a constant power management.
Set this config option to skip the RAPL configuration.
 
||
|- bgcolor="#eeeeee"
| SOC_ESPI || soc/intel/apollolake || bool ||  ||
Use eSPI bus instead of LPC
 
||
|- bgcolor="#eeeeee"
| SOC_INTEL_BAYTRAIL || soc/intel/baytrail || bool ||  ||
Bay Trail M/D part support.
 
||
|- bgcolor="#eeeeee"
| HAVE_MRC || soc/intel/baytrail || bool || Add a Memory Reference Code binary ||
Select this option to add a blob containing
memory reference code.
Note: Without this binary coreboot will not work
 
||
|- bgcolor="#eeeeee"
| MRC_FILE || soc/intel/baytrail || string || Intel memory refeference code path and filename ||
The path and filename of the file to use as System Agent
binary. Note that this points to the sandybridge binary file
which is will not work, but it serves its purpose to do builds.
 
||
|- bgcolor="#eeeeee"
| DCACHE_RAM_SIZE || soc/intel/baytrail || hex ||  ||
The size of the cache-as-ram region required during bootblock
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
must add up to a power of 2.
 
||
|- bgcolor="#eeeeee"
| DCACHE_RAM_MRC_VAR_SIZE || soc/intel/baytrail || hex ||  ||
The amount of cache-as-ram region required by the reference code.
 
||
|- bgcolor="#eeeeee"
| RESET_ON_INVALID_RAMSTAGE_CACHE || soc/intel/baytrail || bool || Reset the system on S3 wake when ramstage cache invalid. ||
The baytrail romstage code caches the loaded ramstage program
in SMM space. On S3 wake the romstage will copy over a fresh
ramstage that was cached in the SMM space. This option determines
the action to take when the ramstage cache is invalid. If selected
the system will reset otherwise the ramstage will be reloaded from
cbfs.
 
||
|- bgcolor="#eeeeee"
| ENABLE_BUILTIN_COM1 || soc/intel/baytrail || bool || Enable builtin COM1 Serial Port ||
The PMC has a legacy COM1 serial port. Choose this option to
configure the pads and enable it. This serial port can be used for
the debug console.
 
||
|- bgcolor="#eeeeee"
| HAVE_REFCODE_BLOB || soc/intel/baytrail || bool || An external reference code blob should be put into cbfs. ||
The reference code blob will be placed into cbfs.
 
||
|- bgcolor="#eeeeee"
| REFCODE_BLOB_FILE || soc/intel/baytrail || string || Path and filename to reference code blob. ||
The path and filename to the file to be added to cbfs.
 
||
|- bgcolor="#eeeeee"
| SOC_INTEL_BRASWELL || soc/intel/braswell || bool ||  ||
Braswell M/D part support.
 
||
|- bgcolor="#eeeeee"
| DCACHE_RAM_SIZE || soc/intel/braswell || hex ||  ||
The size of the cache-as-ram region required during bootblock
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
must add up to a power of 2.
 
||
|- bgcolor="#eeeeee"
| RESET_ON_INVALID_RAMSTAGE_CACHE || soc/intel/braswell || bool || Reset the system on S3 wake when ramstage cache invalid. ||
The haswell romstage code caches the loaded ramstage program
in SMM space. On S3 wake the romstage will copy over a fresh
ramstage that was cached in the SMM space. This option determines
the action to take when the ramstage cache is invalid. If selected
the system will reset otherwise the ramstage will be reloaded from
cbfs.
 
||
|- bgcolor="#eeeeee"
| ENABLE_BUILTIN_COM1 || soc/intel/braswell || bool || Enable builtin COM1 Serial Port ||
The PMC has a legacy COM1 serial port. Choose this option to
configure the pads and enable it. This serial port can be used for
the debug console.
 
||
|- bgcolor="#eeeeee"
| SOC_INTEL_BROADWELL || soc/intel/broadwell || bool ||  ||
Intel Broadwell and Haswell ULT support.
 
||
|- bgcolor="#eeeeee"
| DCACHE_RAM_SIZE || soc/intel/broadwell || hex ||  ||
The size of the cache-as-ram region required during bootblock
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
must add up to a power of 2.
 
||
|- bgcolor="#eeeeee"
| DCACHE_RAM_MRC_VAR_SIZE || soc/intel/broadwell || hex ||  ||
The amount of cache-as-ram region required by the reference code.
 
||
|- bgcolor="#eeeeee"
| HAVE_MRC || soc/intel/broadwell || bool || Add a Memory Reference Code binary ||
Select this option to add a Memory Reference Code binary to
the resulting coreboot image.
 
Note: Without this binary coreboot will not work
 
||
|- bgcolor="#eeeeee"
| MRC_FILE || soc/intel/broadwell || string || Intel Memory Reference Code path and filename ||
The filename of the file to use as Memory Reference Code binary.
 
||
|- bgcolor="#eeeeee"
| PRE_GRAPHICS_DELAY || soc/intel/broadwell || int || Graphics initialization delay in ms ||
On some systems, coreboot boots so fast that connected monitors
(mostly TVs) won't be able to wake up fast enough to talk to the
VBIOS. On those systems we need to wait for a bit before executing
the VBIOS.
 
||
|- bgcolor="#eeeeee"
| RESET_ON_INVALID_RAMSTAGE_CACHE || soc/intel/broadwell || bool || Reset the system on S3 wake when ramstage cache invalid. ||
The romstage code caches the loaded ramstage program in SMM space.
On S3 wake the romstage will copy over a fresh ramstage that was
cached in the SMM space. This option determines the action to take
when the ramstage cache is invalid. If selected the system will
reset otherwise the ramstage will be reloaded from cbfs.
 
||
|- bgcolor="#eeeeee"
| SERIRQ_CONTINUOUS_MODE || soc/intel/broadwell || bool ||  ||
If you set this option to y, the serial IRQ machine will be
operated in continuous mode.
 
||
|- bgcolor="#eeeeee"
| HAVE_REFCODE_BLOB || soc/intel/broadwell || bool || An external reference code blob should be put into cbfs. ||
The reference code blob will be placed into cbfs.


This page shows two representations of the same data:
||
|- bgcolor="#eeeeee"
| REFCODE_BLOB_FILE || soc/intel/broadwell || string || Path and filename to reference code blob. ||
The path and filename to the file to be added to cbfs.
 
||
|- bgcolor="#eeeeee"
| SOC_INTEL_CANNONLAKE || soc/intel/cannonlake || bool ||  ||
Intel Cannonlake support


First a list of all mainboards supported by coreboot (current within
||
one hour) ordered by category. For each mainboard the table shows the
|- bgcolor="#eeeeee"
latest user-contributed report of a successful boot on the device.
| UART_FOR_CONSOLE || soc/intel/cannonlake || int || Index for LPSS UART port to use for console ||
Index for LPSS UART port to use for console:
0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2


After that, the page provides a time-ordered list of these contributed
||
reports, with the newest report first.
|- bgcolor="#eeeeee"
| DCACHE_RAM_SIZE || soc/intel/cannonlake || int ||  ||
The size of the cache-as-ram region required during bootblock
and/or romstage.


Boards without such reports may boot or there may be some maintenance
||
required. The reports contain the coreboot configuration and precise commit
|- bgcolor="#eeeeee"
id, so it is possible to reproduce the build.
| DCACHE_BSP_STACK_SIZE || soc/intel/cannonlake || hex ||  ||
The amount of anticipated stack usage in CAR by bootblock and
other stages.


We encourage developers and users to contribute reports so we know which
||
devices are well-tested.  We have
|- bgcolor="#eeeeee"
[https://review.coreboot.org/gitweb/cgit/coreboot.git/tree/util/board_status a tool in the coreboot repository]
| NHLT_DMIC_1CH_16B || soc/intel/cannonlake || bool || ||
to make contributing easy. The data resides in the
Include DSP firmware settings for 1 channel 16B DMIC array.
[https://review.coreboot.org/gitweb/cgit/board-status.git/ board status repository].
Contributing requires an account on review.coreboot.org


Sometimes the same board is sold under different names, we've tried to
||
list all known names but some names might be missing.
|- bgcolor="#eeeeee"
| NHLT_DMIC_2CH_16B || soc/intel/cannonlake || bool ||  ||
Include DSP firmware settings for 2 channel 16B DMIC array.


If the board is not found in the coreboot's source code, there might
||
be some form of support that is not ready yet for inclusion in coreboot,
|- bgcolor="#eeeeee"
usually people willing to send their patches to coreboot goes through
| NHLT_DMIC_4CH_16B || soc/intel/cannonlake || bool ||  ||
[https://review.coreboot.org gerrit], so looking there could find some
Include DSP firmware settings for 4 channel 16B DMIC array.
code for boards that are not yet merged.


= Vendor trees =
||
Some vendors have their own coreboot trees/fork, like for instance:
|- bgcolor="#eeeeee"
* [http://git.chromium.org/gitweb/?p=chromiumos/third_party/coreboot.git;a=summary chrome/chromium's tree]
| NHLT_MAX98357 || soc/intel/cannonlake || bool ||  ||
== Motherboards supported in coreboot ==
Include DSP firmware settings for headset codec.


{| border="0" style="font-size: smaller"
||
|- bgcolor="#6699ff"
|- bgcolor="#eeeeee"
! align="left" | Vendor
| NHLT_MAX98373 || soc/intel/cannonlake || bool ||  ||
! align="left" | Mainboard
Include DSP firmware settings for headset codec.
! align="left" | Latest known good
 
! align="left" | Northbridge
||
! align="left" | Southbridge
|- bgcolor="#eeeeee"
! align="left" | Super I/O
| NHLT_DA7219 || soc/intel/cannonlake || bool ||  ||
! align="left" | CPU
Include DSP firmware settings for headset codec.
! align="left" | Socket
 
! align="left" | <span title="ROM chip package">ROM&nbsp;<sup>1</sup></span>
||
! align="left" | <span title="ROM chip protocol">P&nbsp;<sup>2</sup></span>
|- bgcolor="#eeeeee"
! align="left" | <span title="ROM chip socketed?">S&nbsp;<sup>3</sup></span>
| PCR_BASE_ADDRESS || soc/intel/cannonlake || hex ||  ||
! align="left" | <span title="Board supported by flashrom?">F&nbsp;<sup>4</sup></span>
This option allows you to select MMIO Base Address of sideband bus.
! align="left" | <span title="Vendor Cooperation Score">VCS<sup>5</sup></span>
 
|- bgcolor="#6699ff"
||
| colspan="13" | <h4>Laptops</h4>
|- bgcolor="#eeeeee"
| STACK_SIZE || soc/intel/cannonlake || hex || Cache-as-ram implementation ||
This option allows you to select how cache-as-ram (CAR) is set up.
 
||
|- bgcolor="#eeeeee"
| USE_CANNONLAKE_CAR_NEM_ENHANCED || soc/intel/cannonlake || bool || Enhanced Non-evict mode ||
A current limitation of NEM (Non-Evict mode) is that code and data
sizes are derived from the requirement to not write out any modified
cache line. With NEM, if there is no physical memory behind the
cached area, the modified data will be lost and NEM results will be
inconsistent. ENHANCED NEM guarantees that modified data is always
kept in cache while clean data is replaced.
 
||
|- bgcolor="#eeeeee"
| USE_CANNONLAKE_FSP_CAR || soc/intel/cannonlake || bool || Use FSP CAR ||
Use FSP APIs to initialize and tear down the Cache-As-Ram.
 
||
|- bgcolor="#eeeeee"
| SOC_INTEL_DENVERTON_NS || soc/intel/denverton_ns || bool ||  ||
Intel Denverton-NS SoC support
 
||
|- bgcolor="#eeeeee"
| FSP_T_ADDR || soc/intel/denverton_ns || hex || Intel FSP-T (temp ram init) binary location ||
The memory location of the Intel FSP-T binary for this platform.
 
||
|- bgcolor="#eeeeee"
| FSP_M_ADDR || soc/intel/denverton_ns || hex || Intel FSP-M (memory init) binary location ||
The memory location of the Intel FSP-M binary for this platform.
 
||
|- bgcolor="#eeeeee"
| FSP_S_ADDR || soc/intel/denverton_ns || hex || Intel FSP-S (silicon init) binary location ||
The memory location of the Intel FSP-S binary for this platform.
 
||
|- bgcolor="#eeeeee"
| PCR_BASE_ADDRESS || soc/intel/denverton_ns || hex ||  ||
This option allows you to select MMIO Base Address of sideband bus.
 
||
|- bgcolor="#eeeeee"
| IQAT_MEMORY_REGION_SIZE || soc/intel/denverton_ns || hex ||  ||
Do not change this value
 
||
|- bgcolor="#eeeeee"
| NON_LEGACY_UART_MODE || soc/intel/denverton_ns || bool || Non Legacy Mode ||
Disable legacy UART mode
 
||
|- bgcolor="#eeeeee"
| LEGACY_UART_MODE || soc/intel/denverton_ns || bool || Legacy Mode ||
Enable legacy UART mode
||
|- bgcolor="#eeeeee"
| DENVERTON_NS_CAR_NEM_ENHANCED || soc/intel/denverton_ns || bool || Enhanced Non-evict mode ||
A current limitation of NEM (Non-Evict mode) is that code and data sizes
are derived from the requirement to not write out any modified cache line.
With NEM, if there is no physical memory behind the cached area,
the modified data will be lost and NEM results will be inconsistent.
ENHANCED NEM guarantees that modified data is always
kept in cache while clean data is replaced.
 
||
|- bgcolor="#eeeeee"
| SOC_INTEL_FSP_BAYTRAIL || soc/intel/fsp_baytrail || bool ||  ||
Bay Trail I part support using the Intel FSP.
 
||
|- bgcolor="#eeeeee"
| SMM_TSEG_SIZE || soc/intel/fsp_baytrail || hex ||  ||
This is set by the FSP
 
||
|- bgcolor="#eeeeee"
| VGA_BIOS_ID || soc/intel/fsp_baytrail || string ||  ||
This is the default PCI ID for the Bay Trail graphics
devices.  This string names the vbios ROM in cbfs.
 
||
|- bgcolor="#eeeeee"
| ENABLE_BUILTIN_COM1 || soc/intel/fsp_baytrail || bool || Enable built-in legacy Serial Port ||
The Baytrail SOC has one legacy serial port. Choose this option to
configure the pads and enable it. This serial port can be used for
the debug console.
 
||
|- bgcolor="#eeeeee"
| FSP_FILE || soc/intel/fsp_baytrail/fsp || string ||  ||
The path and filename of the Intel FSP binary for this platform.
 
||
|- bgcolor="#eeeeee"
| FSP_LOC || soc/intel/fsp_baytrail/fsp || hex ||  ||
The location in CBFS that the FSP is located. This must match the
value that is set in the FSP binary.  If the FSP needs to be moved,
rebase the FSP with Intel's BCT (tool).
 
The Bay Trail FSP is built with a preferred base address of
0xFFFC0000.
 
||
 
||
|- bgcolor="#eeeeee"
| SOC_INTEL_FSP_BROADWELL_DE || soc/intel/fsp_broadwell_de || bool ||  ||
Broadwell-DE support using the Intel FSP.
 
||
|- bgcolor="#eeeeee"
| INTEGRATED_UART || soc/intel/fsp_broadwell_de || bool || Integrated UART ports ||
Use Broadwell-DE Integrated UART ports @3F8h and 2F8h.
 
||
|- bgcolor="#eeeeee"
| SERIRQ_CONTINUOUS_MODE || soc/intel/fsp_broadwell_de || bool ||  ||
If you set this option to y, the serial IRQ machine will be
operated in continuous mode.
 
||
|- bgcolor="#eeeeee"
| FSP_FILE || soc/intel/fsp_broadwell_de/fsp || string ||  ||
The path and filename of the Intel FSP binary for this platform.
 
||
|- bgcolor="#eeeeee"
| FSP_LOC || soc/intel/fsp_broadwell_de/fsp || hex ||  ||
The location in CBFS that the FSP is located. This must match the
value that is set in the FSP binary.  If the FSP needs to be moved,
rebase the FSP with Intel's BCT (tool).
 
The Broadwell-DE FSP is built with a preferred base address of
0xffeb0000.
 
||
|- bgcolor="#eeeeee"
| DCACHE_RAM_BASE || soc/intel/fsp_broadwell_de/fsp || hex ||  ||
This address needs to match the setup performed inside FSP.
On Broadwell-DE the FSP allocates temporary RAM starting at 0xfe100000.
 
||
|- bgcolor="#eeeeee"
| DCACHE_RAM_SIZE || soc/intel/fsp_broadwell_de/fsp || hex ||  ||
The DCACHE is shared between FSP itself and the rest of the coreboot
stages. A size of 0x8000 works fine while providing enough space for
features like VBOOT in verstage. Further increase to a power of two
aligned value leads to errors in FSP.
 
||
|- bgcolor="#eeeeee"
| FSP_MEMORY_DOWN || soc/intel/fsp_broadwell_de/fsp || bool || Enable Memory Down ||
Load SPD data from ROM instead of trying to read from SMBus.
 
If the platform has DIMM sockets, say N. If memory is down, say Y and
supply the appropriate SPD data for each Channel/DIMM.
 
||
|- bgcolor="#eeeeee"
| FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT || soc/intel/fsp_broadwell_de/fsp || bool || Channel 0, DIMM 0 Present ||
Select Y if Channel 0, DIMM 0 is present.
 
||
|- bgcolor="#eeeeee"
| FSP_MEMORY_DOWN_CH0DIMM0_SPD_FILE || soc/intel/fsp_broadwell_de/fsp || string || Channel 0, DIMM 0 SPD File ||
Path to the file which contains the SPD data for Channel 0, DIMM 0.
 
||
|- bgcolor="#eeeeee"
| FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT || soc/intel/fsp_broadwell_de/fsp || bool || Channel 0, DIMM 1 Present ||
Select Y if Channel 0, DIMM 1 is present.
 
||
|- bgcolor="#eeeeee"
| FSP_MEMORY_DOWN_CH0DIMM1_SPD_FILE || soc/intel/fsp_broadwell_de/fsp || string || Channel 0, DIMM 1 SPD File ||
Path to the file which contains the SPD data for Channel 0, DIMM 1.
 
||
|- bgcolor="#eeeeee"
| FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT || soc/intel/fsp_broadwell_de/fsp || bool || Channel 1, DIMM 0 Present ||
Select Y if Channel 1, DIMM 0 is present.
 
||
|- bgcolor="#eeeeee"
| FSP_MEMORY_DOWN_CH1DIMM0_SPD_FILE || soc/intel/fsp_broadwell_de/fsp || string || Channel 1, DIMM 0 SPD File ||
Path to the file which contains the SPD data for Channel 1, DIMM 0.
 
||
|- bgcolor="#eeeeee"
| FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT || soc/intel/fsp_broadwell_de/fsp || bool || Channel 1, DIMM 1 Present ||
Select Y if Channel 1, DIMM 1 is present.
 
||
|- bgcolor="#eeeeee"
| FSP_MEMORY_DOWN_CH1DIMM1_SPD_FILE || soc/intel/fsp_broadwell_de/fsp || string || Channel 1, DIMM 1 SPD File ||
Path to the file which contains the SPD data for Channel 1, DIMM 1.
 
||
|- bgcolor="#eeeeee"
| FSP_HYPERTHREADING || soc/intel/fsp_broadwell_de/fsp || bool || Enable Hyper-Threading ||
Enable Intel(r) Hyper-Threading Technology for the Broadwell-DE SoC.
 
||
|- bgcolor="#eeeeee"
| FSP_EHCI1_ENABLE || soc/intel/fsp_broadwell_de/fsp || bool || EHCI1 Enable ||
Enable EHCI controller 1
 
||
|- bgcolor="#eeeeee"
| FSP_EHCI2_ENABLE || soc/intel/fsp_broadwell_de/fsp || bool || EHCI2 Enable ||
Enable EHCI controller 2
 
||
 
||
|- bgcolor="#eeeeee"
| SOC_INTEL_QUARK || soc/intel/quark || bool ||  ||
Intel Quark support
 
||
|- bgcolor="#eeeeee"
| ENABLE_BUILTIN_HSUART0 || soc/intel/quark || bool || Enable built-in HSUART0 ||
The Quark SoC has two HSUART. Choose this option to configure the pads
and enable HSUART0, which can be used for the debug console.
 
||
|- bgcolor="#eeeeee"
| ENABLE_BUILTIN_HSUART1 || soc/intel/quark || bool || Enable built-in HSUART1 ||
The Quark SoC has two HSUART. Choose this option to configure the pads
and enable HSUART1, which can be used for the debug console.
 
||
|- bgcolor="#eeeeee"
| TTYS0_BASE || soc/intel/quark || hex || HSUART Base Address ||
Memory mapped MMIO of HSUART.
 
||
|- bgcolor="#eeeeee"
| ENABLE_DEBUG_LED || soc/intel/quark || bool ||  ||
Enable the use of the SD LED for early debugging before serial output
is available.  Setting this LED indicates that control has reached the
desired check point.
 
||
|- bgcolor="#eeeeee"
| ENABLE_DEBUG_LED_ESRAM || soc/intel/quark || bool || SD LED indicates ESRAM initialized ||
Indicate that ESRAM has been successfully initialized.  If the SD LED
does not light then the ESRAM initialization needs to be debugged.
 
||
|- bgcolor="#eeeeee"
| ENABLE_DEBUG_LED_FINDFSP || soc/intel/quark || bool || SD LED indicates fsp.bin file was found ||
Indicate that fsp.bin was found.  If the SD LED does not light then
the code between ESRAM initialization through find_fsp needs to
debugged.  Start by verifying that the correct fsp.bin is in the
image.
 
||
|- bgcolor="#eeeeee"
| ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY || soc/intel/quark || bool || SD LED indicates bootblock.c successfully entered ||
Indicate that bootblock_c_entry was entered.  If the SD LED does not
light then debug the code between ESRAM and bootblock_c_entry.  For
FSP 1.1, use ENABLE_DEBUG_LED_FINDFSP to split this code.
 
||
|- bgcolor="#eeeeee"
| ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY || soc/intel/quark || bool || SD LED indicates bootblock_soc_early_init successfully entered ||
Indicate that bootblock_soc_early_init was entered.  If the SD LED
does not light then debug the code in bootblock_main_with_timestamp.
 
||
|- bgcolor="#eeeeee"
| ENABLE_DEBUG_LED_SOC_EARLY_INIT_EXIT || soc/intel/quark || bool || SD LED indicates bootblock_soc_early_init successfully exited ||
Indicate that bootblock_soc_early_init exited.  If the SD LED does not
light then debug the scripts in bootblock_soc_early_init.
 
||
|- bgcolor="#eeeeee"
| ENABLE_DEBUG_LED_SOC_INIT_ENTRY || soc/intel/quark || bool || SD LED indicates bootblock_soc_init successfully entered ||
Indicate that bootblock_soc_init was entered.  If the SD LED does not
light then debug the code in bootblock_mainboard_early_init and
console_init.  If the SD LED does light but there is no serial then
debug the serial port configuration and initialization.
 
||
|- bgcolor="#eeeeee"
| DISPLAY_ESRAM_LAYOUT || soc/intel/quark || bool || Display ESRAM layout ||
Select this option to display coreboot's use of ESRAM.
 
||
|- bgcolor="#eeeeee"
| CBFS_SIZE || soc/intel/quark || hex ||  ||
Specify the size of the coreboot file system in the read-only (recovery)
portion of the flash part.  On Quark systems the firmware image stores
more than just coreboot, including:
- The chipset microcode (RMU) binary file located at 0xFFF00000
- Intel Trusted Execution Engine firmware
 
||
|- bgcolor="#eeeeee"
| ADD_FSP_RAW_BIN || soc/intel/quark || bool || Add the Intel FSP binary to the flash image without relocation ||
Select this option to add an Intel FSP binary to
the resulting coreboot image.
 
Note: Without this binary, coreboot builds relying on the FSP
will not boot
 
||
|- bgcolor="#eeeeee"
| FSP_FILE || soc/intel/quark || string || Intel FSP binary path and filename ||
The path and filename of the Intel FSP binary for this platform.
 
||
|- bgcolor="#eeeeee"
| FSP_LOC || soc/intel/quark || hex ||  ||
The location in CBFS that the FSP is located. This must match the
value that is set in the FSP binary.  If the FSP needs to be moved,
rebase the FSP with Intel's BCT (tool).
 
||
|- bgcolor="#eeeeee"
| FSP_ESRAM_LOC || soc/intel/quark || hex ||  ||
The location in ESRAM where a copy of the FSP binary is placed.
 
||
|- bgcolor="#eeeeee"
| RELOCATE_FSP_INTO_DRAM || soc/intel/quark || bool || Relocate FSP into DRAM ||
Relocate the FSP binary into DRAM before the call to SiliconInit.
 
||
|- bgcolor="#eeeeee"
| ADD_RMU_FILE || soc/intel/quark || bool || Should the RMU binary be added to the flash image? ||
The RMU file is required to get the chip out of reset.
 
||
|- bgcolor="#eeeeee"
| RMU_FILE || soc/intel/quark || string ||  ||
The path and filename of the Intel Quark RMU binary.
 
||
|- bgcolor="#eeeeee"
| RMU_LOC || soc/intel/quark || hex ||  ||
The location in CBFS that the RMU is located. It must match the
strap-determined base address.
 
||
|- bgcolor="#eeeeee"
| STORAGE_TEST || soc/intel/quark || bool || Test SD/MMC/eMMC card or device access ||
Read block 0 from each parition of the storage device.  User
must also enable one or both of COMMONLIB_STORAGE_SD or
COMMONLIB_STORAGE_MMC.
 
||
|- bgcolor="#eeeeee"
| I2C_DEBUG || soc/intel/quark || bool || Enable I2C debugging ||
Display the I2C segments and controller errors
 
||
|- bgcolor="#eeeeee"
| SOC_INTEL_SKYLAKE || soc/intel/skylake || bool ||  ||
Intel Skylake support
 
||
|- bgcolor="#eeeeee"
| SOC_INTEL_KABYLAKE || soc/intel/skylake || bool ||  ||
Intel Kabylake support
 
||
|- bgcolor="#eeeeee"
| DCACHE_RAM_SIZE || soc/intel/skylake || hex ||  ||
The size of the cache-as-ram region required during bootblock
and/or romstage.
 
||
|- bgcolor="#eeeeee"
| DCACHE_BSP_STACK_SIZE || soc/intel/skylake || hex ||  ||
The amount of anticipated stack usage in CAR by bootblock and
other stages.
 
||
|- bgcolor="#eeeeee"
| EXCLUDE_NATIVE_SD_INTERFACE || soc/intel/skylake || bool ||  ||
If you set this option to n, will not use native SD controller.
 
||
|- bgcolor="#eeeeee"
| PCR_BASE_ADDRESS || soc/intel/skylake || hex ||  ||
This option allows you to select MMIO Base Address of sideband bus.
 
||
|- bgcolor="#eeeeee"
| SERIRQ_CONTINUOUS_MODE || soc/intel/skylake || bool ||  ||
If you set this option to y, the serial IRQ machine will be
operated in continuous mode.
 
||
|- bgcolor="#eeeeee"
| UART_FOR_CONSOLE || soc/intel/skylake || int || Index for LPSS UART port to use for console ||
Index for LPSS UART port to use for console:
0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
 
||
|- bgcolor="#eeeeee"
| SKYLAKE_SOC_PCH_H || soc/intel/skylake || bool ||  ||
Choose this option if you have a PCH-H chipset.
 
||
|- bgcolor="#eeeeee"
| NHLT_DMIC_2CH || soc/intel/skylake || bool ||  ||
Include DSP firmware settings for 2 channel DMIC array.
 
||
|- bgcolor="#eeeeee"
| NHLT_DMIC_4CH || soc/intel/skylake || bool ||  ||
Include DSP firmware settings for 4 channel DMIC array.
 
||
|- bgcolor="#eeeeee"
| NHLT_NAU88L25 || soc/intel/skylake || bool ||  ||
Include DSP firmware settings for nau88l25 headset codec.
 
||
|- bgcolor="#eeeeee"
| NHLT_MAX98357 || soc/intel/skylake || bool ||  ||
Include DSP firmware settings for max98357 amplifier.
 
||
|- bgcolor="#eeeeee"
| NHLT_MAX98373 || soc/intel/skylake || bool ||  ||
Include DSP firmware settings for max98373 amplifier.
 
||
|- bgcolor="#eeeeee"
| NHLT_SSM4567 || soc/intel/skylake || bool ||  ||
Include DSP firmware settings for ssm4567 smart amplifier.
 
||
|- bgcolor="#eeeeee"
| NHLT_RT5514 || soc/intel/skylake || bool ||  ||
Include DSP firmware settings for rt5514 DSP.
 
||
|- bgcolor="#eeeeee"
| NHLT_RT5663 || soc/intel/skylake || bool ||  ||
Include DSP firmware settings for rt5663 headset codec.
 
||
|- bgcolor="#eeeeee"
| NHLT_MAX98927 || soc/intel/skylake || bool ||  ||
Include DSP firmware settings for max98927 amplifier.
 
||
|- bgcolor="#eeeeee"
| NHLT_DA7219 || soc/intel/skylake || bool ||  ||
Include DSP firmware settings for DA7219 headset codec.
 
||
|- bgcolor="#eeeeee"
| NHLT_DA7219 || soc/intel/skylake || bool || Cache-as-ram implementation ||
This option allows you to select how cache-as-ram (CAR) is set up.
 
||
|- bgcolor="#eeeeee"
| USE_SKYLAKE_CAR_NEM_ENHANCED || soc/intel/skylake || bool || Enhanced Non-evict mode ||
A current limitation of NEM (Non-Evict mode) is that code and data
sizes are derived from the requirement to not write out any modified
cache line. With NEM, if there is no physical memory behind the
cached area, the modified data will be lost and NEM results will be
inconsistent. ENHANCED NEM guarantees that modified data is always
kept in cache while clean data is replaced.
 
||
|- bgcolor="#eeeeee"
| USE_SKYLAKE_FSP_CAR || soc/intel/skylake || bool || Use FSP CAR ||
Use FSP APIs to initialize and tear down the Cache-As-Ram.
 
||
|- bgcolor="#eeeeee"
| SKIP_FSP_CAR || soc/intel/skylake || bool || Skip cache as RAM setup in FSP ||
Skip Cache as RAM setup in FSP.
 
||
|- bgcolor="#eeeeee"
| NO_FADT_8042 || soc/intel/skylake || bool ||  ||
Choose this option if you want to disable 8042 Keyboard
 
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON || soc/intel/common || bool ||  ||
common code for Intel SOCs
 
||
|- bgcolor="#eeeeee"
| || || (comment) || || Intel SoC Common Code ||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK || soc/intel/common/block || bool ||  ||
SoC driver for intel common IP code
 
||
|- bgcolor="#eeeeee"
| || || (comment) || || Intel SoC Common IP Code ||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_TIMER || soc/intel/common/block/timer || bool ||  ||
Intel Processor common TIMER support
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_XDCI || soc/intel/common/block/xdci || bool ||  ||
Intel Processor common XDCI support
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_SCS || soc/intel/common/block/scs || bool ||  ||
Intel Processor common storage and communication subsystem support
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_SATA || soc/intel/common/block/sata || bool ||  ||
Intel Processor common SATA support
 
||
|- bgcolor="#eeeeee"
| SOC_AHCI_PORT_IMPLEMENTED_INVERT || soc/intel/common/block/sata || bool ||  ||
SATA PCI configuration space offset 0x92 Port
implement register bit 0-2 represents respective
SATA port enable status as in 0 = Disable; 1 = Enable.
If this option is selected then port enable status will be
inverted as in 0 = Enable; 1 = Disable.
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_LPC || soc/intel/common/block/lpc || bool ||  ||
Use common LPC code for platform. Only soc specific code needs to
be implemented as per requirement.
 
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE || soc/intel/common/block/lpc || bool ||  ||
By default COMA range to LPC is enable. COMB range to LPC is optional
and should select based on platform dedicated selection.
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_SPI || soc/intel/common/block/spi || bool ||  ||
Intel Processor common SPI support
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_P2SB || soc/intel/common/block/p2sb || bool ||  ||
Intel Processor common P2SB driver
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_SMM || soc/intel/common/block/smm || bool ||  ||
Intel Processor common SMM support
 
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP || soc/intel/common/block/smm || bool ||  ||
Intel Processor trap flag if it is supported
 
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS || soc/intel/common/block/smm || int ||  ||
Time in milliseconds that SLP_SMI for S5 waits for before
enabling sleep. This is required to avoid any race between
SLP_SMI and PWRBTN SMI.
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_SA || soc/intel/common/block/systemagent || bool ||  ||
Intel Processor common System Agent support
 
||
|- bgcolor="#eeeeee"
| SA_PCIEX_LENGTH || soc/intel/common/block/systemagent || hex ||  ||
This option allows you to select length of PCIEX region.
 
||
|- bgcolor="#eeeeee"
| SA_ENABLE_IMR || soc/intel/common/block/systemagent || bool ||  ||
This option allows you to add the isolated memory ranges (IMRs).
 
||
|- bgcolor="#eeeeee"
| SA_ENABLE_DPR || soc/intel/common/block/systemagent || bool ||  ||
This option allows you to add the DMA Protected Range (DPR).
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_HDA || soc/intel/common/block/hda || bool ||  ||
Intel Processor common High Definition Audio driver support
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_LPSS || soc/intel/common/block/lpss || bool ||  ||
Intel Processor common LPSS support
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_FAST_SPI || soc/intel/common/block/fast_spi || bool ||  ||
Intel Processor common FAST_SPI support
 
||
|- bgcolor="#eeeeee"
| FAST_SPI_DISABLE_WRITE_STATUS || soc/intel/common/block/fast_spi || bool || Disable write status SPI opcode ||
Disable the write status SPI opcode in Intel Fast SPI block.
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_UART || soc/intel/common/block/uart || bool ||  ||
Intel Processor common UART support
 
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_M_VAL || soc/intel/common/block/uart || hex ||  ||
Clock m-divisor value for m/n divider
 
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_N_VAL || soc/intel/common/block/uart || hex ||  ||
Clock m-divisor value for m/n divider
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_GSPI || soc/intel/common/block/gspi || bool ||  ||
Intel Processor Common GSPI support
 
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ || soc/intel/common/block/gspi || int ||  ||
The input clock speed into the SPI controller IP block, in MHz.
No default is set here as this is an SOC-specific value
and must be provided by the SOC.
 
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_GSPI_MAX || soc/intel/common/block/gspi || int ||  ||
Maximum number of GSPI controllers supported by the PCH. SoC
must define this config if SOC_INTEL_COMMON_BLOCK_GSPI is
selected.
 
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 || soc/intel/common/block/gspi || bool ||  ||
Intel Processor Common GSPI support with quirks to handle
SPI_CS_CONTROL changes introduced in CNL.
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_XHCI || soc/intel/common/block/xhci || bool ||  ||
Intel Processor common XHCI support
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_PCIE || soc/intel/common/block/pcie || bool ||  ||
Intel Processor common PCIE support
 
||
|- bgcolor="#eeeeee"
| PCIE_DEBUG_INFO || soc/intel/common/block/pcie || bool ||  ||
Enable debug logs in PCIe module. Allows debug information on memory
base and limit, prefetchable memory base and limit, prefetchable memory
base upper 32 bits and prefetchable memory limit upper 32 bits.
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_PCR || soc/intel/common/block/pcr || bool ||  ||
Intel Processor common Private configuration registers (PCR)
 
||
|- bgcolor="#eeeeee"
| PCR_COMMON_IOSF_1_0 || soc/intel/common/block/pcr || bool ||  ||
The mapping of addresses via the SBREG_BAR assumes the IOSF-SB
agents are using 32-bit aligned accesses for their configuration
registers. For IOSF versions greater than 1_0, IOSF-SB
agents can use any access (8/16/32 bit aligned) for their
configuration registers
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_ACPI || soc/intel/common/block/acpi || bool ||  ||
Intel Processor common code for ACPI
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_RTC || soc/intel/common/block/rtc || bool ||  ||
Intel Processor common RTC support
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_CPU || soc/intel/common/block/cpu || bool ||  ||
This option selects Intel Common CPU Model support code
which provides various CPU related APIs which are common
between all Intel Processor families. Common CPU code is supported
for SOCs starting from SKL,KBL,APL, and future.
 
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_CPU_MPINIT || soc/intel/common/block/cpu || bool ||  ||
This option selects Intel Common CPU MP Init code. In
this common MP Init mechanism, the MP Init is occurring before
calling FSP Silicon Init. Hence, MP Init will be pulled to
BS_DEV_INIT_CHIPS Entry. And on Exit of BS_DEV_INIT, it is
ensured that all MTRRs are re-programmed based on the DRAM
resource settings.
 
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_CAR || soc/intel/common/block/cpu || bool ||  ||
This option allows you to select how cache-as-ram (CAR) is set up.
 
||
|- bgcolor="#eeeeee"
| INTEL_CAR_NEM || soc/intel/common/block/cpu || bool ||  ||
Traditionally, CAR is set up by using Non-Evict mode. This method
does not allow CAR and cache to co-exist, because cache fills are
blocked in NEM.
 
||
|- bgcolor="#eeeeee"
| INTEL_CAR_CQOS || soc/intel/common/block/cpu || bool ||  ||
Cache Quality of Service allows more fine-grained control of cache
usage. As result, it is possible to set up a portion of L2 cache for
CAR and use the remainder for actual caching.
 
||
|- bgcolor="#eeeeee"
| INTEL_CAR_NEM_ENHANCED || soc/intel/common/block/cpu || bool ||  ||
A current limitation of NEM (Non-Evict mode) is that code and data sizes
are derived from the requirement to not write out any modified cache line.
With NEM, if there is no physical memory behind the cached area,
the modified data will be lost and NEM results will be inconsistent.
ENHANCED NEM guarantees that modified data is always
kept in cache while clean data is replaced.
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_CSE || soc/intel/common/block/cse || bool ||  ||
Driver for communication with Converged Security Engine (CSE)
over Host Embedded Controller Interface (HECI)
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_EBDA || soc/intel/common/block/ebda || bool ||  ||
Intel Processor common EBDA library support
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_PMC || soc/intel/common/block/pmc || bool ||  ||
Intel Processor common code for Power Management controller(PMC)
subsystem
 
||
|- bgcolor="#eeeeee"
| POWER_STATE_OFF_AFTER_FAILURE || soc/intel/common/block/pmc || bool || S5 Soft Off ||
Choose this option if you want to keep system into
S5 after reapplying power after failure
 
||
|- bgcolor="#eeeeee"
| POWER_STATE_ON_AFTER_FAILURE || soc/intel/common/block/pmc || bool || S0 Full On ||
Choose this option if you want to keep system into
S0 after reapplying power after failure
 
||
|- bgcolor="#eeeeee"
| POWER_STATE_PREVIOUS_AFTER_FAILURE || soc/intel/common/block/pmc || bool || Keep Previous State ||
Choose this option if you want to keep system into
same power state as before failure even after reapplying
power
 
||
|- bgcolor="#eeeeee"
| PMC_INVALID_READ_AFTER_WRITE || soc/intel/common/block/pmc || bool ||  ||
Enable this for PMC devices where a read back of ACPI BAR and
IO access bit does not return the previously written value.
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_SMBUS || soc/intel/common/block/smbus || bool ||  ||
Intel Processor common SMBus support
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_GPIO || soc/intel/common/block/gpio || bool ||  ||
Intel Processor common GPIO support
 
||
|- bgcolor="#eeeeee"
| DEBUG_SOC_COMMON_BLOCK_GPIO || soc/intel/common/block/gpio || bool || Output verbose GPIO debug messages ||
This option enables GPIO debug messages
 
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_SGX || soc/intel/common/block/sgx || bool ||  ||
Software Guard eXtension(SGX) Feature. Intel SGX is a set of new CPU
instructions that can be used by applications to set aside private
regions of code and data.
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_DSP || soc/intel/common/block/dsp || bool ||  ||
Intel Processor common DSP support
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_I2C || soc/intel/common/block/i2c || bool ||  ||
Intel Processor Common I2C support
 
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_I2C_DEBUG || soc/intel/common/block/i2c || bool || Enable debug output for LPSS I2C transactions ||
Enable debug output for I2C transactions.  This can be useful
when debugging I2C drivers.
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_SRAM || soc/intel/common/block/sram || bool ||  ||
Intel Processor common SRAM support
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_ITSS || soc/intel/common/block/itss || bool ||  ||
Intel Processor common interrupt timer subsystem support
 
||
||
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_GRAPHICS || soc/intel/common/block/graphics || bool ||  ||
Intel Processor common Graphics support
 
||
 
||
|- bgcolor="#eeeeee"
| ACPI_CONSOLE || soc/intel/common || bool ||  ||
Provide a mechanism for serial console based ACPI debug.
 
||
|- bgcolor="#eeeeee"
| MMA || soc/intel/common || bool || Enable MMA (Memory Margin Analysis) support for Intel Core ||
Set this option to y to enable MMA (Memory Margin Analysis) support
 
||
|- bgcolor="#eeeeee"
| TPM_TIS_ACPI_INTERRUPT || soc/intel/common || int ||  ||
acpi_get_gpe() is used to provide interrupt status to TPM layer.
This option specifies the GPE number.
 
||
|- bgcolor="#eeeeee"
| SOC_AMD_STONEYRIDGE_FP4 || soc/amd/stoneyridge || bool ||  ||
AMD Stoney Ridge FP4 support
 
||
|- bgcolor="#eeeeee"
| SOC_AMD_STONEYRIDGE_FT4 || soc/amd/stoneyridge || bool ||  ||
AMD Stoney Ridge FT4 support
 
||
|- bgcolor="#eeeeee"
| DCACHE_BSP_STACK_SIZE || soc/amd/stoneyridge || hex ||  ||
The amount of anticipated stack usage in CAR by bootblock and
other stages.
 
||
|- bgcolor="#eeeeee"
| PRERAM_CBMEM_CONSOLE_SIZE || soc/amd/stoneyridge || hex ||  ||
Increase this value if preram cbmem console is getting truncated
 
||
|- bgcolor="#eeeeee"
| BOTTOMIO_POSITION || soc/amd/stoneyridge || hex || Bottom of 32-bit IO space ||
If PCI peripherals with big BARs are connected to the system
the bottom of the IO must be decreased to allocate such
devices.
 
Declare the beginning of the 128MB-aligned MMIO region.  This
option is useful when PCI peripherals requesting large address
ranges are present.
 
||
|- bgcolor="#eeeeee"
| VGA_BIOS_ID || soc/amd/stoneyridge || string ||  ||
The default VGA BIOS PCI vendor/device ID should be set to the
result of the map_oprom_vendev() function in northbridge.c.
 
||
|- bgcolor="#eeeeee"
| STONEYRIDGE_XHCI_ENABLE || soc/amd/stoneyridge || bool || Enable Stoney Ridge XHCI Controller ||
The XHCI controller must be enabled and the XHCI firmware
must be added in order to have USB 3.0 support configured
by coreboot. The OS will be responsible for enabling the XHCI
controller if the the XHCI firmware is available but the
XHCI controller is not enabled by coreboot.
 
||
|- bgcolor="#eeeeee"
| STONEYRIDGE_XHCI_FWM || soc/amd/stoneyridge || bool || Add xhci firmware ||
Add Stoney Ridge XHCI Firmware to support the onboard USB 3.0
 
||
|- bgcolor="#eeeeee"
| STONEYRIDGE_IMC_FWM || soc/amd/stoneyridge || bool || Add IMC firmware ||
Add Stoney Ridge IMC Firmware to support the onboard fan control
 
||
|- bgcolor="#eeeeee"
| STONEYRIDGE_GEC_FWM || soc/amd/stoneyridge || bool ||  ||
Add Stoney Ridge GEC Firmware to support the onboard gigabit Ethernet MAC.
Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
 
||
|- bgcolor="#eeeeee"
| STONEYRIDGE_SATA_MODE || soc/amd/stoneyridge || int || SATA Mode ||
Select the mode in which SATA should be driven.
The default is NATIVE.
0: NATIVE mode does not require a ROM.
2: AHCI may work with or without AHCI ROM. It depends on the payload support.
For example, seabios does not require the AHCI ROM.
3: LEGACY IDE
4: IDE to AHCI
5: AHCI7804: ROM Required, and AMD driver required in the OS.
6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
 
||
|- bgcolor="#eeeeee"
| || || (comment) || || NATIVE ||
|- bgcolor="#eeeeee"
| || || (comment) || || AHCI ||
|- bgcolor="#eeeeee"
| || || (comment) || || LEGACY IDE ||
|- bgcolor="#eeeeee"
| || || (comment) || || IDE to AHCI ||
|- bgcolor="#eeeeee"
| || || (comment) || || AHCI7804 ||
|- bgcolor="#eeeeee"
| || || (comment) || || IDE to AHCI7804 ||
|- bgcolor="#eeeeee"
| STONEYRIDGE_LEGACY_FREE || soc/amd/stoneyridge || bool || System is legacy free ||
Select y if there is no keyboard controller in the system.
This sets variables in AGESA and ACPI.
 
||
|- bgcolor="#eeeeee"
| SERIRQ_CONTINUOUS_MODE || soc/amd/stoneyridge || bool ||  ||
Set this option to y for serial IRQ in continuous mode.
Otherwise it is in quiet mode.
 
||
|- bgcolor="#eeeeee"
| STONEYRIDGE_ACPI_IO_BASE || soc/amd/stoneyridge || hex ||  ||
Base address for the ACPI registers.
This value must match the hardcoded value of AGESA.
 
||
|- bgcolor="#eeeeee"
| STONEYRIDGE_UART || soc/amd/stoneyridge || bool || UART controller on Stoney Ridge ||
There are two UART controllers in Stoney Ridge.
The UART registers are memory-mapped. UART
controller 0 registers range from FEDC_6000h
to FEDC_6FFFh. UART controller 1 registers
range from FEDC_8000h to FEDC_8FFFh.
 
||
|- bgcolor="#eeeeee"
| USE_PSPSCUREOS || soc/amd/stoneyridge || bool || Include PSP SecureOS blobs in AMD firmware ||
Include the PspSecureOs, PspTrustlet and TrustletKey binaries
in the amdfw section.
 
If unsure, answer 'y'
 
||
|- bgcolor="#eeeeee"
| AMDFW_OUTSIDE_CBFS || soc/amd/stoneyridge || bool || The AMD firmware is outside CBFS ||
The AMDFW (PSP) is typically locatable in cbfs.  Select this
option to manually attach the generated amdfw.rom outside of
cbfs.  The location is selected by the FWM position.
 
||
|- bgcolor="#eeeeee"
| AMD_FWM_POSITION_INDEX || soc/amd/stoneyridge || int || Firmware Directory Table location (0 to 5) ||
Typically this is calculated by the ROM size, but there may
be situations where you want to put the firmware directory
table in a different location.
0: 512 KB - 0xFFFA0000
1: 1 MB  - 0xFFF20000
2: 2 MB  - 0xFFE20000
3: 4 MB  - 0xFFC20000
4: 8 MB  - 0xFF820000
5: 16 MB  - 0xFF020000
 
||
|- bgcolor="#eeeeee"
| || || (comment) || || AMD Firmware Directory Table set to location for 512KB ROM ||
|- bgcolor="#eeeeee"
| || || (comment) || || AMD Firmware Directory Table set to location for 1MB ROM ||
|- bgcolor="#eeeeee"
| || || (comment) || || AMD Firmware Directory Table set to location for 2MB ROM ||
|- bgcolor="#eeeeee"
| || || (comment) || || AMD Firmware Directory Table set to location for 4MB ROM ||
|- bgcolor="#eeeeee"
| || || (comment) || || AMD Firmware Directory Table set to location for 8MB ROM ||
|- bgcolor="#eeeeee"
| || || (comment) || || AMD Firmware Directory Table set to location for 16MB ROM ||
|- bgcolor="#eeeeee"
| MAINBOARD_POWER_RESTORE || soc/amd/stoneyridge || int ||  ||
This option determines what state to go to once power is restored
after having been lost in S0.  Select this option to automatically
return to S0.  Otherwise the system will remain in S5 once power
is restored.
 
||
|- bgcolor="#eeeeee"
| VENDORCODE_FULL_SUPPORT || soc/amd/stoneyridge || int ||  ||
This option determines if all files under
vendorcode/amd/pi/00670F00/ will be compiled or only
selected procedures of source files (minimum required).
 
||
|- bgcolor="#eeeeee"
| SOC_AMD_COMMON || soc/amd/common || bool ||  ||
common code for AMD SOCs
 
||
|- bgcolor="#eeeeee"
| SOC_AMD_COMMON_BLOCK || soc/amd/common/block || bool ||  ||
SoC driver for AMD common IP code
 
||
|- bgcolor="#eeeeee"
| || || (comment) || || AMD SoC Common IP Code ||
|- bgcolor="#eeeeee"
| SOC_AMD_COMMON_BLOCK_S3 || soc/amd/common/block/s3 || bool ||  ||
Select this option to add S3 related functions to the build.
 
||
||
|- bgcolor="#eeeeee"
| SOC_AMD_COMMON_BLOCK_PI || soc/amd/common/block/pi || bool ||  ||
This option builds functions that interface AMD's AGESA.
 
||
||
|- bgcolor="#eeeeee"
| SOC_AMD_COMMON_BLOCK_PCI || soc/amd/common/block/pci || bool ||  ||
This option builds functions used to program PCI interrupt
routing, both PIC and APIC modes.
 
||
||
|- bgcolor="#eeeeee"
| SOC_AMD_COMMON_BLOCK_CAR || soc/amd/common/block/cpu || bool ||  ||
This option allows the SOC to use a standard AMD cache-as-ram (CAR)
implementation.  CAR setup is built into bootblock and teardown is
in postcar.  The teardown procedure does not preserve the stack so
it may not be appropriate for a romstage implementation without
additional consideration.  If this option is not used, the SOC must
implement these functions separately.
 
||
||
|- bgcolor="#eeeeee"
| SOC_AMD_COMMON_BLOCK_PSP || soc/amd/common/block/psp || bool ||  ||
This option builds in the Platform Security Processor initialization
functions.
 
||
|- bgcolor="#eeeeee"
| SOC_AMD_PSP_SELECTABLE_SMU_FW || soc/amd/common/block/psp || bool ||  ||
Some PSP implementations allow storing SMU firmware into cbfs and
calling the PSP to load the blobs at the proper time.
 
The soc/&lt;codename&gt; should select this if its PSP supports the feature
and each mainboard can choose to select an appropriate fanless or
fanned set of blobs.  Ask your AMD representative whether your APU
is considered fanless.
 
||
 
||
|- bgcolor="#eeeeee"
| CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE || soc/broadcom/cygnus || bool || Enable DDR auto self-refresh ||
Warning: M0 expects that auto self-refresh is enabled. Modify
with caution.
 
 
||
|- bgcolor="#eeeeee"
| DEBUG_DRAM || soc/mediatek/mt8173 || bool || Output verbose DRAM related debug messages ||
This option enables additional DRAM related debug messages.
 
||
|- bgcolor="#eeeeee"
| DEBUG_I2C || soc/mediatek/mt8173 || bool || Output verbose I2C related debug messages ||
This option enables I2C related debug messages.
 
||
|- bgcolor="#eeeeee"
| DEBUG_PMIC || soc/mediatek/mt8173 || bool || Output verbose PMIC related debug messages ||
This option enables PMIC related debug messages.
 
||
|- bgcolor="#eeeeee"
| DEBUG_PMIC_WRAP || soc/mediatek/mt8173 || bool || Output verbose PMIC WRAP related debug messages ||
This option enables PMIC WRAP related debug messages.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_MVMAP2315_UART_ADDRESS || soc/marvell/mvmap2315 || hex ||  ||
Map the UART to the respective MMIO address
 
||
|- bgcolor="#eeeeee"
| TTYS0_BAUD || soc/marvell/mvmap2315 || int ||  ||
Baud rate for the UART
||
|- bgcolor="#eeeeee"
| IPQ_QFN_PART || soc/qualcomm/ipq40xx || bool ||  ||
Is the SoC a QFN part (as opposed to a BGA part)
 
||
|- bgcolor="#eeeeee"
| SBL_ELF || soc/qualcomm/ipq40xx || string || file name of the QCA SBL ELF ||
The path and filename of the binary blob containing
ipq40xx early initialization code, as supplied by the
vendor.
 
||
|- bgcolor="#eeeeee"
| SBL_UTIL_PATH || soc/qualcomm/ipq40xx || string || Path for utils to combine SBL_ELF and bootblock ||
Path for utils to combine SBL_ELF and bootblock
 
||
|- bgcolor="#eeeeee"
| SBL_BLOB || soc/qualcomm/ipq806x || string || file name of the Qualcomm SBL blob ||
The path and filename of the binary blob containing
ipq806x early initialization code, as supplied by the
vendor.
 
||
|- bgcolor="#eeeeee"
| RK3399_SPREAD_SPECTRUM_DDR || soc/rockchip/rk3399 || bool || Spread-spectrum DDR clock ||
Select Spread Spectrum Modulator (SSMOD) is a fully-digital circuit
used to modulate the frequency of the Silicon Creations’ Fractional
PLL in order to reduce EMI.
 
||
|- bgcolor="#eeeeee"
| || || (comment) || || CPU ||
|- bgcolor="#eeeeee"
| RESET_ON_INVALID_RAMSTAGE_CACHE || cpu/intel/haswell || bool || Reset the system on S3 wake when ramstage cache invalid. ||
The haswell romstage code caches the loaded ramstage program
in SMM space. On S3 wake the romstage will copy over a fresh
ramstage that was cached in the SMM space. This option determines
the action to take when the ramstage cache is invalid. If selected
the system will reset otherwise the ramstage will be reloaded from
cbfs.
 
||
|- bgcolor="#eeeeee"
| CPU_INTEL_FIRMWARE_INTERFACE_TABLE || cpu/intel/fit || None ||  ||
This option selects building a Firmware Interface Table (FIT).
 
||
|- bgcolor="#eeeeee"
| CPU_INTEL_NUM_FIT_ENTRIES || cpu/intel/fit || int ||  ||
This option selects the number of empty entries in the FIT table.
 
||
||
|- bgcolor="#eeeeee"
| CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED || cpu/intel/turbo || None ||  ||
This option indicates that the turbo mode setting is not package
scoped. i.e. enable_turbo() needs to be called on not just the bsp
 
||
||
|- bgcolor="#eeeeee"
| SET_VMX_LOCK_BIT || cpu/intel/common || bool || Set lock bit after configuring VMX ||
Although the Intel manual says you must set the lock bit in addition
to the VMX bit in order for VMX to work, this isn't strictly true, so
we have the option to leave it unlocked and allow the OS (e.g. Linux)
to manage things itself. This is beneficial for testing purposes as
there is no need to reflash the firmware just to toggle the lock bit.
However, leaving the lock bit unset will break Windows' detection of
VMX support and built-in virtualization features like Hyper-V.
 
||
|- bgcolor="#eeeeee"
| GEODE_VSA_FILE || cpu/amd/geode_lx || bool || Add a VSA image ||
Select this option if you have an AMD Geode LX vsa that you would
like to add to your ROM.
 
You will be able to specify the location and file name of the
image later.
 
||
|- bgcolor="#eeeeee"
| VSA_FILENAME || cpu/amd/geode_lx || string || AMD Geode LX VSA path and filename ||
The path and filename of the file to use as VSA.
 
||
|- bgcolor="#eeeeee"
| XIP_ROM_SIZE || cpu/amd/agesa || hex ||  ||
Overwride the default write through caching size as 1M Bytes.
On some AMD platforms, one socket supports 2 or more kinds of
processor family, compiling several CPU families agesa code
will increase the romstage size.
In order to execute romstage in place on the flash ROM,
more space is required to be set as write through caching.
 
||
|- bgcolor="#eeeeee"
| ENABLE_MRC_CACHE || cpu/amd/agesa || bool || Use cached memory configuration ||
Try to restore memory training results
from non-volatile memory.
 
||
|- bgcolor="#eeeeee"
| FORCE_AM1_SOCKET_SUPPORT || cpu/amd/agesa/family16kb || bool ||  ||
Force AGESA to ignore package type mismatch between CPU and northbridge
in memory code. This enables Socket AM1 support with current AGESA
version for Kabini platform.
Enable this option only if you have Socket AM1 board.
Note that the AGESA release shipped with coreboot does not officially
support the AM1 socket. Selecting this option might damage your hardware.
 
||
|- bgcolor="#eeeeee"
| XIP_ROM_SIZE || cpu/amd/pi || hex ||  ||
Overwride the default write through caching size as 1M Bytes.
On some AMD platforms, one socket supports 2 or more kinds of
processor family, compiling several CPU families agesa code
will increase the romstage size.
In order to execute romstage in place on the flash ROM,
more space is required to be set as write through caching.
 
||
|- bgcolor="#eeeeee"
| PARALLEL_MP || cpu/x86 || bool ||  ||
This option uses common MP infrastructure for bringing up APs
in parallel. It additionally provides a more flexible mechanism
for sequencing the steps of bringing up the APs.
 
||
|- bgcolor="#eeeeee"
| PARALLEL_MP_AP_WORK || cpu/x86 || bool ||  ||
Allow APs to do other work after initialization instead of going
to sleep.
 
||
|- bgcolor="#eeeeee"
| LAPIC_MONOTONIC_TIMER || cpu/x86 || bool ||  ||
Expose monotonic time using the local APIC.
 
||
|- bgcolor="#eeeeee"
| TSC_CONSTANT_RATE || cpu/x86 || bool ||  ||
This option asserts that the TSC ticks at a known constant rate.
Therefore, no TSC calibration is required.
 
||
|- bgcolor="#eeeeee"
| TSC_MONOTONIC_TIMER || cpu/x86 || bool ||  ||
Expose monotonic time using the TSC.
 
||
|- bgcolor="#eeeeee"
| TSC_SYNC_LFENCE || cpu/x86 || bool ||  ||
The CPU driver should select this if the CPU needs
to execute an lfence instruction in order to synchronize
rdtsc. This is true for all modern AMD CPUs.
 
||
|- bgcolor="#eeeeee"
| TSC_SYNC_MFENCE || cpu/x86 || bool ||  ||
The CPU driver should select this if the CPU needs
to execute an mfence instruction in order to synchronize
rdtsc. This is true for all modern Intel CPUs.
 
||
|- bgcolor="#eeeeee"
| NO_FIXED_XIP_ROM_SIZE || cpu/x86 || bool ||  ||
The XIP_ROM_SIZE Kconfig variable is used globally on x86
with the assumption that all chipsets utilize this value.
For the chipsets which do not use the variable it can lead
to unnecessary alignment constraints in cbfs for romstage.
Therefore, allow those chipsets a path to not be burdened.
 
||
|- bgcolor="#eeeeee"
| SMM_MODULE_HEAP_SIZE || cpu/x86 || hex ||  ||
This option determines the size of the heap within the SMM handler
modules.
 
||
|- bgcolor="#eeeeee"
| SERIALIZED_SMM_INITIALIZATION || cpu/x86 || bool ||  ||
On some CPUs, there is a race condition in SMM.
This can occur when both hyperthreads change SMM state
variables in parallel without coordination.
Setting this option serializes the SMM initialization
to avoid an ugly hang in the boot process at the cost
of a slightly longer boot time.
 
||
|- bgcolor="#eeeeee"
| X86_AMD_FIXED_MTRRS || cpu/x86 || bool ||  ||
This option informs the MTRR code to use the RdMem and WrMem fields
in the fixed MTRR MSRs.
 
||
|- bgcolor="#eeeeee"
| PLATFORM_USES_FSP1_0 || cpu/x86 || bool ||  ||
Selected for Intel processors/platform combinations that use the
Intel Firmware Support Package (FSP) 1.0 for initialization.
 
||
|- bgcolor="#eeeeee"
| MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING || cpu/x86 || bool ||  ||
On certain platforms a boot speed gain can be realized if mirroring
the payload data stored in non-volatile storage. On x86 systems the
payload would typically live in a memory-mapped SPI part. Copying
the SPI contents to RAM before performing the load can speed up
the boot process.
 
||
|- bgcolor="#eeeeee"
| SOC_SETS_MSRS || cpu/x86 || bool ||  ||
The SoC requires different access methods for reading and writing
the MSRs.  Use SoC specific routines to handle the MSR access.
 
||
||
|- bgcolor="#eeeeee"
| NO_CAR_GLOBAL_MIGRATION || cpu || bool ||  ||
This option is selected if there is no need to migrate CAR globals.
All stages which use CAR globals can directly access the variables
from their linked addresses.
 
||
|- bgcolor="#eeeeee"
| SMP || cpu || bool ||  ||
This option is used to enable certain functions to make coreboot
work correctly on symmetric multi processor (SMP) systems.
 
||
|- bgcolor="#eeeeee"
| AP_SIPI_VECTOR || cpu || hex ||  ||
This must equal address of ap_sipi_vector from bootblock build.
 
||
|- bgcolor="#eeeeee"
| MMX || cpu || bool ||  ||
Select MMX in your socket or model Kconfig if your CPU has MMX
streaming SIMD instructions. ROMCC can build more efficient
code if it can spill to MMX registers.
 
||
|- bgcolor="#eeeeee"
| SSE || cpu || bool ||  ||
Select SSE in your socket or model Kconfig if your CPU has SSE
streaming SIMD instructions. ROMCC can build more efficient
code if it can spill to SSE (aka XMM) registers.
 
||
|- bgcolor="#eeeeee"
| SSE2 || cpu || bool ||  ||
Select SSE2 in your socket or model Kconfig if your CPU has SSE2
streaming SIMD instructions. Some parts of coreboot can be built
with more efficient code if SSE2 instructions are available.
 
||
|- bgcolor="#eeeeee"
| USES_MICROCODE_HEADER_FILES || cpu || bool ||  ||
This is selected by a board or chipset to set the default for the
microcode source choice to a list of external microcode headers
 
||
|- bgcolor="#eeeeee"
| CPU_MICROCODE_CBFS_GENERATE || cpu || bool || Generate from tree ||
Select this option if you want microcode updates to be assembled when
building coreboot and included in the final image as a separate CBFS
file. Microcode will not be hard-coded into ramstage.
 
The microcode file may be removed from the ROM image at a later
time with cbfstool, if desired.
 
If unsure, select this option.
 
||
|- bgcolor="#eeeeee"
| CPU_MICROCODE_CBFS_EXTERNAL_HEADER || cpu || bool || Include external microcode header files ||
Select this option if you want to include external c header files
containing the CPU microcode. This will be included as a separate
file in CBFS.
 
A word of caution: only select this option if you are sure the
microcode that you have is newer than the microcode shipping with
coreboot.
 
The microcode file may be removed from the ROM image at a later
time with cbfstool, if desired.
 
If unsure, select "Generate from tree"
 
||
|- bgcolor="#eeeeee"
| CPU_MICROCODE_CBFS_NONE || cpu || bool || Do not include microcode updates ||
Select this option if you do not want CPU microcode included in CBFS.
Note that for some CPUs, the microcode is hard-coded into the source
tree and is not loaded from CBFS. In this case, microcode will still
be updated. There is a push to move all microcode to CBFS, but this
change is not implemented for all CPUs.
 
This option currently applies to:
- Intel SandyBridge/IvyBridge
- VIA Nano
 
Microcode may be added to the ROM image at a later time with cbfstool,
if desired.
 
If unsure, select "Generate from tree"
 
The GOOD:
Microcode updates intend to solve issues that have been discovered
after CPU production. The expected effect is that systems work as
intended with the updated microcode, but we have also seen cases where
issues were solved by not applying microcode updates.
 
The BAD:
Note that some operating system include these same microcode patches,
so you may need to also disable microcode updates in your operating
system for this option to have an effect.
 
The UGLY:
A word of CAUTION: some CPUs depend on microcode updates to function
correctly. Not updating the microcode may leave the CPU operating at
less than optimal performance, or may cause outright hangups.
There are CPUs where coreboot cannot properly initialize the CPU
without microcode updates
For example, if running with the factory microcode, some Intel
SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs
will hang when changing the frequency.
 
Make sure you have a way of flashing the ROM externally before
selecting this option.
 
||
|- bgcolor="#eeeeee"
| CPU_MICROCODE_MULTIPLE_FILES || cpu || bool ||  ||
Select this option to install separate microcode container files into
CBFS instead of using the traditional monolithic microcode file format.
 
||
|- bgcolor="#eeeeee"
| CPU_MICROCODE_HEADER_FILES || cpu || string || List of space separated microcode header files with the path ||
A list of one or more microcode header files with path from the
coreboot directory.  These should be separated by spaces.
 
||
|- bgcolor="#eeeeee"
| CPU_UCODE_BINARIES || cpu || string || Microcode binary path and filename ||
Some platforms have microcode in the blobs directory, and these can
be hardcoded in the makefiles.  For platforms with microcode
binaries that aren't in the makefile, set this option to pull
in the microcode.
 
This should contain the full path of the file for one or more
microcode binary files to include, separated by spaces.
 
If unsure, leave this blank.
 
||
||
|- bgcolor="#eeeeee"
| || || (comment) || || Northbridge ||
|- bgcolor="#eeeeee"
| I945_LVDS || northbridge/intel/i945 || string ||  ||
Selected by mainboards that use native graphics initialization
for the LVDS port. A linear framebuffer is only supported for
LVDS.
 
||
|- bgcolor="#eeeeee"
| OVERRIDE_CLOCK_DISABLE || northbridge/intel/i945 || bool ||  ||
Usually system firmware turns off system memory clock
signals to unused SO-DIMM slots to reduce EMI and power
consumption.
However, some boards do not like unused clock signals to
be disabled.
 
||
|- bgcolor="#eeeeee"
| MAXIMUM_SUPPORTED_FREQUENCY || northbridge/intel/i945 || int ||  ||
If non-zero, this designates the maximum DDR frequency
the board supports, despite what the chipset should be
capable of.
 
||
|- bgcolor="#eeeeee"
| CHECK_SLFRCS_ON_RESUME || northbridge/intel/i945 || int ||  ||
On some boards it may be neccessary to hard reset early
during resume from S3 if the SLFRCS register indicates that
a memory channel is not guaranteed to be in self-refresh.
On other boards the check always creates a false positive,
effectively making it impossible to resume.
 
||
|- bgcolor="#eeeeee"
| USE_NATIVE_RAMINIT || northbridge/intel/sandybridge || bool || Use native raminit ||
Select if you want to use coreboot implementation of raminit rather than
System Agent/MRC.bin. You should answer Y.
 
||
|- bgcolor="#eeeeee"
| NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES || northbridge/intel/sandybridge || bool || Ignore vendor programmed fuses that limit max. DRAM frequency ||
Ignore the mainboard's vendor programmed fuses that might limit the
maximum DRAM frequency. By selecting this option the fuses will be
ignored and the only limits on DRAM frequency are set by RAM's SPD and
hard fuses in southbridge's clockgen.
Disabled by default as it might causes system instability.
Handle with care!
 
||
|- bgcolor="#eeeeee"
| NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS || northbridge/intel/sandybridge || bool || Ignore XMP profile max DIMMs per channel ||
Ignore the max DIMMs per channel restriciton defined in XMP profiles.
Disabled by default as it might cause system instability.
Handle with care!
 
||
|- bgcolor="#eeeeee"
| MMCONF_BASE_ADDRESS || northbridge/intel/sandybridge || hex ||  ||
The MRC blob requires it to be at 0xf0000000.
 
||
|- bgcolor="#eeeeee"
| MRC_FILE || northbridge/intel/sandybridge || string || Intel System Agent path and filename ||
The path and filename of the file to use as System Agent
binary.
 
||
|- bgcolor="#eeeeee"
| DCACHE_RAM_SIZE || northbridge/intel/haswell || hex ||  ||
The size of the cache-as-ram region required during bootblock
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
must add up to a power of 2.
 
||
|- bgcolor="#eeeeee"
| DCACHE_RAM_MRC_VAR_SIZE || northbridge/intel/haswell || hex ||  ||
The amount of cache-as-ram region required by the reference code.
 
||
|- bgcolor="#eeeeee"
| DCACHE_RAM_ROMSTAGE_STACK_SIZE || northbridge/intel/haswell || hex ||  ||
The amount of anticipated stack usage from the data cache
during pre-ram ROM stage execution.
 
||
|- bgcolor="#eeeeee"
| HAVE_MRC || northbridge/intel/haswell || bool || Add a System Agent binary ||
Select this option to add a System Agent binary to
the resulting coreboot image.
 
Note: Without this binary coreboot will not work
 
||
|- bgcolor="#eeeeee"
| MRC_FILE || northbridge/intel/haswell || string || Intel System Agent path and filename ||
The path and filename of the file to use as System Agent
binary.
 
||
|- bgcolor="#eeeeee"
| PRE_GRAPHICS_DELAY || northbridge/intel/haswell || int || Graphics initialization delay in ms ||
On some systems, coreboot boots so fast that connected monitors
(mostly TVs) won't be able to wake up fast enough to talk to the
VBIOS. On those systems we need to wait for a bit before executing
the VBIOS.
 
||
|- bgcolor="#eeeeee"
| VGA_BIOS_ID || northbridge/intel/fsp_sandybridge || string ||  ||
This is the default PCI ID for the sandybridge/ivybridge graphics
devices.  This string names the vbios ROM in cbfs.  The following
PCI IDs will be remapped to load this ROM:
0x80860102, 0x8086010a, 0x80860112, 0x80860116
0x80860122, 0x80860126, 0x80860166
 
||
|- bgcolor="#eeeeee"
| FSP_FILE || northbridge/intel/fsp_sandybridge/fsp || string ||  ||
The path and filename of the Intel FSP binary for this platform.
 
||
|- bgcolor="#eeeeee"
| FSP_LOC || northbridge/intel/fsp_sandybridge/fsp || hex || Intel FSP Binary location in CBFS ||
The location in CBFS that the FSP is located. This must match the
value that is set in the FSP binary.  If the FSP needs to be moved,
rebase the FSP with the Intel's BCT (tool).
 
The Ivy Bridge Processor/Panther Point FSP is built with a preferred
base address of 0xFFF80000
 
||
 
||
|- bgcolor="#eeeeee"
| SDRAMPWR_4DIMM || northbridge/intel/i440bx || bool ||  ||
This option affects how the SDRAMC register is programmed.
Memory clock signals will not be routed properly if this option
is set wrong.
 
If your board has 4 DIMM slots, you must use select this option, in
your Kconfig file of the board. On boards with 3 DIMM slots,
do _not_ select this option.
 
||
||
|- bgcolor="#eeeeee"
| SET_TSEG_1MB || northbridge/intel/fsp_rangeley || bool || 1 MB ||
Set the TSEG area to 1 MB.
 
||
|- bgcolor="#eeeeee"
| SET_TSEG_2MB || northbridge/intel/fsp_rangeley || bool || 2 MB ||
Set the TSEG area to 2 MB.
 
||
|- bgcolor="#eeeeee"
| SET_TSEG_4MB || northbridge/intel/fsp_rangeley || bool || 4 MB ||
Set the TSEG area to 4 MB.
 
||
|- bgcolor="#eeeeee"
| SET_TSEG_8MB || northbridge/intel/fsp_rangeley || bool || 8 MB ||
Set the TSEG area to 8 MB.
||
|- bgcolor="#eeeeee"
| FSP_FILE || northbridge/intel/fsp_rangeley/fsp || string ||  ||
The path and filename of the Intel FSP binary for this platform.
 
||
|- bgcolor="#eeeeee"
| FSP_LOC || northbridge/intel/fsp_rangeley/fsp || hex ||  ||
The location in CBFS that the FSP is located. This must match the
value that is set in the FSP binary.  If the FSP needs to be moved,
rebase the FSP with Intel's BCT (tool).
 
The Rangeley FSP is built with a preferred base address of 0xFFF80000
 
||
|- bgcolor="#eeeeee"
| BOTTOMIO_POSITION || northbridge/amd/pi || hex || Bottom of 32-bit IO space ||
If PCI peripherals with big BARs are connected to the system
the bottom of the IO must be decreased to allocate such
devices.
 
Declare the beginning of the 128MB-aligned MMIO region.  This
option is useful when PCI peripherals requesting large address
ranges are present.
 
||
|- bgcolor="#eeeeee"
| VGA_BIOS_ID || northbridge/amd/pi/00630F01 || string ||  ||
The default VGA BIOS PCI vendor/device ID should be set to the
result of the map_oprom_vendev() function in northbridge.c.
 
||
|- bgcolor="#eeeeee"
| VGA_BIOS_ID || northbridge/amd/pi/00730F01 || string ||  ||
The default VGA BIOS PCI vendor/device ID should be set to the
result of the map_oprom_vendev() function in northbridge.c.
 
||
|- bgcolor="#eeeeee"
| VGA_BIOS_ID || northbridge/amd/pi/00660F01 || string ||  ||
The default VGA BIOS PCI vendor/device ID should be set to the
result of the map_oprom_vendev() function in northbridge.c.
 
||
|- bgcolor="#eeeeee"
| REDIRECT_NBCIMX_TRACE_TO_SERIAL || northbridge/amd/cimx/rd890 || bool || Redirect AMD Northbridge CIMX Trace to serial console ||
This Option allows you to redirect the AMD Northbridge CIMX
Trace debug information to the serial console.
 
Warning: Only enable this option when debuging or tracing AMD CIMX code.
 
||
|- bgcolor="#eeeeee"
| NO_MMCONF_SUPPORT || northbridge/amd/amdk8 || bool ||  ||
If you want to remove this, you need to make sure any access to CPU
nodes 0:18.0, 0:19.0, ...  continue to use PCI IO config access.
 
||
|- bgcolor="#eeeeee"
| VGA_BIOS_ID || northbridge/amd/agesa/family16kb || string ||  ||
The default VGA BIOS PCI vendor/device ID should be set to the
result of the map_oprom_vendev() function in northbridge.c.
 
||
|- bgcolor="#eeeeee"
| SVI_HIGH_FREQ || northbridge/amd/amdfam10 || bool ||  ||
Select this for boards with a Voltage Regulator able to operate
at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.
 
||
|- bgcolor="#6699dd"
! align="left" | Menu: HyperTransport setup || || || ||
|- bgcolor="#eeeeee"
| SVI_HIGH_FREQ || northbridge/amd/amdfam10 || bool || HyperTransport downlink width ||
This option sets the maximum permissible HyperTransport
downlink width.
 
Use of this option will only limit the autodetected HT width.
It will not (and cannot) increase the width beyond the autodetected
limits.
 
This is primarily used to work around poorly designed or laid out HT
traces on certain motherboards.
 
||
|- bgcolor="#eeeeee"
| LIMIT_HT_DOWN_WIDTH_16 || northbridge/amd/amdfam10 || bool || HyperTransport uplink width ||
This option sets the maximum permissible HyperTransport
uplink width.
 
Use of this option will only limit the autodetected HT width.
It will not (and cannot) increase the width beyond the autodetected
limits.
 
This is primarily used to work around poorly designed or laid out HT
traces on certain motherboards.
 
||
 
|- bgcolor="#eeeeee"
| || || (comment) || || Southbridge ||
|- bgcolor="#eeeeee"
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/ibexpeak || bool ||  ||
If you set this option to y, the serial IRQ machine will be
operated in continuous mode.
 
||
|- bgcolor="#eeeeee"
| INTEL_LYNXPOINT_LP || southbridge/intel/lynxpoint || bool ||  ||
Set this option to y for Lynxpont LP (Haswell ULT).
 
||
|- bgcolor="#eeeeee"
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/lynxpoint || bool ||  ||
If you set this option to y, the serial IRQ machine will be
operated in continuous mode.
 
||
|- bgcolor="#eeeeee"
| ME_MBP_CLEAR_LATE || southbridge/intel/lynxpoint || bool || Defer wait for ME MBP Cleared ||
If you set this option to y, the Management Engine driver
will defer waiting for the MBP Cleared indicator until the
finalize step.  This can speed up boot time if the ME takes
a long time to indicate this status.
 
||
|- bgcolor="#eeeeee"
| FINALIZE_USB_ROUTE_XHCI || southbridge/intel/lynxpoint || bool || Route all ports to XHCI controller in finalize step ||
If you set this option to y, the USB ports will be routed
to the XHCI controller during the finalize SMM callback.
 
||
|- bgcolor="#eeeeee"
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/bd82x6x || bool ||  ||
If you set this option to y, the serial IRQ machine will be
operated in continuous mode.
 
||
|- bgcolor="#eeeeee"
| LOCK_SPI_FLASH_RO || southbridge/intel/bd82x6x || bool || Write-protect all flash sections ||
Select this if you want to write-protect the whole firmware flash
chip. The locking will take place during the chipset lockdown, which
is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set)
or has to be triggered later (e.g. by the payload or the OS).
 
NOTE: If you trigger the chipset lockdown unconditionally,
you won't be able to write to the flash chip using the
internal programmer any more.
 
||
|- bgcolor="#eeeeee"
| LOCK_SPI_FLASH_NO_ACCESS || southbridge/intel/bd82x6x || bool || Write-protect all flash sections and read-protect non-BIOS sections ||
Select this if you want to protect the firmware flash against all
further accesses (with the exception of the memory mapped BIOS re-
gion which is always readable). The locking will take place during
the chipset lockdown, which is either triggered by coreboot (when
INTEL_CHIPSET_LOCKDOWN is set) or has to be triggered later (e.g.
by the payload or the OS).
 
NOTE: If you trigger the chipset lockdown unconditionally,
you won't be able to write to the flash chip using the
internal programmer any more.
 
||
|- bgcolor="#eeeeee"
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/fsp_bd82x6x || bool ||  ||
If you set this option to y, the serial IRQ machine will be
operated in continuous mode.
 
||
|- bgcolor="#eeeeee"
| INTEL_CHIPSET_LOCKDOWN || southbridge/intel/common || bool || Lock down chipset in coreboot ||
Some registers within host bridge on particular chipsets should be
locked down on each normal boot path (done by either coreboot or payload)
and S3 resume (always done by coreboot). Select this to let coreboot
to do this on normal boot path.
 
||
||
|- bgcolor="#eeeeee"
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/fsp_rangeley || bool ||  ||
If you set this option to y, the serial IRQ machine will be
operated in continuous mode.
 
||
|- bgcolor="#eeeeee"
| IFD_BIN_PATH || southbridge/intel/fsp_rangeley || string ||  ||
The path and filename to the descriptor.bin file.
 
||
|- bgcolor="#eeeeee"
| SERIRQ_CONTINUOUS_MODE || southbridge/intel/fsp_i89xx || bool ||  ||
If you set this option to y, the serial IRQ machine will be
operated in continuous mode.
 
||
|- bgcolor="#eeeeee"
| HUDSON_XHCI_ENABLE || southbridge/amd/pi/hudson || bool || Enable Hudson XHCI Controller ||
The XHCI controller must be enabled and the XHCI firmware
must be added in order to have USB 3.0 support configured
by coreboot. The OS will be responsible for enabling the XHCI
controller if the the XHCI firmware is available but the
XHCI controller is not enabled by coreboot.
 
||
|- bgcolor="#eeeeee"
| HUDSON_XHCI_FWM || southbridge/amd/pi/hudson || bool || Add xhci firmware ||
Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0
 
||
|- bgcolor="#eeeeee"
| HUDSON_IMC_FWM || southbridge/amd/pi/hudson || bool || Add IMC firmware ||
Add Hudson 2/3/4 IMC Firmware to support the onboard fan control
 
||
|- bgcolor="#eeeeee"
| HUDSON_GEC_FWM || southbridge/amd/pi/hudson || bool ||  ||
Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC.
Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
 
||
|- bgcolor="#eeeeee"
| HUDSON_SATA_MODE || southbridge/amd/pi/hudson || int || SATA Mode ||
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
The default is NATIVE.
0: NATIVE mode does not require a ROM.
1: RAID mode must have the two ROM files.
2: AHCI may work with or without AHCI ROM. It depends on the payload support.
For example, seabios does not require the AHCI ROM.
3: LEGACY IDE
4: IDE to AHCI
5: AHCI7804: ROM Required, and AMD driver required in the OS.
6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
 
||
|- bgcolor="#eeeeee"
| || || (comment) || || NATIVE ||
|- bgcolor="#eeeeee"
| || || (comment) || || RAID ||
|- bgcolor="#eeeeee"
| || || (comment) || || AHCI ||
|- bgcolor="#eeeeee"
| || || (comment) || || LEGACY IDE ||
|- bgcolor="#eeeeee"
| || || (comment) || || IDE to AHCI ||
|- bgcolor="#eeeeee"
| || || (comment) || || AHCI7804 ||
|- bgcolor="#eeeeee"
| || || (comment) || || IDE to AHCI7804 ||
|- bgcolor="#eeeeee"
| RAID_ROM_ID || southbridge/amd/pi/hudson || string || RAID device PCI IDs ||
1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode
 
||
|- bgcolor="#eeeeee"
| RAID_MISC_ROM_POSITION || southbridge/amd/pi/hudson || hex || RAID Misc ROM Position ||
The RAID ROM requires that the MISC ROM is located between the range
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
The CONFIG_ROM_SIZE must be larger than 0x100000.
 
||
|- bgcolor="#eeeeee"
| HUDSON_LEGACY_FREE || southbridge/amd/pi/hudson || bool || System is legacy free ||
Select y if there is no keyboard controller in the system.
This sets variables in AGESA and ACPI.
 
||
|- bgcolor="#eeeeee"
| AZ_PIN || southbridge/amd/pi/hudson || hex ||  ||
bit 1,0 - pin 0
bit 3,2 - pin 1
bit 5,4 - pin 2
bit 7,6 - pin 3
 
||
|- bgcolor="#eeeeee"
| AMDFW_OUTSIDE_CBFS || southbridge/amd/pi/hudson || hex ||  ||
The AMDFW (PSP) is typically locatable in cbfs.  Select this
option to manually attach the generated amdfw.rom at an
offset of 0x20000 from the bottom of the coreboot ROM image.
 
||
|- bgcolor="#eeeeee"
| SERIRQ_CONTINUOUS_MODE || southbridge/amd/pi/hudson || bool ||  ||
Set this option to y for serial IRQ in continuous mode.
Otherwise it is in quiet mode.
 
||
|- bgcolor="#eeeeee"
| HUDSON_ACPI_IO_BASE || southbridge/amd/pi/hudson || hex ||  ||
Base address for the ACPI registers.
This value must match the hardcoded value of AGESA.
 
||
|- bgcolor="#eeeeee"
| HUDSON_UART || southbridge/amd/pi/hudson || bool || UART controller on Kern ||
There are two UART controllers in Kern.
The UART registers are memory-mapped. UART
controller 0 registers range from FEDC_6000h
to FEDC_6FFFh. UART controller 1 registers
range from FEDC_8000h to FEDC_8FFFh.
 
||
 
||
||
|- bgcolor="#eeeeee"
| ENABLE_IDE_COMBINED_MODE || southbridge/amd/cimx/sb800 || bool || Enable SATA IDE combined mode ||
If Combined Mode is enabled. IDE controller is exposed and
SATA controller has control over Port0 through Port3,
IDE controller has control over Port4 and Port5.
 
If Combined Mode is disabled, IDE controller is hidden and
SATA controller has full control of all 6 Ports when operating in non-IDE mode.
 
||
|- bgcolor="#eeeeee"
| IDE_COMBINED_MODE || southbridge/amd/cimx/sb800 || hex || SATA Mode ||
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
The default is AHCI.
 
||
|- bgcolor="#eeeeee"
| SB800_SATA_IDE || southbridge/amd/cimx/sb800 || bool || NATIVE ||
NATIVE does not require a ROM.
 
||
|- bgcolor="#eeeeee"
| SB800_SATA_AHCI || southbridge/amd/cimx/sb800 || bool || AHCI ||
AHCI is the default and may work with or without AHCI ROM. It depends on the payload support.
For example, seabios does not require the AHCI ROM.
 
||
|- bgcolor="#eeeeee"
| SB800_SATA_RAID || southbridge/amd/cimx/sb800 || bool || RAID ||
sb800 RAID mode must have the two required ROM files.
 
||
|- bgcolor="#eeeeee"
| RAID_ROM_ID || southbridge/amd/cimx/sb800 || string || RAID device PCI IDs ||
1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode
 
||
|- bgcolor="#eeeeee"
| RAID_MISC_ROM_POSITION || southbridge/amd/cimx/sb800 || hex || RAID Misc ROM Position ||
The RAID ROM requires that the MISC ROM is located between the range
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
The CONFIG_ROM_SIZE must larger than 0x100000.
 
||
|- bgcolor="#eeeeee"
| SB800_IMC_FWM || southbridge/amd/cimx/sb800 || bool || Add IMC firmware ||
Add SB800 / Hudson 1 IMC Firmware to support the onboard fan control.
 
||
|- bgcolor="#eeeeee"
| SB800_FWM_AT_FFFA0000 || southbridge/amd/cimx/sb800 || bool || 0xFFFA0000 ||
The IMC and GEC ROMs requires a 'signature' located at one of several
fixed locations in memory.  The location used shouldn't matter, just
select an area that doesn't conflict with anything else.
 
||
|- bgcolor="#eeeeee"
| SB800_FWM_AT_FFF20000 || southbridge/amd/cimx/sb800 || bool || 0xFFF20000 ||
The IMC and GEC ROMs requires a 'signature' located at one of several
fixed locations in memory.  The location used shouldn't matter, just
select an area that doesn't conflict with anything else.
 
||
|- bgcolor="#eeeeee"
| SB800_FWM_AT_FFE20000 || southbridge/amd/cimx/sb800 || bool || 0xFFE20000 ||
The IMC and GEC ROMs requires a 'signature' located at one of several
fixed locations in memory.  The location used shouldn't matter, just
select an area that doesn't conflict with anything else.
 
||
|- bgcolor="#eeeeee"
| SB800_FWM_AT_FFC20000 || southbridge/amd/cimx/sb800 || bool || 0xFFC20000 ||
The IMC and GEC ROMs requires a 'signature' located at one of several
fixed locations in memory.  The location used shouldn't matter, just
select an area that doesn't conflict with anything else.
 
||
|- bgcolor="#eeeeee"
| SB800_FWM_AT_FF820000 || southbridge/amd/cimx/sb800 || bool || 0xFF820000 ||
The IMC and GEC ROMs requires a 'signature' located at one of several
fixed locations in memory.  The location used shouldn't matter, just
select an area that doesn't conflict with anything else.
 
||
|- bgcolor="#eeeeee"
| EHCI_BAR || southbridge/amd/cimx/sb800 || hex || Fan Control ||
Select the method of SB800 fan control to be used.  None would be
for either fixed maximum speed fans connected to the SB800 or for
an external chip controlling the fan speeds.  Manual control sets
up the SB800 fan control registers.  IMC fan control uses the SB800
IMC to actively control the fan speeds.
 
||
|- bgcolor="#eeeeee"
| SB800_NO_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || None ||
No SB800 Fan control - Do not set up the SB800 fan control registers.
 
||
|- bgcolor="#eeeeee"
| SB800_MANUAL_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || Manual ||
Configure the SB800 fan control registers in devicetree.cb.
 
||
|- bgcolor="#eeeeee"
| SB800_IMC_FAN_CONTROL || southbridge/amd/cimx/sb800 || bool || IMC Based ||
Set up the SB800 to use the IMC based Fan controller.  This requires
the IMC ROM from AMD.  Configure the registers in devicetree.cb.
 
||
|- bgcolor="#eeeeee"
| SATA_CONTROLLER_MODE || southbridge/amd/cimx/sb900 || hex ||  ||
0x0 = Native IDE mode.
0x1 = RAID mode.
0x2 = AHCI mode.
0x3 = Legacy IDE mode.
0x4 = IDE-&gt;AHCI mode.
0x5 = AHCI mode as 7804 ID (AMD driver).
0x6 = IDE-&gt;AHCI mode as 7804 ID (AMD driver).
 
||
|- bgcolor="#eeeeee"
| PCIB_ENABLE || southbridge/amd/cimx/sb900 || bool ||  ||
n = Disable PCI Bridge Device 14 Function 4.
y = Enable PCI Bridge Device 14 Function 4.
 
||
|- bgcolor="#eeeeee"
| ACPI_SCI_IRQ || southbridge/amd/cimx/sb900 || hex ||  ||
Set SCI IRQ to 9.
 
||
|- bgcolor="#eeeeee"
| EXT_CONF_SUPPORT || southbridge/amd/sr5650 || bool || Enable PCI-E MMCONFIG support ||
Select to enable PCI-E MMCONFIG support on the SR5650.
 
||
|- bgcolor="#eeeeee"
| EXT_CONF_SUPPORT || southbridge/amd/rs690 || bool ||  ||
Select if RS690 should be setup to support MMCONF.
 
||
|- bgcolor="#eeeeee"
| HUDSON_XHCI_ENABLE || southbridge/amd/agesa/hudson || bool || Enable Hudson XHCI Controller ||
The XHCI controller must be enabled and the XHCI firmware
must be added in order to have USB 3.0 support configured
by coreboot. The OS will be responsible for enabling the XHCI
controller if the the XHCI firmware is available but the
XHCI controller is not enabled by coreboot.
 
||
|- bgcolor="#eeeeee"
| HUDSON_XHCI_FWM || southbridge/amd/agesa/hudson || bool || Add xhci firmware ||
Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0
 
||
|- bgcolor="#eeeeee"
| HUDSON_IMC_FWM || southbridge/amd/agesa/hudson || bool || Add imc firmware ||
Add Hudson 2/3/4 IMC Firmware to support the onboard fan control
 
||
|- bgcolor="#eeeeee"
| HUDSON_GEC_FWM || southbridge/amd/agesa/hudson || bool ||  ||
Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC.
Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.
 
||
|- bgcolor="#eeeeee"
| HUDSON_SATA_MODE || southbridge/amd/agesa/hudson || int || SATA Mode ||
Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
The default is NATIVE.
0: NATIVE mode does not require a ROM.
1: RAID mode must have the two ROM files.
2: AHCI may work with or without AHCI ROM. It depends on the payload support.
For example, seabios does not require the AHCI ROM.
3: LEGACY IDE
4: IDE to AHCI
5: AHCI7804: ROM Required, and AMD driver required in the OS.
6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.
 
||
|- bgcolor="#eeeeee"
| || || (comment) || || NATIVE ||
|- bgcolor="#eeeeee"
| || || (comment) || || RAID ||
|- bgcolor="#eeeeee"
| || || (comment) || || AHCI ||
|- bgcolor="#eeeeee"
| || || (comment) || || LEGACY IDE ||
|- bgcolor="#eeeeee"
| || || (comment) || || IDE to AHCI ||
|- bgcolor="#eeeeee"
| || || (comment) || || AHCI7804 ||
|- bgcolor="#eeeeee"
| || || (comment) || || IDE to AHCI7804 ||
|- bgcolor="#eeeeee"
| RAID_ROM_ID || southbridge/amd/agesa/hudson || string || RAID device PCI IDs ||
1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode
 
||
|- bgcolor="#eeeeee"
| RAID_MISC_ROM_POSITION || southbridge/amd/agesa/hudson || hex || RAID Misc ROM Position ||
The RAID ROM requires that the MISC ROM is located between the range
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
The CONFIG_ROM_SIZE must be larger than 0x100000.
 
||
|- bgcolor="#eeeeee"
| HUDSON_LEGACY_FREE || southbridge/amd/agesa/hudson || bool || System is legacy free ||
Select y if there is no keyboard controller in the system.
This sets variables in AGESA and ACPI.
 
||
|- bgcolor="#eeeeee"
| AZ_PIN || southbridge/amd/agesa/hudson || hex ||  ||
bit 1,0 - pin 0
bit 3,2 - pin 1
bit 5,4 - pin 2
bit 7,6 - pin 3
||
|- bgcolor="#eeeeee"
| SOUTHBRIDGE_AMD_SB700_33MHZ_SPI || southbridge/amd/sb700 || bool || Enable high speed SPI clock ||
When set, the SPI clock will run at 33MHz instead
of the compatibility mode 16.5MHz.  Note that not
all ROMs are capable of 33MHz operation, so you
will need to verify this option is appropriate for
the ROM you are using.
 
||
|- bgcolor="#eeeeee"
| NO_EARLY_SMBUS || southbridge/amd/cs5536 || bool ||  ||
Skip the CS5536 early SMBUS initialization.
 
||
|- bgcolor="#eeeeee"
| EHCI_BAR || southbridge/amd/sb600 || hex || SATA Mode ||
Select the mode in which SATA should be driven. IDE or AHCI.
The default is IDE.
 
config SATA_MODE_IDE
bool "IDE"
 
config SATA_MODE_AHCI
bool "AHCI"
||
|- bgcolor="#eeeeee"
| || || (comment) || || Super I/O ||
|- bgcolor="#eeeeee"
| SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG || superio/ite/common || bool ||  ||
Enable extended, 16-bit wide tacho counters.
 
||
|- bgcolor="#eeeeee"
| SUPERIO_ITE_ENV_CTRL_8BIT_PWM || superio/ite/common || bool ||  ||
PWM duty cycles are set in 8-bit registers (instead of 7 bit).
 
||
|- bgcolor="#eeeeee"
| SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 || superio/ite/common || bool ||  ||
The second FAN controller has a separate frequency setting.
 
||
|- bgcolor="#eeeeee"
| || || (comment) || || Embedded Controllers ||
|- bgcolor="#eeeeee"
| EC_ACPI || ec/acpi || bool ||  ||
ACPI Embedded Controller interface. Mostly found in laptops.
 
||
||
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC || ec/google/chromeec || bool ||  ||
Google's Chrome EC
 
||
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_ACPI_MEMMAP || ec/google/chromeec || bool ||  ||
When defined, ACPI accesses EC memmap data on ports 66h/62h. When
not defined, the memmap data is instead accessed on 900h-9ffh via
the LPC bus.
 
||
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_BOARDID || ec/google/chromeec || bool ||  ||
Provides common routine for reading boardid from Chrome EC.
 
||
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_I2C || ec/google/chromeec || bool ||  ||
Google's Chrome EC via I2C bus.
 
||
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_I2C_PROTO3 || ec/google/chromeec || bool ||  ||
Use only proto3 for i2c EC communication.
 
||
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_LPC || ec/google/chromeec || bool ||  ||
Google Chrome EC via LPC bus.
 
||
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_MEC || ec/google/chromeec || bool ||  ||
Microchip EC variant for LPC register access.
 
||
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_PD || ec/google/chromeec || bool ||  ||
Indicates that Google's Chrome USB PD chip is present.
 
||
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_SPI || ec/google/chromeec || bool ||  ||
Google's Chrome EC via SPI bus.
 
||
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US || ec/google/chromeec || int ||  ||
Force delay after asserting /CS to allow EC to wakeup.
 
||
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_BOARDNAME || ec/google/chromeec || string || Chrome EC board name for EC ||
The board name used in the Chrome EC code base to build
the EC firmware.  If set, the coreboot build with also
build the EC firmware and add it to the image.
 
||
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_PD_BOARDNAME || ec/google/chromeec || string || Chrome EC board name for PD ||
The board name used in the Chrome EC code base to build
the PD firmware.  If set, the coreboot build with also
build the EC firmware and add it to the image.
 
||
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_RTC || ec/google/chromeec || bool || Enable Chrome OS EC RTC ||
Enable support for the real-time clock on the Chrome OS EC. This
uses the EC_CMD_RTC_GET_VALUE command to read the current time.
 
||
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_FIRMWARE_NONE || ec/google/chromeec || bool || No EC firmware is included ||
Disable building and including any EC firmware in the image.
 
config EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL
bool "External EC firmware is included"
help
Include EC firmware binary in the image from an external source.
It is expected to be built externally.
 
config EC_GOOGLE_CHROMEEC_FIRMWARE_BUILTIN
bool "Builtin EC firmware is included"
help
Build and include EC firmware binary in the image.
 
||
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_FIRMWARE_FILE || ec/google/chromeec || string || Chrome EC firmware path and filename ||
The path and filename of the EC firmware file to use.
 
||
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_PD_FIRMWARE_NONE || ec/google/chromeec || bool || No PD firmware is included ||
Disable building and including any PD firmware in the image.
 
config EC_GOOGLE_CHROMEEC_PD_FIRMWARE_EXTERNAL
bool "External PD firmware is included"
help
Include PD firmware binary in the image from an external source.
It is expected to be built externally.
 
config EC_GOOGLE_CHROMEEC_PD_FIRMWARE_BUILTIN
bool "Builtin PD firmware is included"
help
Build and include PD firmware binary in the image.
 
||
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_PD_FIRMWARE_FILE || ec/google/chromeec || string || Chrome EC firmware path and filename for PD ||
The path and filename of the PD firmware file to use.
 
||
|- bgcolor="#eeeeee"
| EC_GOOGLE_CHROMEEC_SWITCHES || ec/google/chromeec || bool ||  ||
Enable support for Chrome OS mode switches provided by the Chrome OS
EC.
 
||
||
|- bgcolor="#eeeeee"
| EC_QUANTA_IT8518 || ec/quanta/it8518 || bool ||  ||
Interface to QUANTA IT8518 Embedded Controller.
 
||
||
|- bgcolor="#eeeeee"
| EC_QUANTA_ENE_KB3940Q || ec/quanta/ene_kb3940q || bool ||  ||
Interface to QUANTA ENE KB3940Q Embedded Controller.
 
||
||
|- bgcolor="#eeeeee"
| EC_HP_KBC1126 || ec/hp/kbc1126 || bool ||  ||
Interface to SMSC KBC1126 embedded controller in HP laptops.
 
||
|- bgcolor="#eeeeee"
| || || (comment) || || Please select the following otherwise your laptop cannot be powered on. ||
|- bgcolor="#eeeeee"
| KBC1126_FIRMWARE || ec/hp/kbc1126 || bool || Add firmware images for KBC1126 EC ||
Select this option to add the two firmware blobs for KBC1126.
You need these two blobs to power on your machine.
 
||
|- bgcolor="#eeeeee"
| KBC1126_FW1 || ec/hp/kbc1126 || string || KBC1126 firmware #1 path and filename ||
The path and filename of the file to use as KBC1126 firmware #1.
You can use util/kbc1126/kbc1126_ec_dump to dump it from the
vendor firmware.
 
||
|- bgcolor="#eeeeee"
| KBC1126_FW2 || ec/hp/kbc1126 || string || KBC1126 filename #2 path and filename ||
The path and filename of the file to use as KBC1126 firmware #2.
You can use util/kbc1126/kbc1126_ec_dump to dump it from the
vendor firmware.
 
||
|- bgcolor="#eeeeee"
| H8_BEEP_ON_DEATH || ec/lenovo/h8 || bool || Beep on fatal error ||
Beep when encountered a fatal error.
 
||
|- bgcolor="#eeeeee"
| H8_FLASH_LEDS_ON_DEATH || ec/lenovo/h8 || bool || Flash LEDs on fatal error ||
Flash all LEDs when encountered a fatal error.
 
||
|- bgcolor="#eeeeee"
| H8_SUPPORT_BT_ON_WIFI || ec/lenovo/h8 || bool || Support bluetooth on wifi cards ||
Disable BDC detection and assume bluetooth is installed. Required for
bluetooth on wifi cards, as it's not possible to detect it in coreboot.
 
||
|- bgcolor="#eeeeee"
| EC_RODA_IT8518 || ec/roda/it8518 || bool ||  ||
Interface to IT8518 embedded controller in Roda notebooks.
 
||
||
|- bgcolor="#eeeeee"
| EC_SMSC_MEC1308 || ec/smsc/mec1308 || bool ||  ||
Shared memory mailbox interface to SMSC MEC1308 Embedded Controller.
 
||
||
|- bgcolor="#eeeeee"
| EC_PURISM_LIBREM || ec/purism/librem || bool ||  ||
Purism Librem EC
 
||
||
|- bgcolor="#eeeeee"
| EC_COMPAL_ENE932 || ec/compal/ene932 || bool ||  ||
Interface to COMPAL ENE932 Embedded Controller.
 
||
||
|- bgcolor="#eeeeee"
| EC_KONTRON_IT8516E || ec/kontron/it8516e || bool ||  ||
Kontron uses an ITE IT8516E on the KTQM77. Its firmware might
come from Fintek (mentioned as Finte*c* somewhere in their Linux
driver).
The KTQM77 is an embedded board and the IT8516E seems to be
only used for fan control and GPIO.
 
||
||
|- bgcolor="#eeeeee"
| || || (comment) || || Intel FSP ||
|- bgcolor="#eeeeee"
| HAVE_FSP_BIN || drivers/intel/fsp1_0 || bool || Use Intel Firmware Support Package ||
Select this option to add an Intel FSP binary to
the resulting coreboot image.
 
Note: Without this binary, coreboot builds relying on the FSP
will not boot
 
||
|- bgcolor="#eeeeee"
| FSP_FILE || drivers/intel/fsp1_0 || string || Intel FSP binary path and filename ||
The path and filename of the Intel FSP binary for this platform.
 
||
|- bgcolor="#eeeeee"
| FSP_LOC || drivers/intel/fsp1_0 || hex || Intel FSP Binary location in CBFS ||
The location in CBFS that the FSP is located. This must match the
value that is set in the FSP binary.  If the FSP needs to be moved,
rebase the FSP with Intel's BCT (tool).
 
||
|- bgcolor="#eeeeee"
| ENABLE_FSP_FAST_BOOT || drivers/intel/fsp1_0 || bool || Enable Fast Boot ||
Enabling this feature will force the MRC data to be cached in NV
storage to be used for speeding up boot time on future reboots
and/or power cycles.
 
||
|- bgcolor="#eeeeee"
| ENABLE_MRC_CACHE || drivers/intel/fsp1_0 || bool ||  ||
Enabling this feature will cause MRC data to be cached in NV storage.
This can either be used for fast boot, or just because the FSP wants
it to be saved.
 
||
|- bgcolor="#eeeeee"
| MRC_CACHE_FMAP || drivers/intel/fsp1_0 || bool || Use MRC Cache in FMAP ||
Use the region "RW_MRC_CACHE" in FMAP instead of "mrc.cache" in CBFS.
You must define a region in your FMAP named "RW_MRC_CACHE".
 
||
|- bgcolor="#eeeeee"
| MRC_CACHE_SIZE || drivers/intel/fsp1_0 || hex || Fast Boot Data Cache Size ||
This is the amount of space in NV storage that is reserved for the
fast boot data cache storage.
 
WARNING: Because this area will be erased and re-written, the size
should be a full sector of the flash ROM chip and nothing else should
be included in CBFS in any sector that the fast boot cache data is in.
 
||
|- bgcolor="#eeeeee"
| VIRTUAL_ROM_SIZE || drivers/intel/fsp1_0 || hex || Virtual ROM Size ||
This is used to calculate the offset of the MRC data cache in NV
Storage for fast boot.  If in doubt, leave this set to the default
which sets the virtual size equal to the ROM size.
 
Example: Cougar Canyon 2 has two 8 MB SPI ROMs.  When the SPI ROMs are
loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB.  When
the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM
size is 16 MB.
 
||
|- bgcolor="#eeeeee"
| CACHE_ROM_SIZE_OVERRIDE || drivers/intel/fsp1_0 || hex || Cache ROM Size ||
This is the size of the cachable area that is passed into the FSP in
the early initialization.  Typically this should be the size of the CBFS
area, but the size must be a power of 2 whereas the CBFS size does not
have this limitation.
 
||
|- bgcolor="#eeeeee"
| USE_GENERIC_FSP_CAR_INC || drivers/intel/fsp1_0 || bool ||  ||
The chipset can select this to use a generic cache_as_ram.inc file
that should be good for all FSP based platforms.
 
||
|- bgcolor="#eeeeee"
| FSP_USES_UPD || drivers/intel/fsp1_0 || bool ||  ||
If this FSP uses UPD/VPD data regions, select this in the chipset Kconfig.
||
|- bgcolor="#eeeeee"
| HAVE_INTEL_FIRMWARE || southbridge/intel/common/firmware || bool ||  ||
Chipset uses the Intel Firmware Descriptor to describe the
layout of the SPI ROM chip.
 
||
|- bgcolor="#eeeeee"
| || || (comment) || || Intel Firmware ||
|- bgcolor="#eeeeee"
| HAVE_IFD_BIN || southbridge/intel/common/firmware || bool || Add Intel descriptor.bin file ||
The descriptor binary
 
||
|- bgcolor="#eeeeee"
| EM100 || southbridge/intel/common/firmware || bool || Configure IFD for EM100 usage ||
Set SPI frequency to 20MHz and disable Dual Output Fast Read Support
 
||
|- bgcolor="#eeeeee"
| HAVE_ME_BIN || southbridge/intel/common/firmware || bool || Add Intel ME/TXE firmware ||
The Intel processor in the selected system requires a special firmware
for an integrated controller.  This might be called the Management
Engine (ME), the Trusted Execution Engine (TXE) or something else
depending on the chip. This firmware might or might not be available
in coreboot's 3rdparty/blobs repository. If it is not and if you don't
have access to the firmware from elsewhere, you can still build
coreboot without it. In this case however, you'll have to make sure
that you don't overwrite your ME/TXE firmware on your flash ROM.
 
||
|- bgcolor="#eeeeee"
| CHECK_ME || southbridge/intel/common/firmware || bool || Verify the integrity of the supplied ME/TXE firmware ||
Verify the integrity of the supplied Intel ME/TXE firmware before
proceeding with the build, in order to prevent an accidental loading
of a corrupted ME/TXE image.
 
||
|- bgcolor="#eeeeee"
| USE_ME_CLEANER || southbridge/intel/common/firmware || bool || Strip down the Intel ME/TXE firmware ||
Use me_cleaner to remove all the non-fundamental code from the Intel
ME/TXE firmware.
The resulting Intel ME/TXE firmware will have only the code
responsible for the very basic hardware initialization, leaving the
ME/TXE subsystem essentially in a disabled state.
 
Don't flash a modified ME/TXE firmware and a new coreboot image at the
same time, test them in two different steps.
 
WARNING: this tool isn't based on any official Intel documentation but
only on reverse engineering and trial &amp; error.
 
See the project's page
https://github.com/corna/me_cleaner
or the wiki
https://github.com/corna/me_cleaner/wiki/How-to-apply-me_cleaner
https://github.com/corna/me_cleaner/wiki/How-does-it-work%3F
https://github.com/corna/me_cleaner/wiki/me_cleaner-status
for more info about this tool
 
If unsure, say N.
 
||
|- bgcolor="#eeeeee"
| || || (comment) || || Please test the modified ME/TXE firmware and coreboot in two steps ||
|- bgcolor="#eeeeee"
| HAVE_GBE_BIN || southbridge/intel/common/firmware || bool || Add gigabit ethernet firmware ||
The integrated gigabit ethernet controller needs a firmware file.
Select this if you are going to use the PCH integrated controller
and have the firmware.
 
||
|- bgcolor="#eeeeee"
| HAVE_EC_BIN || southbridge/intel/common/firmware || bool || Add EC firmware ||
The embedded controller needs a firmware file.
 
Select this if you are going to use the PCH integrated controller
and have the EC firmware. EC firmware will be added to final image
through ifdtool.
 
||
|- bgcolor="#eeeeee"
| BUILD_WITH_FAKE_IFD || southbridge/intel/common/firmware || bool || Build with a fake IFD ||
If you don't have an Intel Firmware Descriptor (descriptor.bin) for your
board, you can select this option and coreboot will build without it.
The resulting coreboot.rom will not contain all parts required
to get coreboot running on your board. You can however write only the
BIOS section to your board's flash ROM and keep the other sections
untouched. Unfortunately the current version of flashrom doesn't
support this yet. But there is a patch pending [1].
 
WARNING: Never write a complete coreboot.rom to your flash ROM if it
was built with a fake IFD. It just won't work.
 
[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
 
||
|- bgcolor="#eeeeee"
| IFD_BIOS_SECTION || southbridge/intel/common/firmware || string || BIOS Region Starting:Ending addresses within the ROM ||
The BIOS region is typically the size of the CBFS area, and is located
at the end of the ROM space.
 
For an 8MB ROM with a 3MB CBFS area, this would look like:
0x00500000:0x007fffff
 
||
|- bgcolor="#eeeeee"
| IFD_ME_SECTION || southbridge/intel/common/firmware || string || ME/TXE Region Starting:Ending addresses within the ROM ||
The ME/TXE region typically starts at around 0x1000 and often fills the
ROM space not used by CBFS.
 
For an 8MB ROM with a 3MB CBFS area, this might look like:
0x00001000:0x004fffff
 
||
|- bgcolor="#eeeeee"
| IFD_GBE_SECTION || southbridge/intel/common/firmware || string || GBE Region Starting:Ending addresses within the ROM ||
The Gigabit Ethernet ROM region is used when an Intel NIC is built into
the Southbridge/SOC and the platform uses this device instead of an external
PCIe NIC.  It will be located between the ME/TXE and the BIOS region.
 
Leave this empty if you're unsure.
 
||
|- bgcolor="#eeeeee"
| IFD_PLATFORM_SECTION || southbridge/intel/common/firmware || string || Platform Region Starting:Ending addresses within the Rom ||
The Platform region is used for platform specific data.
It will be located between the ME/TXE and the BIOS region.
 
Leave this empty if you're unsure.
 
||
|- bgcolor="#eeeeee"
| LOCK_MANAGEMENT_ENGINE || southbridge/intel/common/firmware || bool || Lock ME/TXE section ||
The Intel Firmware Descriptor supports preventing write accesses
from the host to the ME or TXE section in the firmware
descriptor. If the section is locked, it can only be overwritten
with an external SPI flash programmer. You will want this if you
want to increase security of your ROM image once you are sure
that the ME/TXE firmware is no longer going to change.
 
If unsure, say N.
 
||
|- bgcolor="#eeeeee"
| CBFS_SIZE || southbridge/intel/common/firmware || hex ||  ||
Reduce CBFS size to give room to the IFD blobs.
 
||
|- bgcolor="#eeeeee"
| UDK_VERSION || vendorcode/intel || int ||  ||
UEFI Development Kit version for Platform
 
||
||
|- bgcolor="#6699dd"
! align="left" | Menu: AMD Platform Initialization || || || ||
|- bgcolor="#eeeeee"
| None || vendorcode/amd || None || AGESA source ||
Select the method for including the AMD Platform Initialization
code into coreboot.  Platform Initialization code is required for
all AMD processors.
 
||
|- bgcolor="#eeeeee"
| CPU_AMD_AGESA_BINARY_PI || vendorcode/amd || bool || binary PI ||
Use a binary PI package.  Generally, these will be stored in the
"3rdparty/blobs" directory.  For some processors, these must be obtained
directly from AMD Embedded Processors Group
(http://www.amdcom/embedded).
 
||
|- bgcolor="#eeeeee"
| CPU_AMD_AGESA_OPENSOURCE || vendorcode/amd || bool || open-source AGESA ||
Build the PI package ("AGESA") from source code in the "vendorcode"
directory.
 
||
|- bgcolor="#eeeeee"
| AGESA_BINARY_PI_VENDORCODE_PATH || vendorcode/amd/pi || string || AGESA PI directory path ||
Specify where to find the AGESA header files
for AMD platform initialization.
 
||
|- bgcolor="#eeeeee"
| AGESA_BINARY_PI_FILE || vendorcode/amd/pi || string || AGESA PI binary file name ||
Specify the binary file to use for AMD platform initialization.
 
||
|- bgcolor="#eeeeee"
| AGESA_BINARY_PI_AS_STAGE || vendorcode/amd/pi || bool || AGESA Binary PI is added as stage to CBFS. ||
AGESA will be added as a stage utilizing --xip cbfstool options
as needed relocating the image to the proper location in memory-mapped
cpu address space. It's required that the file be in ELF format
containing the relocations necessary for relocating at runtime.
 
||
|- bgcolor="#eeeeee"
| AGESA_SPLIT_MEMORY_FILES || vendorcode/amd/pi || bool || Split AGESA Binary PI into pre- and post-memory files. ||
Specifies that AGESA is split into two binaries for pre- and
post-memory.
 
||
|- bgcolor="#eeeeee"
| AGESA_PRE_MEMORY_BINARY_PI_FILE || vendorcode/amd/pi || string ||  ||
Specify the binary file to use for pre-memory AMD platform
initialization.
 
||
|- bgcolor="#eeeeee"
| AGESA_POST_MEMORY_BINARY_PI_FILE || vendorcode/amd/pi || string ||  ||
Specify the binary file to use for post-memory AMD platform
initialization.
 
||
|- bgcolor="#eeeeee"
| AGESA_BINARY_PI_LOCATION || vendorcode/amd/pi || hex || AGESA PI binary address in ROM ||
Specify the ROM address at which to store the binary Platform
Initialization code.
 
||
 
|- bgcolor="#6699dd"
! align="left" | Menu: ChromeOS || || || ||
|- bgcolor="#eeeeee"
| CHROMEOS || vendorcode/google/chromeos || bool || Build for ChromeOS ||
Enable ChromeOS specific features like the GPIO sub table in
the coreboot table. NOTE: Enabling this option on an unsupported
board will most likely break your build.
 
||
|- bgcolor="#eeeeee"
| NO_TPM_RESUME || vendorcode/google/chromeos || bool ||  ||
On some boards the TPM stays powered up in S3. On those
boards, booting Windows will break if the TPM resume command
is sent during an S3 resume.
 
||
|- bgcolor="#eeeeee"
| HAVE_REGULATORY_DOMAIN || vendorcode/google/chromeos || bool || Add regulatory domain methods ||
This option is needed to add ACPI regulatory domain methods
 
||
|- bgcolor="#eeeeee"
| CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME || vendorcode/google/chromeos || bool ||  ||
Disable the platform heirarchy on resume path if the firmware
is involved in resume. The hierarchy is disabled prior to jumping
to the OS.  Note that this option is sepcific to TPM2 boards.
This option is auto selected if CHROMEOS because it matches with
vboot_reference model which disables the platform hierarchy in
the boot loader. However, those operations need to be symmetric
on normal boot as well as resume and coreboot is only involved
in the resume piece w.r.t. the platform hierarchy.
 
||
 
|- bgcolor="#eeeeee"
| GOOGLE_SMBIOS_MAINBOARD_VERSION || vendorcode/google || bool ||  ||
Provide a common implementation for mainboard version,
which returns a formatted 'rev%d' board_id() string.
 
||
||
|- bgcolor="#eeeeee"
| ARCH_RISCV_COMPRESSED || arch/riscv || bool ||  ||
Enable this option if your RISC-V processor supports compressed
instructions (RVC). Currently, this enables RVC for all stages.
 
||
|- bgcolor="#eeeeee"
| ARCH_ARMV8_EXTENSION || arch/arm64/armv8 || int ||  ||
Specify ARMv8 extension, for example '1' for ARMv8.1, to control the
'-march' option passed into the compiler. Defaults to 0 for vanilla
ARMv8 but may be overridden in the SoC's Kconfig.
 
All ARMv8 implementations are downwards-compatible, so this does not
need to be changed unless specific features (e.g. new instructions)
are used by the SoC's coreboot code.
 
||
 
||
|- bgcolor="#eeeeee"
| ARM64_SECURE_OS_FILE || arch/arm64 || string || Secure OS binary file ||
Secure OS binary file.
 
||
|- bgcolor="#eeeeee"
| ARM64_A53_ERRATUM_843419 || arch/arm64 || bool ||  ||
Some early Cortex-A53 revisions had a hardware bug that results in
incorrect address calculations in rare cases. This option enables a
linker workaround to avoid those cases if your toolchain supports it.
Should be selected automatically by SoCs that are affected.
 
||
||
|- bgcolor="#eeeeee"
| USE_MARCH_586 || arch/x86 || bool ||  ||
Allow a platform or processor to select to be compiled using
the '-march=i586' option instead of the typical '-march=i686'
 
||
|- bgcolor="#eeeeee"
| CBMEM_TOP_BACKUP || arch/x86 || bool ||  ||
Platform implements non-volatile storage to cache cbmem_top()
over stage transitions and optionally also over S3 suspend.
 
||
|- bgcolor="#eeeeee"
| LATE_CBMEM_INIT || arch/x86 || bool ||  ||
Enable this in chipset's Kconfig if northbridge does not implement
early cbmem_top() call for romstage. CBMEM tables will be allocated
late in ramstage, after PCI devices resources are known.
 
WARNING: Late CBMEM initialization is deprecated. Platforms that
don't support early CBMEM initialization will be removed after
the release of coreboot 4.7.
 
||
|- bgcolor="#eeeeee"
| PRERAM_CBMEM_CONSOLE_SIZE || arch/x86 || hex ||  ||
Increase this value if preram cbmem console is getting truncated
 
||
|- bgcolor="#eeeeee"
| EARLY_EBDA_INIT || arch/x86 || bool ||  ||
Initialize BIOS EBDA area early in romstage to allow bootloader to
use this region for storing data which can be available across
various stages. If user is selecting this option then its users
responsibility to perform EBDA initialization call during romstage.
 
||
|- bgcolor="#eeeeee"
| BOOTBLOCK_DEBUG_SPINLOOP || arch/x86 || bool ||  ||
Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait
for a JTAG debugger to break into the execution sequence.
 
||
|- bgcolor="#eeeeee"
| BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP || arch/x86 || bool ||  ||
Select this value to provide a routine to save the BIST and timestamp
values.  The default code places the BIST value in MM0 and the
timestamp value in MM2:MM1.  Another file is necessary when the CPU
does not support the MMx register set.
 
||
|- bgcolor="#eeeeee"
| VERSTAGE_DEBUG_SPINLOOP || arch/x86 || bool ||  ||
Add a spin (JMP .) in assembly_entry.S during early verstage to wait
for a JTAG debugger to break into the execution sequence.
 
||
|- bgcolor="#eeeeee"
| ROMSTAGE_DEBUG_SPINLOOP || arch/x86 || bool ||  ||
Add a spin (JMP .) in assembly_entry.S during early romstage to wait
for a JTAG debugger to break into the execution sequence.
 
||
|- bgcolor="#eeeeee"
| SKIP_MAX_REBOOT_CNT_CLEAR || arch/x86 || bool || Do not clear reboot count after successful boot ||
Do not clear the reboot count immediately after successful boot.
Set to allow the payload to control normal/fallback image recovery.
Note that it is the responsibility of the payload to reset the
normal boot bit to 1 after each successsful boot.
 
||
|- bgcolor="#eeeeee"
| ACPI_CPU_STRING || arch/x86 || string ||  ||
Sets the ACPI name string in the processor scope as written by
the acpigen function. Default is \_PR.CPxx. Note that you need
the \ escape character in the string.
 
||
|- bgcolor="#eeeeee"
| COLLECT_TIMESTAMPS_NO_TSC || arch/x86 || bool ||  ||
Use a non-TSC platform-dependent source for timestamps.
 
||
|- bgcolor="#eeeeee"
| COLLECT_TIMESTAMPS_TSC || arch/x86 || bool ||  ||
Use the TSC as the timestamp source.
 
||
|- bgcolor="#eeeeee"
| PAGING_IN_CACHE_AS_RAM || arch/x86 || bool ||  ||
Chipsets scan select this option to preallocate area in cache-as-ram
for storing paging data structures. PAE paging is currently the
only thing being supported.
 
||
|- bgcolor="#eeeeee"
| NUM_CAR_PAGE_TABLE_PAGES || arch/x86 || int ||  ||
The number of 4KiB pages that should be pre-allocated for page tables.
 
||
 
|- bgcolor="#6699dd"
! align="left" | Menu: Devices || || || ||
|- bgcolor="#eeeeee"
| HAVE_VGA_TEXT_FRAMEBUFFER || device || bool ||  ||
Selected by graphics drivers that support legacy VGA text mode.
 
||
|- bgcolor="#eeeeee"
| HAVE_VBE_LINEAR_FRAMEBUFFER || device || bool ||  ||
Selected by graphics drivers that can set up a VBE linear-framebuffer
mode.
 
||
|- bgcolor="#eeeeee"
| HAVE_LINEAR_FRAMEBUFFER || device || bool ||  ||
Selected by graphics drivers that can set up a generic linear
framebuffer.
 
||
|- bgcolor="#eeeeee"
| HAVE_FSP_GOP || device || bool ||  ||
Selected by drivers that support to run a blob that implements
the Graphics Output Protocol (GOP).
 
||
|- bgcolor="#eeeeee"
| MAINBOARD_HAS_NATIVE_VGA_INIT || device || bool ||  ||
Selected by mainboards / drivers that provide native graphics
init within coreboot.
 
||
|- bgcolor="#eeeeee"
| MAINBOARD_FORCE_NATIVE_VGA_INIT || device || bool ||  ||
Selected by mainboards / chipsets whose graphics driver can't or
shouldn't be disabled.
 
||
|- bgcolor="#eeeeee"
| MAINBOARD_HAS_LIBGFXINIT || device || bool ||  ||
Selected by mainboards that implement support for `libgfxinit`.
Usually this requires a list of ports to be probed for displays.
 
||
|- bgcolor="#eeeeee"
| MAINBOARD_DO_NATIVE_VGA_INIT || device || bool || Use native graphics init ||
Some mainboards, such as the Google Link, allow initializing the
display without the need of a binary only VGA OPROM. Enabling this
option may be faster, but also lacks flexibility in setting modes.
 
||
|- bgcolor="#eeeeee"
| MAINBOARD_USE_LIBGFXINIT || device || bool || Use libgfxinit ||
Use the SPARK library `libgfxinit` for the native graphics
initialization. This requires an Ada toolchain.
 
||
|- bgcolor="#eeeeee"
| VGA_ROM_RUN || device || bool || Run VGA Option ROMs ||
Execute VGA Option ROMs in coreboot if found. This can be used
to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS
payload.
 
When using a SeaBIOS payload it runs all option ROMs with much
more complete BIOS interrupt services available than coreboot,
which some option ROMs require in order to function correctly.


|- bgcolor="#dddddd"
||
| Apple
|- bgcolor="#eeeeee"
| [[Board:apple/macbook21|Macbook2,1]]
| RUN_FSP_GOP || device || bool || Run a GOP driver ||  
| style="background:#FFff00" | [[#apple/macbook21|2014-08-17T22:05:53Z]]
Some platforms (e.g. Intel Braswell and Skylake/Kaby Lake) support
| Intel® I945
to run a GOP blob. This option enables graphics initialization with
Intel® SUBTYPE I945GM
such a blob.
| Intel® I82801GX
|  
| Intel® Core™ 2 Duo Mobile, Core™ Duo/Solo, Celeron® M
| Socket mPGA478
| SOIC-8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| Apple
|- bgcolor="#eeeeee"
| [[Board:apple/macbookair4_2|MacBookAir4,2]]
| NO_GFX_INIT || device || bool || None ||  
| style="background:red" | Unknown
Select this to not perform any graphics initialization in
| Intel® SANDYBRIDGE
coreboot. This is useful if the payload (e.g. SeaBIOS) can
| Intel® BD82X6X
initialize graphics or if pre-boot graphics are not required.
|
| Intel® 2nd Gen (Sandybridge) Core i3/i5/i7
| Socket RPGA989
| WSON-8
| SPI
| style="background:red" | N
| style="background:red" | N
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://en.getac.com/AP/MISC/M0100/F0110_DownLoad_File.aspx?bullid=AllBull&fileid=105261&DomainLang=100020&DomainRegion=100027 Getac]
| S3_VGA_ROM_RUN || device || bool || Re-run VGA Option ROMs on S3 resume ||  
| [[Board:getac/p470|P470]]
Execute VGA Option ROMs in coreboot when resuming from S3 suspend.
| style="background:#DBff00" | [[#getac/p470|2017-10-09T20:20:40Z]]
| Intel® I945
Intel® SUBTYPE I945GM
| Intel® I82801GX
TI PCIXX12
| SMSC® FDC37N972
SMSC® SIO10N268
| Intel® Core™ 2 Duo Mobile, Core™ Duo/Solo, Celeron® M
| Socket mPGA478
| ?
| SPI
| ?
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
When using a SeaBIOS payload it runs all option ROMs with much
| Google
more complete BIOS interrupt services available than coreboot,
( Google )
which some option ROMs require in order to function correctly.
| [[Board:google/auron|Auron Broadwell Reference Board]]
| style="background:red" | Unknown
|
|
|
|
|
| SOIC-8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
If unsure, say N when using SeaBIOS as payload, Y otherwise.
| [http://h10025.www1.hp.com/ewfrf/wc/product?product=5389124&cc=us&dlc=en&lc=en&jumpid=reg_r1002_usen_c-001_title_r0005 Google]
( HP )
| [[Board:google/butterfly|Pavilion Chromebook 14]]
| style="background:#FFff00" | [[#google/butterfly|2014-03-28T20:20:38Z]]
| Intel® IVYBRIDGE
| Intel® C216
|
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
| Socket RPGA989
| SOIC-8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| Google
|- bgcolor="#eeeeee"
( Google )
| ALWAYS_LOAD_OPROM || device || bool || ||  
| [[Board:google/chell|Chell Skylake Reference Board]]
Always load option ROMs if any are found. The decision to run
| style="background:red" | Unknown
the ROM is still determined at runtime, but the distinction
|
between loading and not running comes into play for CHROMEOS.
|
|  
|  
|  
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
An example where this is required is that VBT (Video BIOS Tables)
| Google
are needed for the kernel's display driver to know how a piece of
( Google )
hardware is configured to be used.
| [[Board:google/cyan|Cyan Braswell baseboard]]
| style="background:red" | Unknown
|
|
|
|
|
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| Google
|- bgcolor="#eeeeee"
( Samsung )
| ALWAYS_RUN_OPROM || device || bool || ||  
| [[Board:google/daisy|ARM Chromebook]]
Always uncondtionally run the option regardless of other
| style="background:red" | Unknown
policies.
|  
|  
|  
| Samsung Exynos 5250
| ?
| SOIC-8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| Google
|- bgcolor="#eeeeee"
( Google )
| ON_DEVICE_ROM_LOAD || device || bool || Load Option ROMs on PCI devices ||  
| [[Board:google/eve|Eve]]
Load Option ROMs stored on PCI/PCIe/AGP VGA devices in coreboot.
| style="background:red" | Unknown
|  
|  
|  
|  
|  
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
If disabled, only Option ROMs stored in CBFS will be executed by
| Google
coreboot. If you are concerned about security, you might want to
( Google )
disable this option, but it might leave your system in a state of
| [[Board:google/glados|Glados Skylake Reference Board]]
degraded functionality.
| style="background:red" | Unknown
|
|
|
|
|
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
When using a SeaBIOS payload it runs all option ROMs with much
| Google
more complete BIOS interrupt services available than coreboot,
( Google )
which some option ROMs require in order to function correctly.
| [[Board:google/lars|Lars Skylake chromebook]]
| style="background:red" | Unknown
|
|
|
|
|
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
If unsure, say N when using SeaBIOS as payload, Y otherwise.
| [http://www.google.com/intl/en/chrome/devices/chromebooks.html#pixel Google]
| [[Board:google/link|Chromebook Pixel]]
| style="background:red" | Unknown
| Intel® IVYBRIDGE
| Intel® C216
|
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
| Socket RPGA989
| SOIC-8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| Google
|- bgcolor="#eeeeee"
| [[Board:google/nyan|Nyan]]
| PCI_OPTION_ROM_RUN_REALMODE || device || bool || Native mode ||  
| style="background:red" | Unknown
If you select this option, PCI Option ROMs will be executed
|
natively on the CPU in real mode. No CPU emulation is involved,
|  
so this is the fastest, but also the least secure option.
|  
(only works on x86/x64 systems)
|  
|  
| ?
| SPI
| ?
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| Google
|- bgcolor="#eeeeee"
| [[Board:google/nyan_big|Nyan Big]]
| PCI_OPTION_ROM_RUN_YABEL || device || bool || Secure mode ||  
| style="background:red" | Unknown
If you select this option, the x86emu CPU emulator will be used to
|  
execute PCI Option ROMs.
|  
|  
|  
|  
| ?
| SPI
| ?
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
This option prevents Option ROMs from doing dirty tricks with the
| Google
system (such as installing SMM modules or hypervisors), but it is
( Google )
also significantly slower than the native Option ROM initialization
| [[Board:google/nyan_blaze|Nyan Blaze Nvidia Tegra T124 Chromebook]]
method.
| style="background:red" | Unknown
|
|
|
|
|
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
This is the default choice for non-x86 systems.
| Google
( Google )
| [[Board:google/oak|Oak MediaTek MT8173 reference board]]
| style="background:red" | Unknown
|
|
|
|
|
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| Google
|- bgcolor="#eeeeee"
( Google )
| YABEL_PCI_ACCESS_OTHER_DEVICES || device || bool || Allow Option ROMs to access other devices ||  
| [[Board:google/octopus|Octopus GLK Reference Board]]
Per default, YABEL only allows Option ROMs to access the PCI device
| style="background:red" | Unknown
that they are associated with. However, this causes trouble for some
|  
onboard graphics chips whose Option ROM needs to reconfigure the
|  
north bridge.
|  
|  
|
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| Google
|- bgcolor="#eeeeee"
( Acer )
| YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG || device || bool || Fake success on writing other device's config space ||  
| [[Board:google/parrot|C7 Chromebook]]
By default, YABEL aborts when the Option ROM tries to write to other
| style="background:#FFff00" | [[#google/parrot|2014-09-13T00:21:02Z]]
devices' config spaces. With this option enabled, the write doesn't
| Intel® IVYBRIDGE
follow through, but the Option ROM is allowed to go on.
| Intel® C216
This can create issues such as hanging Option ROMs (if it depends on
|  
that other register changing to the written value), so test for
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
impact before using this option.
| Socket RPGA989
| SOIC-8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| Google
|- bgcolor="#eeeeee"
| [[Board:google/peach_pit|Peach Pit]]
| YABEL_VIRTMEM_LOCATION || device || hex || Location of YABEL's virtual memory ||  
| style="background:red" | Unknown
YABEL requires 1MB memory for its CPU emulation. This memory is
|  
normally located at 16MB.
|  
|  
| Samsung Exynos 5420
| ?
| ?
| SPI
| ?
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| Google
|- bgcolor="#eeeeee"
( Google )
| YABEL_DIRECTHW || device || bool || Direct hardware access ||  
| [[Board:google/poppy|Poppy Kabylake Reference Board]]
YABEL consists of two parts: It uses x86emu for the CPU emulation and
| style="background:red" | Unknown
additionally provides a PC system emulation that filters bad device
|  
and memory access (such as PCI config space access to other devices
|  
than the initialized one).
|  
|  
|
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
When choosing this option, x86emu will pass through all hardware
| Google
accesses to memory and I/O devices to the underlying memory and I/O
( Google )
addresses. While this option prevents Option ROMs from doing dirty
| [[Board:google/rambi|Rambi Baytrail Reference Board]]
tricks with the CPU (such as installing SMM modules or hypervisors),
| style="background:red" | Unknown
they can still access all devices in the system.
|
Enable this option for a good compromise between security and speed.
|
|
|
|
| SOIC-8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| Google
|- bgcolor="#6699dd"
( Google )
! align="left" | Menu: Display || || || ||
| [[Board:google/reef|Reef Apollolake Reference Board]]
|- bgcolor="#eeeeee"
| style="background:red" | Unknown
| FRAMEBUFFER_SET_VESA_MODE || device || bool || Set framebuffer graphics resolution ||  
|  
Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console)
|  
|  
|  
|  
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| Google
|- bgcolor="#eeeeee"
| [[Board:google/rotor|rotor]]
| FRAMEBUFFER_SET_VESA_MODE || device || bool || framebuffer graphics resolution ||  
| style="background:red" | Unknown
This option sets the resolution used for the coreboot framebuffer (and
|  
bootsplash screen).
|  
|  
|  
|  
| ?
| parallel flash
| ?
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| Google
|- bgcolor="#eeeeee"
( Google )
| BOOTSPLASH || device || bool || Show graphical bootsplash ||  
| [[Board:google/slippy|Slippy Haswell Chromebook Reference device]]
This option shows a graphical bootsplash screen. The graphics are
| style="background:#FFff00" | [[#google/slippy|2017-04-04T20:03:46Z]]
loaded from the CBFS file bootsplash.jpg.
| Intel® HASWELL
| Intel® LYNXPOINT
|
| Intel® 4th Gen (Haswell) Core i3/i5/i7
| ?
| SOIC-8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
You can either specify the location and file name of the
| Google
image in the 'General' section or add it manually to CBFS, using,
( Lenovo )
for example, cbfstool.
| [[Board:google/stout|Thinkpad X131e Chromebook]]
| style="background:red" | Unknown
| Intel® IVYBRIDGE
| Intel® C216
|
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
| Socket RPGA989
| SOIC-8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| Google
|- bgcolor="#eeeeee"
( Google )
| VGA_TEXT_FRAMEBUFFER || device || bool || Legacy VGA text mode ||  
| [[Board:google/zoombini|Zoombini Cannonlake Reference Board]]
If this option is enabled, coreboot will initialize graphics in
| style="background:red" | Unknown
legacy VGA text mode or, if a VGA BIOS is used and a VESA mode set,
|
switch to text mode before handing control to a payload.
|
|  
|  
|  
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [https://support.hp.com/us-en/product/HP-EliteBook-2570p-Notebook-PC/5259393 HP]
| VBE_LINEAR_FRAMEBUFFER || device || bool || VESA framebuffer ||  
| [[Board:hp/2570p|EliteBook 2570p]]
This option keeps the framebuffer mode set after coreboot finishes
| style="background:#6Cff00" | [[#hp/2570p|2018-01-29T09:41:35Z]]
execution. If this option is enabled, coreboot will pass a
| Intel® IVYBRIDGE
framebuffer entry in its coreboot table and the payload will need a
| Intel® C216
compatible driver.
|  
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
| Socket RPGA989
| SOIC-16
| SPI
| style="background:red" | N
| style="background:red" | N
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [https://support.hp.com/us-en/product/hp-elitebook-2760p-tablet-pc/5071191 HP]
| GENERIC_LINEAR_FRAMEBUFFER || device || bool || Linear \"high-resolution\" framebuffer ||  
| [[Board:hp/2760p|EliteBook 2760p]]
This option enables a high-resolution, linear framebuffer. If this
| style="background:#E4ff00" | [[#hp/2760p|2017-09-30T20:34:28Z]]
option is enabled, coreboot will pass a framebuffer entry in its
| Intel® SANDYBRIDGE
coreboot table and the payload will need a compatible driver.
| Intel® BD82X6X
 
|
||
| Intel® 2nd Gen (Sandybridge) Core i3/i5/i7
| Socket RPGA989
| SOIC-8
| SPI
| style="background:lime" | Y
| style="background:red" | N
| —


|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [https://support.hp.com/us-en/product/HP-EliteBook-8460p-Notebook-PC/5056942 HP]
| PCIEXP_COMMON_CLOCK || device || bool || Enable PCIe Common Clock ||  
| [[Board:hp/8460p|EliteBook 8460p]]
Detect and enable Common Clock on PCIe links.
| style="background:#B4ff00" | [[#hp/8460p|2017-11-18T12:59:33Z]]
| Intel® SANDYBRIDGE
| Intel® BD82X6X
| SMSC® LPC47N217
| Intel® 2nd Gen (Sandybridge) Core i3/i5/i7
| Socket RPGA989
| SOIC-8
| SPI
| style="background:red" | N
| style="background:red" | N
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [https://support.hp.com/us-en/product/HP-EliteBook-8470p-Notebook-PC/5212907 HP]
| PCIEXP_ASPM || device || bool || Enable PCIe ASPM ||  
| [[Board:hp/8470p|EliteBook 8470p]]
Detect and enable ASPM (Active State Power Management) on PCIe links.
| style="background:#FFff00" | [[#hp/8470p|2017-08-24T12:08:03Z]]
| Intel® IVYBRIDGE
| Intel® C216
| SMSC® LPC47N217
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
| Socket RPGA989
| SOIC-16
| SPI
| style="background:red" | N
| style="background:red" | N
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [https://support.hp.com/us-en/product/HP-EliteBook-8770w-Mobile-Workstation/5257511 HP]
| PCIEXP_CLK_PM || device || bool || Enable PCIe Clock Power Management ||  
| [[Board:hp/8770w|EliteBook 8770w]]
Detect and enable Clock Power Management on PCIe.
| style="background:red" | Unknown
| Intel® IVYBRIDGE
| Intel® C216
| SMSC® LPC47N217
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
| Socket RPGA989
| SOIC-16
| SPI
| style="background:red" | N
| style="background:red" | N
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [https://support.hp.com/us-en/product/hp-elitebook-folio-9470m-ultrabook/5271146/product-info HP]
| PCIEXP_L1_SUB_STATE || device || bool || Enable PCIe ASPM L1 SubState ||  
| [[Board:hp/folio_9470m|EliteBook Folio 9470m]]
Detect and enable ASPM on PCIe links.
| style="background:#34ff00" | [[#hp/folio_9470m|2018-03-26T10:25:58Z]]
| Intel® IVYBRIDGE
| Intel® C216
|  
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
| Socket RPGA989
| SOIC-8
| SPI
| style="background:red" | N
| style="background:red" | N
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| HP
| EARLY_PCI_BRIDGE || device || bool || Early PCI bridge ||  
| [[Board:hp/pavilion_m6_1035dx|Pavilion m6 1035dx]]
While coreboot is executing code from ROM, the coreboot resource
| style="background:#FFff00" | [[#hp/pavilion_m6_1035dx|2014-12-06T10:30:54Z]]
allocator has not been running yet. Hence PCI devices living behind
| AMD Family 15h TN (AGESA)
a bridge are not yet visible to the system.
| AMD AGESA HUDSON
 
|  
This option enables static configuration for a single pre-defined
| AMD Family 15h TN (AGESA)
PCI bridge function on bus 0.
| ?
| SOIC-8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [https://support.hp.com/us-en/product/hp-elitebook-revolve-810-g1-tablet/5298038/product-info HP]
| SUBSYSTEM_VENDOR_ID || device || hex || Override PCI Subsystem Vendor ID ||  
| [[Board:hp/revolve_810_g1|EliteBook Revolve 810 G1]]
This config option will override the devicetree settings for
| style="background:#7Cff00" | [[#hp/revolve_810_g1|2018-01-13T04:50:11Z]]
PCI Subsystem Vendor ID.
| Intel® IVYBRIDGE
| Intel® C216
|  
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
| Socket RPGA989
| SOIC-8
| SPI
| style="background:red" | N
| style="background:red" | N
| —


|- bgcolor="#dddddd"
||
| Intel
|- bgcolor="#eeeeee"
( Intel )
| SUBSYSTEM_DEVICE_ID || device || hex || Override PCI Subsystem Device ID ||  
| [[Board:intel/glkrvp|Glkrvp GLK Reference Board]]
This config option will override the devicetree settings for
| style="background:red" | Unknown
PCI Subsystem Device ID.
|  
|  
|  
|  
|  
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| Intel
|- bgcolor="#eeeeee"
( Intel )
| VGA_BIOS || device || bool || Add a VGA BIOS image ||  
| [[Board:intel/kunimitsu|Kunimitsu Skylake Reference Board]]
Select this option if you have a VGA BIOS image that you would
| style="background:red" | Unknown
like to add to your ROM.
|  
|  
|  
|  
|  
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
You will be able to specify the location and file name of the
| Intel
image later.
( Intel )
| [[Board:intel/strago|Strago Braswell Reference Board]]
| style="background:red" | Unknown
|
|
|
|
|
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Lenovo
| VGA_BIOS_FILE || device || string || VGA BIOS path and filename ||  
| [[Board:lenovo/g505s|LENOVO G505S]]
The path and filename of the file to use as VGA BIOS.
| style="background:#26ff00" | [[#lenovo/g505s|2018-04-09T01:03:12Z]]
| AMD Family 15h TN (AGESA)
| AMD AGESA HUDSON
|  
| AMD Family 15h TN (AGESA)
| ?
| SOIC-8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Lenovo
| VGA_BIOS_ID || device || string || VGA device PCI IDs ||  
| [[Board:lenovo/l520|ThinkPad L520]]
The comma-separated PCI vendor and device ID that would associate
| style="background:red" | Unknown
your VGA BIOS to your video card.
| Intel® SANDYBRIDGE
 
| Intel® BD82X6X
Example: 1106,3230
|
 
| Intel® 2nd Gen (Sandybridge) Core i3/i5/i7
In the above example 1106 is the PCI vendor ID (in hex, but without
| Socket RPGA989
the "0x" prefix) and 3230 specifies the PCI device ID of the
| SOIC-8
video card (also in hex, without "0x" prefix).
| SPI
 
| style="background:red" | N
Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.
| style="background:red" | N
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Lenovo
| INTEL_GMA_ADD_VBT_DATA_FILE || device || bool || Add a Video Bios Table (VBT) binary to CBFS ||  
| [[Board:lenovo/r400|ThinkPad R400]]
Add a VBT data file to CBFS. The VBT describes the integrated
| style="background:#0Aff00" | [[#lenovo/t400|2018-05-06T22:17:02Z]]
GPU and connections, and is needed by the GOP driver integrated into
| Intel® GM45
FSP and the OS driver in order to initialize the display.
| Intel® I82801IX
| NSC PC87382
NSC PC87384
| INTEL_SOCKET_MPGA478MN
| INTEL_SOCKET_MPGA478MN
| SOIC-16 or SOIC-8
| SPI
| style="background:red" | N
| style="background:red" | N
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Lenovo
| INTEL_GMA_VBT_FILE || device || string || VBT binary path and filename ||  
| [[Board:lenovo/s230u|ThinkPad S230U (Twist)]]
The path and filename of the VBT binary.
| style="background:#DCff00" | [[#lenovo/s230u|2017-10-09T07:10:54Z]]
| Intel® IVYBRIDGE
| Intel® C216
|  
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
| Socket RPGA989
| SOIC-8
| SPI
| style="background:red" | N
| style="background:red" | N
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Lenovo
| SOFTWARE_I2C || device || bool || Enable I2C controller emulation in software ||  
| [[Board:lenovo/t400|ThinkPad T400]]
This config option will enable code to override the i2c_transfer
| style="background:#0Aff00" | [[#lenovo/t400|2018-05-06T22:17:02Z]]
routine with a (simple) software emulation of the protocol. This may
| Intel® GM45
be useful for debugging or on platforms where a driver for the real
| Intel® I82801IX
I2C controller is not (yet) available. The platform code needs to
| NSC PC87382
provide bindings to manually toggle I2C lines.
NSC PC87384
 
| INTEL_SOCKET_MPGA478MN
||
| INTEL_SOCKET_MPGA478MN
| SOIC-16
| SPI
| style="background:red" | N
| style="background:red" | N
| —


|- bgcolor="#6699dd"
! align="left" | Menu: Generic Drivers || || || ||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Lenovo
| ELOG || drivers/elog || bool || Support for flash based event log ||  
| [[Board:lenovo/t420|ThinkPad T420]]
Enable support for flash based event logging.
| style="background:#FFff00" | [[#lenovo/t420|2017-04-25T04:15:46Z]]
| Intel® SANDYBRIDGE
| Intel® BD82X6X
|  
| Intel® 2nd Gen (Sandybridge) Core i3/i5/i7
| Socket RPGA988B
| SOIC-8 / WSON-8
| SPI
| style="background:red" | N
| style="background:red" | N
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Lenovo
| ELOG_CBMEM || drivers/elog || bool || Store a copy of ELOG in CBMEM ||  
| [[Board:lenovo/t420s|ThinkPad T420s]]
This option will have ELOG store a copy of the flash event log
| style="background:red" | Unknown
in a CBMEM region and export that address in SMBIOS to the OS.
| Intel® SANDYBRIDGE
This is useful if the ELOG location is not in memory mapped flash,
| Intel® BD82X6X
but it means that events added at runtime via the SMI handler
|  
will not be reflected in the CBMEM copy of the log.
| Intel® 2nd Gen (Sandybridge) Core i3/i5/i7
| Socket RPGA988B
| SOIC-8
| SPI
| style="background:red" | N
| style="background:red" | N
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Lenovo
| ELOG_GSMI || drivers/elog || bool || SMI interface to write and clear event log ||  
| [[Board:lenovo/t430|ThinkPad T430]]
This interface is compatible with the linux kernel driver
| style="background:#2Bff00" | [[#lenovo/t430|2018-04-03T21:38:40Z]]
available with CONFIG_GOOGLE_GSMI and can be used to write
| Intel® IVYBRIDGE
kernel reset/shutdown messages to the event log.
| Intel® C216
|
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
| Socket RPGA989
| SOIC-8
| SPI
| style="background:red" | N
| style="background:red" | N
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Lenovo
| ELOG_BOOT_COUNT || drivers/elog || bool || Maintain a monotonic boot number in CMOS ||  
| [[Board:lenovo/t430s|ThinkPad T430s]]
Store a monotonic boot number in CMOS and provide an interface
| style="background:#B1ff00" | [[#lenovo/t430s|2017-11-21T01:38:42Z]]
to read the current value and increment the counter.  This boot
| Intel® IVYBRIDGE
counter will be logged as part of the System Boot event.
| Intel® C216
|
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
| Socket RPGA989
| SOIC-8 / WSON-8
| SPI
| style="background:red" | N
| style="background:red" | N
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Lenovo
| ELOG_BOOT_COUNT_CMOS_OFFSET || drivers/elog || int || Offset in CMOS to store the boot count ||  
| [[Board:lenovo/t500|ThinkPad T500]]
This value must be greater than 16 bytes so as not to interfere
| style="background:#0Aff00" | [[#lenovo/t400|2018-05-06T22:17:02Z]]
with the standard RTC region.  Requires 8 bytes.
| Intel® GM45
| Intel® I82801IX
| NSC PC87382
NSC PC87384
| INTEL_SOCKET_MPGA478MN
| INTEL_SOCKET_MPGA478MN
| SOIC-16 or SOIC-8
| SPI
| style="background:red" | N
| style="background:red" | N
| —


||
||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Lenovo
| USBDEBUG || drivers/usb || bool || USB 2.0 EHCI debug dongle support ||  
( Lenovo )
This option allows you to use a so-called USB EHCI Debug device
| [[Board:lenovo/t520|ThinkPad T520 baseboard]]
(such as the Ajays NET20DC, AMIDebug RX, or a system using the
| style="background:#FFff00" | [[#lenovo/t520|2016-03-03T08:19:11Z]]
Linux "EHCI Debug Device gadget" driver found in recent kernel)
| Intel® SANDYBRIDGE
to retrieve the coreboot debug messages (instead, or in addition
| Intel® BD82X6X
to, a serial port).
|  
 
| Intel® 2nd Gen (Sandybridge) Core i3/i5/i7
This feature is NOT supported on all chipsets in coreboot!
| Socket RPGA988B
| WSON-8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


It also requires a USB2 controller which supports the EHCI
Debug Port capability.
See https://www.coreboot.org/EHCI_Debug_Port for an up-to-date list
of supported controllers.
If unsure, say N.
||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Lenovo
| USBDEBUG_IN_ROMSTAGE || drivers/usb || bool || Enable early (pre-RAM) usbdebug ||  
| [[Board:lenovo/t530|ThinkPad T530]]
Configuring USB controllers in system-agent binary may cause
| style="background:#FFff00" | [[#lenovo/t530|2014-09-11T14:20:53Z]]
problems to usbdebug. Disabling this option delays usbdebug to
| Intel® IVYBRIDGE
be setup on entry to ramstage.
| Intel® C216
|  
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
| Socket RPGA989
| SOIC-8
| SPI
| style="background:red" | N
| style="background:red" | N
| —


If unsure, say Y.
||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Lenovo
| USBDEBUG_HCD_INDEX || drivers/usb || int || Index for EHCI controller to use with usbdebug ||  
| [[Board:lenovo/t60|T60/T60p]]
Some boards have multiple EHCI controllers with possibly only
| style="background:#80ff00" | [[#lenovo/t60|2018-01-08T19:44:33Z]]
one having the Debug Port capability on an external USB port.
| Intel® I945
Intel® SUBTYPE I945GM
| Intel® I82801GX
TI PCI1X2X
| NSC PC87382
NSC PC87384
| Intel® Core™ 2 Duo Mobile, Core™ Duo/Solo, Celeron® M
| Socket mPGA478
| SOIC-8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


Mapping of this index to PCI device functions is southbridge
specific and mainboard level Kconfig should already provide
a working default value here.
||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Lenovo
| USBDEBUG_DEFAULT_PORT || drivers/usb || int || Default USB port to use as Debug Port ||  
| [[Board:lenovo/x131e|ThinkPad X131e]]
Selects which physical USB port usbdebug dongle is connected to.
| style="background:red" | Unknown
Setting of 0 means to scan possible ports starting from 1.
| Intel® SANDYBRIDGE
 
| Intel® C216
Intel platforms have hardwired the debug port location and this
|
setting makes no difference there.
| Intel® 2nd Gen (Sandybridge) Core i3/i5/i7
 
| Socket RPGA989
Hence, if you select the correct port here, you can speed up
| SOIC-8
your boot time. Which USB port number refers to which actual
| SPI
port on your mainboard (potentially also USB pin headers on
| style="background:red" | N
your mainboard) is highly board-specific, and you'll likely
| style="background:red" | N
have to find out by trial-and-error.
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Lenovo
| USBDEBUG_DONGLE_STD || drivers/usb || bool || USB gadget driver or Net20DC ||  
| [[Board:lenovo/x1_carbon_gen1|ThinkPad X1 carbon gen 1]]
Net20DC, BeagleBone Black, Raspberry Pi Zero W
| style="background:#A3ff00" | [[#lenovo/x1_carbon_gen1|2017-12-05T00:29:49Z]]
| Intel® IVYBRIDGE
| Intel® C216
|  
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
| Socket RPGA989
| SOIC-8
| SPI
| style="background:red" | N
| style="background:red" | N
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Lenovo
| USBDEBUG_DONGLE_BEAGLEBONE || drivers/usb || bool || BeagleBone ||  
| [[Board:lenovo/x200|ThinkPad X200]]
Use this to configure the USB hub on BeagleBone board.
| style="background:#A2ff00" | [[#lenovo/x200|2017-12-05T19:47:14Z]]
Do NOT select this for the BeagleBone Black.
| Intel® GM45
| Intel® I82801IX
| NSC PC87382
| Intel® Core 2 Duo (Penryn)
| Socket P
| SOIC-16 or SOIC-8
| SPI
| style="background:red" | N
| style="background:red" | N
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Lenovo
| USBDEBUG_DONGLE_FTDI_FT232H || drivers/usb || bool || FTDI FT232H UART ||  
| [[Board:lenovo/x201|ThinkPad X201]]
Use this with FT232H usb-to-uart. Configuration is hard-coded
| style="background:#01ff00" | [[#lenovo/x201|2018-05-16T06:19:34Z]]
to use 8n1, no flow control.
| Intel® NEHALEM
| Intel® IBEXPEAK
| NSC PC87382
| Intel® 1st Gen (Nehalem) Core i3/i5/i7
| ?
| SOIC-8
| SPI
| style="background:red" | N
| style="background:red" | N
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Lenovo
| USBDEBUG_DONGLE_FTDI_FT232H_BAUD || drivers/usb || int || FTDI FT232H baud rate ||  
| [[Board:lenovo/x220|ThinkPad X220]]
Select baud rate for FT232H in the range 733..12,000,000. Make
| style="background:#63ff00" | [[#lenovo/x220|2018-02-06T15:30:49Z]]
sure that your receiving side supports the same setting and your
| Intel® SANDYBRIDGE
connection works with it. Multiples of 115,200 seem to be a good
| Intel® C216
choice, and EHCI debug usually can't saturate more than 576,000.
|
| Intel® 2nd Gen (Sandybridge) Core i3/i5/i7
| Socket RPGA989
| SOIC-8
| SPI
| style="background:red" | N
| style="background:red" | N
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Lenovo
| COMMON_CBFS_SPI_WRAPPER || drivers/spi || bool || ||  
| [[Board:lenovo/x230|ThinkPad X230]]
Use common wrapper to interface CBFS to SPI bootrom.
| style="background:#01ff00" | [[#lenovo/x230|2018-05-16T07:45:28Z]]
| Intel® IVYBRIDGE
| Intel® C216
|  
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
| Socket RPGA989
| SOIC-8
| SPI
| style="background:red" | N
| style="background:red" | N
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Lenovo
| SPI_FLASH || drivers/spi || bool || ||  
| [[Board:lenovo/x60|X60/X60s]]
Select this option if your chipset driver needs to store certain
| style="background:#02ff00" | [[#lenovo/x60|2018-05-15T03:57:13Z]]
data in the SPI flash.
| Intel® I945
Intel® SUBTYPE I945GM
| Intel® I82801GX
RICOH RL5C476
| NSC PC87382
NSC PC87392
| Intel® Core™ 2 Duo Mobile, Core™ Duo/Solo, Celeron® M
| Socket mPGA478
| SOIC-8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Lenovo
| BOOT_DEVICE_SPI_FLASH_BUS || drivers/spi || int || ||  
| [[Board:lenovo/z61t|Z61t]]
Which SPI bus the boot device is connected to.
| style="background:red" | Unknown
| Intel® I945
Intel® SUBTYPE I945GM
| Intel® I82801GX
TI PCI1X2X
| NSC PC87382
NSC PC87384
| Intel® Core™ 2 Duo Mobile, Core™ Duo/Solo, Celeron® M
| Socket mPGA478
| SOIC-8
| SPI
| style="background:red" | N
| style="background:red" | N
| —


|- bgcolor="#dddddd"
||
| Packard Bell
|- bgcolor="#eeeeee"
| [[Board:packardbell/ms2290|EasyNote LM85 (MS2290)]]
| BOOT_DEVICE_SPI_FLASH_RW_NOMMAP || drivers/spi || bool || ||  
| style="background:#FFff00" | [[#packardbell/ms2290|2014-08-01T17:32:20Z]]
Provide common implementation of the RW boot device that
| Intel® NEHALEM
doesn't provide mmap() operations.
| Intel® IBEXPEAK
|
| Intel® 1st Gen (Nehalem) Core i3/i5/i7
| ?
| SOIC-8
| SPI
| style="background:red" | N
| style="background:red" | N
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Purism
| BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY || drivers/spi || bool || ||  
( Purism )
Include the common implementation in all stages, including the
| [[Board:purism/librem_bdw|Librem Broadwell baseboard]]
early ones.
| style="background:red" | Unknown
|  
|  
|  
|
|
| SOIC8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Purism
| SPI_FLASH_SMM || drivers/spi || bool || SPI flash driver support in SMM ||  
( Purism )
Select this option if you want SPI flash support in SMM.
| [[Board:purism/librem_skl|Librem Skylake baseboard]]
| style="background:red" | Unknown
|  
|
|  
|  
|
| SOIC8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| [http://www.roda-computer.com/en/products/notebooks/rocky-iii-rk886ex.html Roda]
|- bgcolor="#eeeeee"
| [[Board:roda/rk886ex|RK886EX (Rocky III+)]]
| SPI_FLASH_NO_FAST_READ || drivers/spi || bool || Disable Fast Read command ||  
| style="background:red" | Unknown
Select this option if your setup requires to avoid "fast read"s
| Intel® I945
from the SPI flash parts.
Intel® SUBTYPE I945GM
| Intel® I82801GX
TI PCI7420
| SMSC® LPC47N227
RENESAS M3885X
| Intel® Core™ 2 Duo Mobile, Core™ Duo/Solo, Celeron® M
| Socket mPGA478
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| Roda
|- bgcolor="#eeeeee"
| [[Board:roda/rk9|RK9]]
| SPI_FLASH_ADESTO || drivers/spi || bool || ||  
| style="background:red" | Unknown
Select this option if your chipset driver needs to store certain
| Intel® GM45
data in the SPI flash and your SPI flash is made by Adesto Technologies.
| Intel® I82801IX
| SMSC® LPC47N227
| Intel® Core 2 Duo (Penryn)
| Socket P
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| Roda
|- bgcolor="#eeeeee"
| [[Board:roda/rv11|RV11]]
| SPI_FLASH_AMIC || drivers/spi || bool || ||  
| style="background:red" | Unknown
Select this option if your chipset driver needs to store certain
| Intel® IVYBRIDGE
data in the SPI flash and your SPI flash is made by AMIC.
| Intel® C216
| ITE™ IT8783EF if BOARD RODA RW11
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
| Socket RPGA989
| SOIC-8
| SPI
| style="background:red" | N
| style="background:red" | N
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| SAMSUNG
| SPI_FLASH_ATMEL || drivers/spi || bool || ||  
( Samsung )
Select this option if your chipset driver needs to store certain
| [[Board:samsung/lumpy|Series 5 550 Chromebook]]
data in the SPI flash and your SPI flash is made by Atmel.
| style="background:#FFff00" | [[#samsung/lumpy|2017-03-17T21:13:34Z]]
| Intel® SANDYBRIDGE
| Intel® BD82X6X
| SMSC® MEC1308
SMSC® LPC47N207
| Intel® 2nd Gen (Sandybridge) Core i3/i5/i7
| Socket RPGA989
| SOIC-8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#6699ff"
||
| colspan="13" | <h4>Servers</h4>
|- bgcolor="#eeeeee"
| SPI_FLASH_EON || drivers/spi || bool ||  ||
Select this option if your chipset driver needs to store certain
data in the SPI flash and your SPI flash is made by EON.


|- bgcolor="#dddddd"
||
| AMD
|- bgcolor="#eeeeee"
| [[Board:amd/serengeti_cheetah|Serengeti Cheetah]]
| SPI_FLASH_GIGADEVICE || drivers/spi || bool || ||  
| style="background:red" | Unknown
Select this option if your chipset driver needs to store certain
| AMD AMDK8
data in the SPI flash and your SPI flash is made by Gigadevice.
| AMD AMD8132
AMD AMD8151
AMD AMD8111
AMD AMD8131
| Winbond™ W83627HF
| AMD Opteron™
| Socket F
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| AMD
|- bgcolor="#eeeeee"
| [[Board:amd/serengeti_cheetah_fam10|Serengeti Cheetah (Fam10)]]
| SPI_FLASH_MACRONIX || drivers/spi || bool || ||  
| style="background:red" | Unknown
Select this option if your chipset driver needs to store certain
| AMD Family 10h
data in the SPI flash and your SPI flash is made by Macronix.
| AMD AMD8111
AMD AMD8132
| Winbond™ W83627HF
| AMD Opteron™
| Socket F 1207
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [ftp://ftp.aopen.com/pub/server/motherboard/dxplpu/manual/dxplpu-ol-e.pdf AOpen]
| SPI_FLASH_SPANSION || drivers/spi || bool || ||  
| [[Board:aopen/dxplplusu|DXPL Plus-U]]
Select this option if your chipset driver needs to store certain
| style="background:#FFff00" | [[#aopen/dxplplusu|2016-12-04T02:03:58Z]]
data in the SPI flash and your SPI flash is made by Spansion.
| Intel® E7505
| Intel® I82870
Intel® I82801DX
| SMSC® LPC47M10X
| Intel® Xeon®
| Socket 604
| PLCC
| FWH
| style="background:lime" | Y
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| ASUS
|- bgcolor="#eeeeee"
| [[Board:asus/kcma-d8|KCMA-D8]]
| SPI_FLASH_SST || drivers/spi || bool || ||  
| style="background:#1Bff00" | [[#asus/kcma-d8|2018-04-19T15:05:08Z]]
Select this option if your chipset driver needs to store certain
| AMD Family 10h
data in the SPI flash and your SPI flash is made by SST.
| AMD SR5650
AMD SB700
AMD SUBTYPE SP5100
| Winbond™ W83667HG A
| AMD Opteron™ Magny-Cours/Interlagos
| Socket C32
| DIP-8
| SPI
| style="background:lime" | Y
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| ASUS
|- bgcolor="#eeeeee"
| [[Board:asus/kfsn4-dre|KFSN4-DRE]]
| SPI_FLASH_STMICRO || drivers/spi || bool || ||  
| style="background:#5Aff00" | [[#asus/kfsn4-dre|2018-02-15T18:30:23Z]]
Select this option if your chipset driver needs to store certain
| AMD Family 10h
data in the SPI flash and your SPI flash is made by ST MICRO.
| NVIDIA CK804
| Winbond™ W83627THG
| AMD Opteron™
| Socket F 1207
| PLCC-32
| LPC
| style="background:lime" | Y
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| ASUS
|- bgcolor="#eeeeee"
| [[Board:asus/kfsn4-dre_k8|KFSN4-DRE_K8]]
| SPI_FLASH_WINBOND || drivers/spi || bool || ||  
| style="background:#FFff00" | [[#asus/kfsn4-dre_k8|2016-08-22T02:19:24Z]]
Select this option if your chipset driver needs to store certain
| AMD AMDK8
data in the SPI flash and your SPI flash is made by Winbond.
| NVIDIA CK804
| Winbond™ W83627THG
| AMD Opteron™
| Socket F
| PLCC-32
| LPC
| style="background:lime" | Y
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| ASUS
|- bgcolor="#eeeeee"
| [[Board:asus/kgpe-d16|KGPE-D16]]
| SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B || drivers/spi || bool || ||  
| style="background:#0Dff00" | [[#asus/kgpe-d16|2018-05-03T17:31:02Z]]
Select this option if your SPI flash supports the fast read dual-
| AMD Family 10h
output command (opcode 0x3b) where the opcode and address are sent
| AMD SR5650
to the chip on MOSI and data is received on both MOSI and MISO.
AMD SB700
AMD SUBTYPE SP5100
| Winbond™ W83667HG A
| AMD Opteron™ Magny-Cours/Interlagos
| Socket G34
| DIP-8
| SPI
| style="background:lime" | Y
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us&objectID=c00346784&prodTypeId=15351&prodSeriesId=3219755 HP]
| SPI_FLASH_HAS_VOLATILE_GROUP || drivers/spi || bool || ||  
| [[Board:hp/dl145_g1|ProLiant DL145 G1]]
Allows chipset to group write/erase operations under a single volatile
| style="background:red" | Unknown
group.
| AMD AMDK8
| AMD AMD8131
AMD AMD8111
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| PLCC
| LPC
| style="background:lime" | Y
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c00816835&lang=en&cc=us&taskId=101&prodSeriesId=3219755&prodTypeId=15351 HP]
| CACHE_MRC_SETTINGS || drivers/mrc_cache || bool || ||  
| [[Board:hp/dl145_g3|ProLiant DL145 G3]]
Save cached MRC settings
| style="background:red" | Unknown
| AMD AMDK8
| BROADCOM BCM21000
BROADCOM BCM5785
| SERVERENGINES PILOT
NSC PC87417
| AMD Opteron™
| Socket F
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us&objectID=c01765799 HP]
| MRC_WRITE_NV_LATE || drivers/mrc_cache || bool || ||  
| [[Board:hp/dl165_g6_fam10|ProLiant DL165 G6 (Fam10)]]
MRC settings are normally written to NVRAM at BS_DEV_ENUMERATE-EXIT.
| style="background:red" | Unknown
If a platform requires MRC settings written to NVRAM later than
| AMD Family 10h
normal, select this item.  This will cause the write to occur at
| BROADCOM BCM21000
BS_OS_RESUME_CHECK-ENTRY.
BROADCOM BCM5785
| SERVERENGINES PILOT
NSC PC87417
| AMD Opteron™
| Socket F 1207
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| [http://web.archive.org/web/20060507170150/http://www.iwill.net/product_2.asp?p_id=98 IWILL]
|- bgcolor="#eeeeee"
| [[Board:iwill/dk8_htx|DK8-HTX]]
| DIGITIZER_AUTODETECT || drivers/lenovo || bool || Autodetect ||  
| style="background:red" | Unknown
The presence of digitizer is inferred from model number stored in
| AMD AMDK8
AT24RF chip.
| AMD AMD8111
AMD AMD8131
| Winbond™ W83627HF
| AMD Opteron™
| Socket 940
| ?
| ?
| ?
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.msiserver.de/de/Produkte/Server_Mainboards/K9SD_Master_S2R_MS_9185.aspx MSI]
| DIGITIZER_PRESENT || drivers/lenovo || bool || Present ||  
| [[Board:msi/ms9185|K9SD Master-S2R (MS-9185)]]
The digitizer is assumed to be present.
| style="background:red" | Unknown
| AMD AMDK8
| BROADCOM BCM5780
BROADCOM BCM5785
| NSC PC87417
| AMD Opteron™
| Socket F
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://cweb.msi.com.tw/program/products/server/svr/pro_svr_detail.php?UID=632 MSI]
| DIGITIZER_ABSENT || drivers/lenovo || bool || Absent ||  
| [[Board:msi/ms9282|K9SD Master (MS-9282)]]
The digitizer is assumed to be absent.
| style="background:red" | Unknown
| AMD AMDK8
| NVIDIA MCP55
| Winbond™ W83627EHG
| AMD Opteron™
| Socket F
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| Open Compute Project
|- bgcolor="#eeeeee"
| [[Board:ocp/monolake|Mono Lake]]
| UART_OVERRIDE_INPUT_CLOCK_DIVIDER || drivers/uart || boolean || ||  
| style="background:red" | Unknown
Set to "y" when the platform overrides the uart_input_clock_divider
|  
routine.
|  
|  
|
|
| ?
| SPI
| yes
| ?
| —


|- bgcolor="#dddddd"
||
| Open Compute Project
|- bgcolor="#eeeeee"
| [[Board:ocp/wedge100s|Wedge 100S]]
| UART_OVERRIDE_REFCLK || drivers/uart || boolean || ||  
| style="background:red" | Unknown
Set to "y" when the platform overrides the uart_platform_refclk
|  
routine.
|  
| ITE™ COMMON ROMSTAGE
|
|
| ?
| SPI
| yes
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Scaleway
| DRIVERS_UART_OXPCIE || drivers/uart || bool || Oxford OXPCIe952 ||  
( Scaleway )
Support for Oxford OXPCIe952 serial port PCIe cards.
| [[Board:scaleway/tagada|Tagada]]
Currently only devices with the vendor ID 0x1415 and device ID
| style="background:red" | Unknown
0xc158 or 0xc11b will work.
|
|  
|  
|  
|  
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| [http://www.supermicro.com/Aplus/motherboard/Opteron2000/MCP55/H8DME-2.cfm Supermicro]
|- bgcolor="#eeeeee"
| [[Board:supermicro/h8dme|H8DME-2]]
| UART_USE_REFCLK_AS_INPUT_CLOCK || drivers/uart || bool || ||  
| style="background:red" | Unknown
Use uart_platform_refclk to specify the input clock value.
| AMD AMDK8
| NVIDIA MCP55
| Winbond™ W83627HF
| AMD Opteron™
| Socket F
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| [http://www.supermicro.com/Aplus/motherboard/Opteron2000/MCP55/H8DMR-i2.cfm Supermicro]
|- bgcolor="#eeeeee"
| [[Board:supermicro/h8dmr|H8DMR-i2]]
| UART_PCI_ADDR || drivers/uart || hex || UART's PCI bus, device, function address ||  
| style="background:red" | Unknown
Specify zero if the UART is connected to another bus type.
| AMD AMDK8
For PCI based UARTs, build the value as:
| NVIDIA MCP55
* 1 &lt;&lt; 31 - Valid bit, PCI UART in use
| Winbond™ W83627HF
* Bus &lt;&lt; 20
| AMD Opteron™
* Device &lt;&lt; 15
| Socket F
* Function &lt;&lt; 12
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| Supermicro
||
| [[Board:supermicro/h8dmr_fam10|H8DMR-i2 (Fam10)]]
|- bgcolor="#eeeeee"
| style="background:red" | Unknown
| GIC || drivers/gic || None || ||  
| AMD Family 10h
This option enables GIC support, the ARM generic interrupt controller.
| NVIDIA MCP55
| Winbond™ W83627HF
| AMD Opteron™
| Socket F 1207
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| [http://www.supermicro.com/Aplus/motherboard/Opteron8000/MCP55/H8QME-2.cfm Supermicro]
||
| [[Board:supermicro/h8qme_fam10|H8QME-2+ (Fam10)]]
|- bgcolor="#eeeeee"
| style="background:red" | Unknown
| REALTEK_8168_RESET || drivers/net || bool || ||  
| AMD Family 10h
This forces a realtek 10ec:8168 card to reset to ensure power state
| AMD AMD8132
is correct at boot.
NVIDIA MCP55
| Winbond™ W83627HF
| AMD Opteron™
| Socket F 1207
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| Supermicro
|- bgcolor="#eeeeee"
| [[Board:supermicro/h8scm_fam10|H8SCM (Fam10)]]
| REALTEK_8168_MACADDRESS || drivers/net || string || Realtek rt8168 mac address ||  
| style="background:red" | Unknown
This is a string to set the mac address on a Realtek rt8168 card.
| AMD Family 10h
It must be in the form of "xx:xx:xx:xx:xx:xx", where x is a
| AMD SR5650
hexadecimal number for it to be valid. Failing to do so will
AMD SB700
result in the default macaddress being used.
AMD SUBTYPE SP5100
| Winbond™ W83627HF
Nuvoton WPCM450
| AMD Opteron™ Magny-Cours/Interlagos
| Socket C32
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.tyan.com/product_board_detail.aspx?pid=157 Tyan]
| RT8168_SET_LED_MODE || drivers/net || bool || ||  
| [[Board:tyan/s2912|Thunder n3600R (S2912)]]
This is to set a customized LED mode to distinguish 10/100/1000
| style="background:red" | Unknown
link and speed status with limited LEDs avaiable on a board.
| AMD AMDK8
Please refer to RTL811x datasheet section 7.2 Customizable LED
| NVIDIA MCP55
Configuration for details. With this flag enabled, the
| Winbond™ W83627HF
customized_leds variable will be read from devicetree setting.
| AMD Opteron™
| Socket F
| ?
| ?
| ?
| ?
| —


||
||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Tyan
| DRIVERS_PS2_KEYBOARD || drivers/pc80/pc || bool || PS/2 keyboard init ||  
| [[Board:tyan/s2912_fam10|S2912 (Fam10)]]
Enable this option to initialize PS/2 keyboards found connected
| style="background:red" | Unknown
to the PS/2 port.
| AMD Family 10h
 
| NVIDIA MCP55
Some payloads (eg, filo) require this option.  Other payloads
| Winbond™ W83627HF
(eg, GRUB 2, SeaBIOS, Linux) do not require it.
| AMD Opteron™
Initializing a PS/2 keyboard can take several hundred milliseconds.
| Socket F 1207
 
| ?
If you know you will only use a payload which does not require
| ?
this option, then you can say N here to speed up boot time.
| ?
Otherwise say Y.
| ?
| —


|- bgcolor="#6699ff"
||
| colspan="13" | <h4>Desktops / Workstations</h4>
||
|- bgcolor="#eeeeee"
| VGA || drivers/pc80/vga || bool ||  ||
Include legacy VGA support code.


|- bgcolor="#dddddd"
||
| [http://www.asrock.com/mb/overview.asp?Model=939A785GMH/128M&s=939 ASROCK]
||
| [[Board:asrock/939a785gmh|939A785GMH/128M]]
|- bgcolor="#eeeeee"
| style="background:#B3ff00" | [[#asrock/939a785gmh|2017-11-19T01:50:13Z]]
| LPC_TPM || drivers/pc80/tpm || bool || Enable TPM support ||  
| AMD AMDK8
Enable this option to enable LPC TPM support in coreboot.
| AMD RS780
AMD SB700
| Winbond™ W83627DHG
| AMD Athlon™ 64 / FX / X2
| Socket 939
| DIP8
| SPI
| ?
| ?
| —


|- bgcolor="#dddddd"
If unsure, say N.
| [http://www.asrock.com/mb/Intel/B75%20Pro3-M/ ASROCK]
| [[Board:asrock/b75pro3-m|B75 Pro3-M]]
| style="background:#D9ff00" | [[#asrock/b75pro3-m|2017-10-12T02:45:41Z]]
| Intel® IVYBRIDGE
| Intel® C216
| Nuvoton  NCT6776
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
| Socket RPGA989
| DIP-8
| SPI
| style="background:lime" | Y
| style="background:red" | N
| —


|- bgcolor="#dddddd"
||
| [http://www.asrock.com/mb/intel/g41c-gs/ ASROCK]
|- bgcolor="#eeeeee"
| [[Board:asrock/g41c-gs|G41C-GS R2.0]]
| TPM_TIS_BASE_ADDRESS || drivers/pc80/tpm || hex ||  ||  
| style="background:#FFff00" | [[#asrock/g41c-gs|2017-08-31T13:23:34Z]]
This can be used to adjust the TPM memory base address.
| Intel® X4X
The default is specified by the TCG PC Client Specific TPM
| Intel® I82801GX
Interface Specification 1.2 and should not be changed unless
| Nuvoton NCT6776
the TPM being used does not conform to TPM TIS 1.2.
| Intel® Core 2, Pentium 4/D
| Socket LGA775
| DIP-8
| SPI
| style="background:lime" | Y
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.asus.com/Motherboards/AMD_Socket_939/A8NE/ ASUS]
| TPM_PIRQ || drivers/pc80/tpm || hex || ||  
| [[Board:asus/a8n_e|A8N-E]]
This can be used to specify a PIRQ to use instead of SERIRQ,
| style="background:#FFff00" | [[#asus/a8n_e|2014-02-25T19:03:49Z]]
which is needed for SPI TPM interrupt support on x86.
| AMD AMDK8
| NVIDIA CK804
| ITE™ IT8712F
| AMD Athlon™ 64 / FX / X2
| Socket 939
| PLCC
| LPC
| style="background:lime" | Y
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.asus.com/Motherboards/AMD_Socket_939/A8NSLI/ ASUS]
| TPM_INIT_FAILURE_IS_FATAL || drivers/pc80/tpm || bool || ||  
| [[Board:asus/a8n_sli|A8N-SLI]]
What to do if TPM init failed. If true, force a hard reset,
| style="background:#FFff00" | [[#asus/a8n_e|2014-02-25T19:03:49Z]]
otherwise just log error message to console.
| AMD AMDK8
| NVIDIA CK804
| ITE™ IT8712F
| AMD Athlon™ 64 / FX / X2
| Socket 939
| PLCC
| ?
| style="background:lime" | Y
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.asus.com/Motherboards/AMD_Socket_939/A8VE_Deluxe/ ASUS]
| SKIP_TPM_STARTUP_ON_NORMAL_BOOT || drivers/pc80/tpm || bool || ||  
| [[Board:asus/a8v-e_deluxe|A8V-E Deluxe]]
Skip TPM init on normal boot. Useful if payload does TPM init.
| style="background:red" | Unknown
| AMD AMDK8
| VIA VT8237R
VIA K8T890
VIA SUBTYPE K8T890
| Winbond™ W83627EHG
| AMD Athlon™ 64 / FX / X2
| Socket 939
| PLCC
| ?
| style="background:lime" | Y
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.asus.com/Motherboards/AMD_Socket_939/A8VE_SE/ ASUS]
| TPM_DEACTIVATE || drivers/pc80/tpm || bool || Deactivate TPM ||  
| [[Board:asus/a8v-e_se|A8V-E SE]]
Deactivate TPM by issuing deactivate command.
| style="background:#FFff00" | [[#asus/a8v-e_se|2014-01-03T17:47:48Z]]
| AMD AMDK8
| VIA VT8237R
VIA K8T890
VIA SUBTYPE K8T890
| Winbond™ W83627EHG
| AMD Athlon™ 64 / FX / X2
| Socket 939
| PLCC
| LPC
| style="background:lime" | Y
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.asus.com/Motherboards/AMD_Socket_FM2/F2A85M/ ASUS]
| TPM_RDRESP_NEED_DELAY || drivers/pc80/tpm || bool || Enable Delay Workaround for TPM ||  
| [[Board:asus/f2a85-m|F2A85-M]]
Certain TPMs seem to need some delay when reading response
| style="background:#FFff00" | [[#asus/f2a85-m|2017-09-04T11:13:36Z]]
to work around a race-condition-related issue, possibly
| AMD Family 15h TN (AGESA)
caused by ill-programmed TPM firmware.
| AMD AGESA HUDSON
| ITE™ IT8728F if BOARD ASUS F2A85 M || BOARD ASUS F2A85 M LE
Nuvoton  NCT6779D if BOARD ASUS F2A85 M PRO
| AMD Family 15h TN (AGESA)
| ?
| DIP8
| [http://www.winbond-usa.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/SerialFlash/W25Q64BV.htm SPI]
| style="background:lime" | Y
| style="background:lime" | Y
| —


||
||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| ASUS
| PLATFORM_USES_FSP1_1 || drivers/intel/fsp1_1 || bool || ||  
| [[Board:asus/k8v-x|K8V-X]]
Does the code require the Intel Firmware Support Package?
| style="background:red" | Unknown
| AMD AMDK8
| VIA VT8237R
VIA K8T890
VIA SUBTYPE K8T800 OLD
| Winbond™ W83697HF
| AMD Sempron™ / Athlon™ 64 / Turion™ 64
| Socket 754
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
| || || (comment) || || Intel FSP 1.1 ||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.asus.com/Motherboards/AMD_AM2/M2NE/ ASUS]
| HAVE_FSP_BIN || drivers/intel/fsp1_1 || bool || Should the Intel FSP binary be added to the flash image ||  
| [[Board:asus/m2n-e|M2N-E]]
Select this option to add an Intel FSP binary to
| style="background:red" | Unknown
the resulting coreboot image.
| AMD AMDK8
 
| NVIDIA MCP55
Note: Without this binary, coreboot builds relying on the FSP
| ITE™ IT8716F
will not boot
| ?
| Socket AM2
| PLCC
| LPC
| style="background:lime" | Y
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.asus.com/Motherboards/AMD_AM2/M2V/ ASUS]
| CPU_MICROCODE_CBFS_LEN || drivers/intel/fsp1_1 || hex || Microcode update region length in bytes ||  
| [[Board:asus/m2v|M2V]]
The length in bytes of the microcode update region.
| style="background:red" | Unknown
| AMD AMDK8
| VIA VT8237R
VIA K8T890
VIA SUBTYPE K8T890
| ITE™ IT8712F
| ?
| Socket AM2
| PLCC
| LPC
| style="background:lime" | Y
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.asus.com/Motherboards/AMD_AM2/M2VMX_SE/ ASUS]
| CPU_MICROCODE_CBFS_LOC || drivers/intel/fsp1_1 || hex || Microcode update base address in CBFS ||  
| [[Board:asus/m2v-mx_se|M2V-MX SE]]
The location (base address) in CBFS that contains the microcode update
| style="background:#9Fff00" | [[#asus/m2v-mx_se|2017-12-09T03:28:27Z]]
binary.
| AMD AMDK8
| VIA VT8237R
VIA K8T890
VIA SUBTYPE K8M890
| ITE™ IT8712F
| ?
| Socket AM2
| DIP8
| SPI
| style="background:lime" | Y
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.asus.com/Motherboards/AMD_AM2Plus/M4A78EM/ ASUS]
| FSP_FILE || drivers/intel/fsp1_1 || string || Intel FSP binary path and filename ||  
| [[Board:asus/m4a78-em|M4A78-EM]]
The path and filename of the Intel FSP binary for this platform.
| style="background:red" | Unknown
| AMD Family 10h
| AMD RS780
AMD SB700
| ITE™ IT8712F
| AMD Athlon™ 64 / FX / X2
| Socket AM3
| DIP8
| SPI
| style="background:lime" | Y
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.asus.com/Motherboards/AMD_AM2Plus/M4A785M/ ASUS]
| FSP_LOC || drivers/intel/fsp1_1 || hex || Intel FSP Binary location in CBFS ||  
| [[Board:asus/m4a785-m|M4A785-M]]
The location in CBFS that the FSP is located. This must match the
| style="background:red" | Unknown
value that is set in the FSP binary.  If the FSP needs to be moved,
| AMD Family 10h
rebase the FSP with Intel's BCT (tool).
| AMD RS780
AMD SB700
| ITE™ IT8712F
| AMD Athlon™ 64 / FX / X2
| Socket AM3
| DIP8
| SPI
| style="background:lime" | Y
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.asus.com/Motherboards/AMD_AM3/M4A785TM/ ASUS]
| DISPLAY_UPD_DATA || drivers/intel/fsp1_1 || bool || Display UPD data ||  
| [[Board:asus/m4a785t-m|M4A785T-M]]
Display the user specified product data prior to memory
| style="background:#FFff00" | [[#asus/m4a785t-m|2015-10-22T18:20:48Z]]
initialization.
| AMD Family 10h
| AMD RS780
AMD SB700
| ITE™ IT8712F
| AMD Athlon™ 64 / FX / X2
| Socket AM3
| DIP8
| SPI
| style="background:lime" | Y
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.asus.com/Motherboards/AMD_AM3Plus/M5A88V_EVO/ ASUS]
| FSP_USES_UPD || drivers/intel/fsp1_1 || bool || ||  
| [[Board:asus/m5a88-v|M5A88-V]]
If this FSP uses UPD/VPD data regions, select this in the chipset
| style="background:red" | Unknown
Kconfig.
| AMD Family 10h
| AMD RS780
AMD SB800
| ITE™ IT8721F
| AMD Athlon™ 64 / FX / X2
| Socket AM3
| DIP8
| SPI
| style="background:lime" | Y
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [https://www.asus.com/ROG-Republic-Of-Gamers/MAXIMUS_IV_GENEZ/ ASUS]
| USE_GENERIC_FSP_CAR_INC || drivers/intel/fsp1_1 || bool ||  ||  
| [[Board:asus/maximus_iv_gene-z|Maximus IV GENE-Z]]
The chipset can select this to use a generic cache_as_ram.inc file
| style="background:#29ff00" | [[#asus/maximus_iv_gene-z|2018-04-06T10:29:01Z]]
that should be good for all FSP based platforms.
| Intel® SANDYBRIDGE
| Intel® BD82X6X
| Nuvoton NCT6776
| Intel® 2nd Gen (Sandybridge) Core i3/i5/i7
| Socket LGA1155
| DIP-8
| SPI
| style="background:lime" | Y
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b/ ASUS]
| INTEL_DDI || drivers/intel/gma || bool || ||  
| [[Board:asus/p2b|P2B]]
helper functions for intel DDI operations
| style="background:#99ff00" | [[#asus/p2b|2017-12-15T03:32:04Z]]
| Intel® I440BX
| Intel® I82371EB
| Winbond™ W83977TF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-d/ ASUS]
| INTEL_GMA_SSC_ALTERNATE_REF || drivers/intel/gma || bool || ||  
| [[Board:asus/p2b-d|P2B-D]]
Set when the SSC reference clock for LVDS runs at a different fre-
| style="background:red" | Unknown
quency than the general display reference clock.
| Intel® I440BX
 
| Intel® I82371EB
To be set by northbridge or mainboard Kconfig.  For most platforms,
| Winbond™ W83977TF
there is no choice, i.e. for i945 and gm45 the SSC reference always
| Intel® Pentium® II/III, Celeron®
differs from the display reference clock (i945: 66Mhz SSC vs. 48MHz
| Slot 1
DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Nehalem and newer, it's
| DIP32
the same frequency for SSC/non-SSC (120MHz).  The only, currently
| Parallel
supported platform with a choice seems to be Pineview, where the
| style="background:lime" | Y
alternative is 100MHz vs. the default 96MHz.
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-ds/ ASUS]
| INTEL_GMA_SWSMISCI || drivers/intel/gma || bool || ||  
| [[Board:asus/p2b-ds|P2B-DS]]
Select this option for Atom-based platforms which use the SWSMISCI
| style="background:red" | Unknown
register (0xe0) rather than the SWSCI register (0xe8).
| Intel® I440BX
| Intel® I82371EB
| Winbond™ W83977TF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-f/ ASUS]
| GFX_GMA_ANALOG_I2C_PORT || drivers/intel/gma || string || ||  
| [[Board:asus/p2b-f|P2B-F]]
Boards with a DVI-I connector share the I2C pins for both analog and
| style="background:red" | Unknown
digital displays. In that case, the EDID for a VGA display has to be
| Intel® I440BX
read over the I2C interface of the coupled digital port.
| Intel® I82371EB
| Winbond™ W83977TF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-ls/ ASUS]
| DRIVERS_INTEL_MIPI_CAMERA || drivers/intel/mipi_camera || bool || ||  
| [[Board:asus/p2b-ls|P2B-LS]]
MIPI CSI I2C camera SSDT generator. Generates SSDB and PWDB
| style="background:#F5ff00" | [[#asus/p2b-ls|2017-09-13T17:26:27Z]]
structures which are used by the Intel kernel drivers.
| Intel® I440BX
| Intel® I82371EB
| Winbond™ W83977TF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —


||
||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p3b-f/ ASUS]
| || || (comment) || || Intel FSP ||
| [[Board:asus/p3b-f|P3B-F]]
|- bgcolor="#eeeeee"
| style="background:#F5ff00" | [[#asus/p3b-f|2017-09-13T17:26:27Z]]
| HAVE_FSP_BIN || drivers/intel/fsp1_0 || bool || Use Intel Firmware Support Package ||  
| Intel® I440BX
Select this option to add an Intel FSP binary to
| Intel® I82371EB
the resulting coreboot image.
| Winbond™ W83977TF
| Intel® Pentium® II/III, Celeron®
| Slot 1
| DIP32
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —


Note: Without this binary, coreboot builds relying on the FSP
will not boot
||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [https://www.asus.com/Motherboards/P5GCMX/ ASUS]
| FSP_FILE || drivers/intel/fsp1_0 || string || Intel FSP binary path and filename ||  
| [[Board:asus/p5gc-mx|P5GC-MX]]
The path and filename of the Intel FSP binary for this platform.
| style="background:#FFff00" | [[#asus/p5gc-mx|2017-06-17T18:00:03Z]]
| Intel® I945
Intel® SUBTYPE I945GC
| Intel® I82801GX
| Winbond™ W83627DHG
| Intel® Core 2, Pentium 4/D
| Socket LGA775
| DIP-8
| SPI
| style="background:lime" | Y
| ?
| —


|- bgcolor="#dddddd"
||
| [http://www.avalue.com.tw/en/product/detail.aspx?ccid=2&cid=9&id=68&zid=245 AVALUE]
|- bgcolor="#eeeeee"
| [[Board:avalue/eax-785e|EAX-785E]]
| FSP_LOC || drivers/intel/fsp1_0 || hex || Intel FSP Binary location in CBFS ||  
| style="background:red" | Unknown
The location in CBFS that the FSP is located. This must match the
| AMD Family 10h
value that is set in the FSP binary.  If the FSP needs to be moved,
| AMD RS780
rebase the FSP with Intel's BCT (tool).
AMD SB800
| Winbond™ W83627HF #COM1, COM2
#FINTEK F81216AD #COM3, COM4
| AMD Athlon™ 64 / FX / X2
| Socket AM3
| SOIC-8
| SPI
| style="background:red" | N
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.foxconnchannel.com/ProductDetail.aspx?T=motherboard&U=en-us0000455 Foxconn]
| ENABLE_FSP_FAST_BOOT || drivers/intel/fsp1_0 || bool || Enable Fast Boot ||  
| [[Board:foxconn/g41s-k|G41S-K]]
Enabling this feature will force the MRC data to be cached in NV
| style="background:#9Dff00" | [[#foxconn/g41s-k|2017-12-11T07:06:21Z]]
storage to be used for speeding up boot time on future reboots
| Intel® X4X
and/or power cycles.
| Intel® I82801GX
| ITE™ IT8720F
| Intel® Core 2, Pentium 4/D
| Socket LGA775
| DIP-8
| SPI
| style="background:lime" | Y
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| [http://www.gigabyte.com/products/product-page.aspx?pid=2669#ov GIGABYTE]
|- bgcolor="#eeeeee"
| [[Board:gigabyte/ga-945gcm-s2l|GA-945GCM-S2L]]
| ENABLE_MRC_CACHE || drivers/intel/fsp1_0 || bool || ||  
| style="background:#FFff00" | [[#gigabyte/ga-945gcm-s2l|2017-04-17T16:12:02Z]]
Enabling this feature will cause MRC data to be cached in NV storage.
| Intel® I945
This can either be used for fast boot, or just because the FSP wants
Intel® SUBTYPE I945GC
it to be saved.
| Intel® I82801GX
| ITE™ IT8718F
| Intel® Core 2, Pentium 4/D
| Socket LGA775
| SOIC-8
| SPI
| style="background:red" | N
| ?
| —


|- bgcolor="#dddddd"
||
| [http://www.gigabyte.com/products/product-page.aspx?pid=4150#sp GIGABYTE]
|- bgcolor="#eeeeee"
| [[Board:gigabyte/ga-b75m-d3h|GA-B75M-D3H]]
| MRC_CACHE_FMAP || drivers/intel/fsp1_0 || bool || Use MRC Cache in FMAP ||  
| style="background:#B3ff00" | [[#gigabyte/ga-b75m-d3h|2017-11-19T01:50:13Z]]
Use the region "RW_MRC_CACHE" in FMAP instead of "mrc.cache" in CBFS.
| Intel® IVYBRIDGE
You must define a region in your FMAP named "RW_MRC_CACHE".
| Intel® C216
| ITE™ IT8728F
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
| Socket LGA1155
| SOIC-8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| [http://www.gigabyte.com/products/product-page.aspx?pid=4151#ov GIGABYTE]
|- bgcolor="#eeeeee"
| [[Board:gigabyte/ga-b75m-d3v|GA-B75M-D3V]]
| MRC_CACHE_SIZE || drivers/intel/fsp1_0 || hex || Fast Boot Data Cache Size ||  
| style="background:#B3ff00" | [[#gigabyte/ga-b75m-d3v|2017-11-19T01:50:13Z]]
This is the amount of space in NV storage that is reserved for the
| Intel® IVYBRIDGE
fast boot data cache storage.
| Intel® C216
| ITE™ IT8728F
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
| Socket LGA1155
| SOIC-8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
WARNING: Because this area will be erased and re-written, the size
| [http://www.gigabyte.com/products/product-page.aspx?pid=3024#ov GIGABYTE]
should be a full sector of the flash ROM chip and nothing else should
| [[Board:gigabyte/ga-g41m-es2l|GA-G41M-ES2L]]
be included in CBFS in any sector that the fast boot cache data is in.
| style="background:#0Bff00" | [[#gigabyte/ga-g41m-es2l|2018-05-06T06:18:48Z]]
| Intel® X4X
| Intel® I82801GX
| ITE™ IT8718F
| Intel® Core 2, Pentium 4/D
| Socket LGA775
| SOIC-8
| SPI
| style="background:red" | N
| ?
| —


|- bgcolor="#dddddd"
||
| [http://www.computerbase.de/news/hardware/mainboards/amd-systeme/2007/mai/gigabyte_dtx-mainboard/ GIGABYTE]
|- bgcolor="#eeeeee"
| [[Board:gigabyte/ga_2761gxdk|GA-2761GXDK (Churchill)]]
| VIRTUAL_ROM_SIZE || drivers/intel/fsp1_0 || hex || Virtual ROM Size ||  
| style="background:red" | Unknown
This is used to calculate the offset of the MRC data cache in NV
| AMD AMDK8
Storage for fast boot.  If in doubt, leave this set to the default
| SIS SIS966
which sets the virtual size equal to the ROM size.
| ITE™ IT8716F
| ?
| Socket AM2
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
Example: Cougar Canyon 2 has two 8 MB SPI ROMs. When the SPI ROMs are
| [http://www.gigabyte.com/products/product-page.aspx?pid=2287#ov GIGABYTE]
loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB. When
| [[Board:gigabyte/m57sli|GA-M57SLI-S4]]
the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM
| style="background:#FFff00" | [[#gigabyte/m57sli|2017-04-17T16:31:52Z]]
size is 16 MB.
| AMD AMDK8
| NVIDIA MCP55
| ITE™ IT8716F
| ?
| Socket AM2
| ?
| ?
| style="background:red" | N
| style="background:lime" | Y
| [[Gigabyte m57sli Vendor Cooperation Score|3]]


|- bgcolor="#dddddd"
||
| [http://www.gigabyte.us/products/product-page.aspx?pid=3447#sp GIGABYTE]
|- bgcolor="#eeeeee"
| [[Board:gigabyte/ma785gm|GA-MA785GM-US2H]]
| CACHE_ROM_SIZE_OVERRIDE || drivers/intel/fsp1_0 || hex || Cache ROM Size ||  
| style="background:red" | Unknown
This is the size of the cachable area that is passed into the FSP in
| AMD Family 10h
the early initialization.  Typically this should be the size of the CBFS
| AMD RS780
area, but the size must be a power of 2 whereas the CBFS size does not
AMD SB700
have this limitation.
| ITE™ IT8718F
| AMD Athlon™ 64 / FX / X2
| Socket AM3
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| [http://www.gigabyte.com/products/product-page.aspx?pid=3156#ov GIGABYTE]
|- bgcolor="#eeeeee"
| [[Board:gigabyte/ma785gmt|GA-MA785GMT-UD2H]]
| USE_GENERIC_FSP_CAR_INC || drivers/intel/fsp1_0 || bool || ||  
| style="background:#FFff00" | [[#gigabyte/ma785gmt|2015-07-02T05:20:16Z]]
The chipset can select this to use a generic cache_as_ram.inc file
| AMD Family 10h
that should be good for all FSP based platforms.
| AMD RS780
AMD SB700
| ITE™ IT8718F
| AMD Athlon™ 64 / FX / X2
| Socket AM3
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| [http://www.gigabyte.com/products/product-page.aspx?pid=2995#ov GIGABYTE]
|- bgcolor="#eeeeee"
| [[Board:gigabyte/ma78gm|GA-MA78GM-US2H]]
| FSP_USES_UPD || drivers/intel/fsp1_0 || bool ||  ||
| style="background:red" | Unknown
If this FSP uses UPD/VPD data regions, select this in the chipset Kconfig.
| AMD Family 10h
||
| AMD RS780
|- bgcolor="#eeeeee"
AMD SB700
| DRIVERS_INTEL_WIFI || drivers/intel/wifi || bool || Support Intel PCI-e WiFi adapters ||  
| ITE™ IT8718F
When enabled, add identifiers in ACPI and SMBIOS tables to
| AMD Athlon™ 64 / X2 / FX, Sempron™
make OS drivers work with certain Intel PCI-e WiFi chipsets.
| Socket AM2+
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Google
| USE_SAR || drivers/intel/wifi || bool || ||  
( Google )
Enable it when wifi driver uses SAR configuration feature.
| [[Board:google/fizz|Fizz Kabylake Reference Board]]
VPD entry "wifi_sar" is required to support it.
| style="background:red" | Unknown
|
|  
|  
|  
|  
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| [http://www.intel.com/p/en_US/support/highlights/dsktpboards/d510mo Intel]
|- bgcolor="#eeeeee"
| [[Board:intel/d510mo|D510MO]]
| DSAR_SET_NUM || drivers/intel/wifi || hex || Number of SAR sets when D-SAR is enabled ||  
| style="background:#0Bff00" | [[#intel/d510mo|2018-05-06T06:18:48Z]]
There can be up to 3 optional SAR table sets.
| Intel® PINEVIEW
| Intel® I82801GX
| Winbond™ W83627THG
| INTEL_SOCKET_FCBGA559
| INTEL_SOCKET_FCBGA559
| SOIC-8
| SPI
| style="background:red" | N
| ?
| —


|- bgcolor="#dddddd"
||
| [http://www.intel.com/support/motherboards/desktop/d945gclf/sb/CS-029163.htm?wapkw=d945gclf+overview Intel]
||
| [[Board:intel/d945gclf|D945GCLF]]
|- bgcolor="#eeeeee"
| style="background:#E5ff00" | [[#intel/d945gclf|2017-09-30T01:24:47Z]]
| PLATFORM_USES_FSP2_0 || drivers/intel/fsp2_0 || bool || ||  
| Intel® I945
Include FSP 2.0 wrappers and functionality
Intel® SUBTYPE I945GC
| Intel® I82801GX
| SMSC® LPC47M15X
| Intel® Atom™ 230
| Socket 441
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| Intel
|- bgcolor="#eeeeee"
| [[Board:intel/dcp847ske|Intel NUC DCP847SKE]]
| ADD_FSP_BINARIES || drivers/intel/fsp2_0 || bool || Add Intel FSP 2.0 binaries to CBFS ||  
| style="background:red" | Unknown
Add the FSP-M and FSP-S binaries to CBFS. Currently coreboot does not
| Intel® SANDYBRIDGE
use the FSP-T binary and it is not added.
| Intel® C216
| Nuvoton  NCT6776
| Intel® 2nd Gen (Sandybridge) Core i3/i5/i7
| Socket RPGA989
| SOIC-8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| [https://ark.intel.com/products/41036/Intel-Desktop-Board-DG43GT Intel]
|- bgcolor="#eeeeee"
| [[Board:intel/dg43gt|DG43GT]]
| DISPLAY_FSP_CALLS_AND_STATUS || drivers/intel/fsp2_0 || bool || Display the FSP calls and status ||  
| style="background:#EBff00" | [[#intel/dg43gt|2017-09-23T22:29:35Z]]
Display the FSP call entry point and parameters prior to calling FSP
| Intel® X4X
and display the status upon return from FSP.
| Intel® I82801JX
| Winbond™ W83627DHG
| Intel® Core 2, Pentium 4/D
| Socket LGA775
| SOIC-8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.jetway.com.tw/jw/motherboard_view.asp?productid=567&proname=PA78VM5 Jetway]
| DISPLAY_FSP_HEADER || drivers/intel/fsp2_0 || bool || Display the FSP header ||  
| [[Board:jetway/pa78vm5|PA78VM5 (Fam10)]]
Display the FSP header information when the FSP file is found.
| style="background:red" | Unknown
| AMD Family 10h
| AMD RS780
AMD SB700
| FINTEK F71863FG
| AMD Athlon™ 64 / X2 / FX, Sempron™
| Socket AM2+
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| [http://no.msi.com/product/mb/K8N-Neo3.html MSI]
|- bgcolor="#eeeeee"
| [[Board:msi/ms7135|MS-7135 (K8N Neo3)]]
| DISPLAY_HOBS || drivers/intel/fsp2_0 || bool || Display the hand-off-blocks ||  
| style="background:#4Bff00" | [[#msi/ms7135|2018-03-02T15:21:54Z]]
Display the FSP HOBs which are provided for coreboot.
| AMD AMDK8
| NVIDIA CK804
| Winbond™ W83627THG
| AMD Sempron™ / Athlon™ 64 / Turion™ 64
| Socket 754
| PLCC
| LPC
| variable
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| [http://no.msi.com/product/mb/K9N-Neo--PCB-1-0-.html MSI]
|- bgcolor="#eeeeee"
| [[Board:msi/ms7260|MS-7260 (K9N Neo)]]
| DISPLAY_UPD_DATA || drivers/intel/fsp2_0 || bool || Display UPD data ||  
| style="background:red" | Unknown
Display the user specified product data prior to memory
| AMD AMDK8
initialization.
| NVIDIA MCP55
| Winbond™ W83627EHG
| ?
| Socket AM2
| PLCC
| ?
| style="background:lime" | Y
| style="background:yellow" | ...<sup>6</sup>
| —


|- bgcolor="#dddddd"
||
| [https://www.msi.com/Motherboard/FM2-A75MA-E35.html MSI]
|- bgcolor="#eeeeee"
| [[Board:msi/ms7721|MS-7721]]
| FSP_T_FILE || drivers/intel/fsp2_0 || string || Intel FSP-T (temp ram init) binary path and filename ||  
| style="background:#26ff00" | [[#msi/ms7721|2018-04-09T12:06:51Z]]
The path and filename of the Intel FSP-M binary for this platform.
| AMD Family 15h TN (AGESA)
| AMD AGESA HUDSON
| FINTEK F71869AD
| AMD Family 15h TN (AGESA)
| ?
| SOIC8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| MSI
|- bgcolor="#eeeeee"
| [[Board:msi/ms9652_fam10|MS-9652]]
| FSP_M_FILE || drivers/intel/fsp2_0 || string || Intel FSP-M (memory init) binary path and filename ||  
| style="background:red" | Unknown
The path and filename of the Intel FSP-M binary for this platform.
| AMD Family 10h
| NVIDIA MCP55
| Winbond™ W83627EHG
| AMD Opteron™
| Socket F 1207
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://docs.oracle.com/cd/E19127-01/ultra40.ws/820-0123-13/intro.html Sun Microsystems]
| FSP_S_FILE || drivers/intel/fsp2_0 || string || Intel FSP-S (silicon init) binary path and filename ||  
| [[Board:sunw/ultra40|Ultra 40]]
The path and filename of the Intel FSP-S binary for this platform.
| style="background:red" | Unknown
| AMD AMDK8
| NVIDIA CK804
| SMSC® LPC47B397
SMSC® LPC47M10X
| AMD Opteron™
| Socket 940
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://docs.oracle.com/cd/E19127-01/ultra40.ws/820-0123-13/intro.html Sun Microsystems]
| FSP_CAR || drivers/intel/fsp2_0 || bool || Use FSP TempRamInit &amp; TempRamExit APIs ||  
| [[Board:sunw/ultra40m2|Ultra 40 M2]]
Use FSP APIs to initialize &amp; Tear Down the Cache-As-Ram
| style="background:red" | Unknown
| AMD AMDK8
| NVIDIA MCP55
| SMSC® DME1737
| AMD Opteron™
| Socket F
| PLCC
| LPC
| style="background:lime" | Y
| ?
| —


|- bgcolor="#dddddd"
||
| [http://www.win-ent.com/network-computing/network-systems/desktop-platforms/440-pl-60640.html Win Enterprises]
|- bgcolor="#eeeeee"
| [[Board:winent/pl6064|PL60640]]
| FSP_M_XIP || drivers/intel/fsp2_0 || bool || Is FSP-M XIP ||  
| style="background:red" | Unknown
Select this value when FSP-M is execute-in-place.
| AMD LX
| AMD CS5536
| Winbond™ W83627HF
| AMD Geode™ LX
| —
| ?
| ?
| ?
| ?
| —


|- bgcolor="#6699ff"
||
| colspan="13" | <h4>Embedded / PC/104 / Half-size boards</h4>
|- bgcolor="#eeeeee"
| VERIFY_HOBS || drivers/intel/fsp2_0 || bool || Verify the FSP hand-off-blocks ||
Verify that the HOBs required by coreboot are returned by FSP and
that the resource HOBs are in the correct order and position.


|- bgcolor="#dddddd"
||
| [http://www.aaeonusa.com/products/details/?item_id=1043 Aaeon]
|- bgcolor="#eeeeee"
| [[Board:aaeon/pfm-540i_revb|PFM-540I Rev.B]]
| DISPLAY_FSP_VERSION_INFO || drivers/intel/fsp2_0 || bool || Display Firmware Ingredient Version Information ||  
| style="background:red" | Unknown
Select this option to display Firmware version information.
| AMD LX
| AMD CS5536
| SMSC® SMSC®SUPERIO
| AMD Geode™ LX
| —
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.adlinktech.com/PD/web/PD_detail.php?pid=1277 ADLINK]
| FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS || drivers/intel/fsp2_0 || bool || ||  
| [[Board:adlink/CM2-GF|CoreModule2-GF]]
This is selected by SoC or mainboard to supply their own
| style="background:#FFff00" | [[#lippert/frontrunner-af|2017-09-01T05:15:05Z]]
concept of a version for the memory settings respectively.
| AMD Family 14h (AGESA)
This allows deployed systems to bump their version number
| AMD CIMX SB800
with the same FSP which will trigger a retrain of the memory.
| SMSC® SMSC®SUPERIO
| AMD Family 14h (AGESA)
| ?
| SOIC8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.adlinktech.com/PD/web/PD_detail.php?pid=1132 ADLINK]
| DRIVERS_SIL_3114 || drivers/sil/3114 || bool || Silicon Image SIL3114 ||  
| [[Board:adlink/cExpress-GFR|cExpress-GFR]]
It sets PCI class to IDE compatible native mode, allowing
| style="background:red" | Unknown
SeaBIOS, FILO etc... to boot from it.
| AMD Family 14h (AGESA)
| AMD CIMX SB800
| Winbond™ W83627DHG
| AMD Family 14h (AGESA)
| ?
| SOIC8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| [http://www.amd.com/Documents/40631a_epic_rdk_pb.pdf AMD]
||
| [[Board:amd/samba|Samba]]
|- bgcolor="#eeeeee"
| style="background:red" | Unknown
| DRIVER_TI_TPS65090 || drivers/ti/tps65090 || bool || ||  
| AMD LX
TI TPS65090
| AMD CS5536
| ITE™ IT8712F
| AMD Geode™ LX
| —
| SOIC8
| SPI
| style="background:red" | N
| style="background:red" | N
| —


||
||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.digitallogic.ch/english/products/datasheets/ms_pc104_detail.asp?id=MSM800SEV DIGITAL-LOGIC]
| DRIVERS_EMULATION_QEMU_BOCHS || drivers/emulation/qemu || bool || bochs dispi interface vga driver ||  
| [[Board:digitallogic/msm800sev|MSM800SEV]]
VGA driver for qemu emulated vga cards supporting
| style="background:red" | Unknown
the bochs dispi interface.  This includes
| AMD LX
standard vga, vmware svga and qxl.  The default
| AMD CS5536
vga (cirrus) is *not* supported, so you have to
| Winbond™ W83627HF
pick another one explicitly via 'qemu -vga $card'.
| AMD Geode™ LX
| —
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| GizmoSphere
|- bgcolor="#eeeeee"
| [[Board:gizmosphere/gizmo|Gizmo]]
| DRIVER_XPOWERS_AXP209 || drivers/xpowers/axp209 || bool || ||  
| style="background:#FFff00" | [[#gizmosphere/gizmo|2017-08-25T20:33:26Z]]
X-Powers AXP902 Power Management Unit
| AMD Family 14h (AGESA)
| AMD CIMX SB800
|  
| AMD Family 14h (AGESA)
| ?
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Google
| DRIVER_XPOWERS_AXP209_BOOTBLOCK || drivers/xpowers/axp209 || bool || ||  
( Google )
Make AXP209 functionality available in he bootblock.
| [[Board:google/beltino|Beltino Haswell Chromebox Reference device]]
| style="background:red" | Unknown
| Intel® HASWELL
| Intel® LYNXPOINT
| ITE™ IT8772F
| Intel® 4th Gen (Haswell) Core i3/i5/i7
| ?
| SOIC-8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| [http://web.archive.org/web/20111208234719/http://ieiworld.com/product_groups/industrial/content.aspx?gid=00001000010000000001&cid=09050652111816087425&id=09069696333360342284 IEI]
|- bgcolor="#eeeeee"
| [[Board:iei/kino-780am2-fam10|Kino-780AM2]]
| DRIVER_PARADE_PS8640 || drivers/parade/ps8640 || bool || ||  
| style="background:red" | Unknown
Parade PS8640 MIPI DSI to eDP Converter
| AMD Family 10h
| AMD RS780
AMD SB700
| FINTEK F71859
| AMD Athlon™ 64 / X2 / FX, Sempron™
| Socket AM2+
| ?
| SPI
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| [http://www.ieiworld.com/en/product_IPC.asp?model=PCISA-LX IEI]
||
| [[Board:iei/pcisa-lx-800-r10|PCISA-LX-800-R10]]
|- bgcolor="#eeeeee"
| style="background:red" | Unknown
| DRIVER_PARADE_PS8625 || drivers/parade/ps8625 || bool || ||  
| AMD LX
Parade ps8625 display port to lvds bridge
| AMD CS5536
| Winbond™ W83627HF
| AMD Geode™ LX
| —
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| [http://www.ieiworld.com/product_groups/industrial/content.aspx?gid=00001000010000000001&cid=09050665574743104681&id=08142307826854456110#.UCLx8cLlgao IEI]
||
| [[Board:iei/pm-lx-800-r11|PM-LX-800-R11]]
|- bgcolor="#eeeeee"
| style="background:red" | Unknown
| DRIVER_MAXIM_MAX77686 || drivers/maxim/max77686 || bool || ||  
| AMD LX
Maxim MAX77686 power regulator
| AMD CS5536
| Winbond™ W83627EHG
| AMD Geode™ LX
| —
| PLCC
| LPC
| style="background:lime" | Y
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| [http://www.ieiworld.com/product_groups/industrial/content.aspx?gid=00001000010000000001&cid=09050665574743104681&id=09034367569861123956#.UI2CfiExUao IEI]
||
| [[Board:iei/pm-lx2-800-r10|PM-LX2-800-R10]]
|- bgcolor="#eeeeee"
| style="background:red" | Unknown
| DRIVERS_I2C_PCA9538 || drivers/i2c/pca9538 || bool || ||  
| AMD LX
Enable support for I2C I/O expander PCA9538.
| AMD CS5536
| SMSC® SMSC®SUPERIO
| AMD Geode™ LX
| —
| PLCC
| LPC
| style="background:lime" | Y
| style="background:lime" | Y
| —


||
||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.adlinktech.com/PD/web/PD_detail.php?pid=1277 LiPPERT]
| DRIVERS_I2C_RX6110SA || drivers/i2c/rx6110sa || bool || ||  
| [[Board:lippert/frontrunner-af|FrontRunner-AF]]
Enable support for external RTC chip RX6110 SA.
| style="background:#FFff00" | [[#lippert/frontrunner-af|2017-09-01T05:15:05Z]]
| AMD Family 14h (AGESA)
| AMD CIMX SB800
| SMSC® SMSC®SUPERIO
| AMD Family 14h (AGESA)
| ?
| SOIC8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


||
||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.adlinktech.com/PD/web/PD_detail.php?pid=1154 LiPPERT]
| DRIVERS_I2C_DESIGNWARE || drivers/i2c/designware || bool || ||  
| [[Board:lippert/hurricane-lx|Hurricane-LX]]
Designware I2C support
| style="background:red" | Unknown
| AMD LX
| AMD CS5536
| ITE™ IT8712F
| AMD Geode™ LX
| —
| SOIC8
| SPI
| style="background:red" | N
| style="background:red" | N
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.adlinktech.com/PD/web/PD_detail.php?pid=1128 LiPPERT]
| DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ || drivers/i2c/designware || int || ||  
| [[Board:lippert/literunner-lx|Cool LiteRunner-LX]]
The i2c ip block's clock.
| style="background:red" | Unknown
| AMD LX
| AMD CS5536
| ITE™ IT8712F
| AMD Geode™ LX
| —
| SOIC8
| SPI
| style="background:red" | N
| style="background:red" | N
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.adlinktech.com/PD/web/PD_detail.php?pid=1147 LiPPERT]
| DRIVERS_I2C_RTD2132 || drivers/i2c/rtd2132 || bool || ||  
| [[Board:lippert/roadrunner-lx|Cool RoadRunner-LX]]
Enable support for Realtek RTD2132 DisplayPort to LVDS bridge chip.
| style="background:red" | Unknown
| AMD LX
| AMD CS5536
| ITE™ IT8712F
| AMD Geode™ LX
| —
| PLCC
| FWH
| style="background:lime" | Y
| style="background:lime" | Y
| —


||
||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.adlinktech.com/PD/web/PD_detail.php?pid=1148 LiPPERT]
| STORAGE_ERASE || commonlib/storage || bool || Support SD/MMC erase operations ||  
| [[Board:lippert/spacerunner-lx|Cool SpaceRunner-LX]]
Select to enable SD/MMC erase oprations
| style="background:red" | Unknown
| AMD LX
| AMD CS5536
| ITE™ IT8712F
| AMD Geode™ LX
| —
| SOIC8
| SPI
| style="background:red" | N
| style="background:red" | N
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.adlinktech.com/PD/web/PD_detail.php?pid=1132 LiPPERT]
| STORAGE_WRITE || commonlib/storage || bool || Support SD/MMC write operations ||  
| [[Board:lippert/toucan-af|Toucan-AF]]
Select to enable SD/MMC write oprations
| style="background:red" | Unknown
| AMD Family 14h (AGESA)
| AMD CIMX SB800
| Winbond™ W83627DHG
| AMD Family 14h (AGESA)
| ?
| SOIC8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| [http://pcengines.ch/alix1c.htm PC Engines]
|- bgcolor="#eeeeee"
| [[Board:pcengines/alix1c|alix1c]]
| SD_MMC_DEBUG || commonlib/storage || bool || Debug SD/MMC card/devices operations ||  
| style="background:#7Aff00" | [[#pcengines/alix1c|2018-01-15T00:44:43Z]]
Display overview of SD/MMC card/device operations
| AMD LX
| AMD CS5536
| Winbond™ W83627HF
| AMD Geode™ LX
| —
| PLCC-32
| LPC
| style="background:red" | N
| style="background:lime" | Y
| style="background:lime"| [[PC Engines ALIX.1C Vendor Cooperation Score|4]]


|- bgcolor="#dddddd"
||
| [http://pcengines.ch/alix2c3.htm PC Engines]
|- bgcolor="#eeeeee"
| [[Board:pcengines/alix2c|alix2c]]
| SD_MMC_TRACE || commonlib/storage || bool || Trace SD/MMC card/device operations ||  
| style="background:red" | Unknown
Display details of SD/MMC card/device operations
|  
|  
|  
|
|
| TSOP-32
| LPC
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| [http://pcengines.ch/alix2d0.htm PC Engines]
|- bgcolor="#eeeeee"
| [[Board:pcengines/alix2d|alix2d]]
| SDHC_DEBUG || commonlib/storage || bool || Debug SD/MMC controller settings ||  
| style="background:#7Aff00" | [[#pcengines/alix2d|2018-01-15T00:44:43Z]]
Display clock speed and bus width settings
| AMD LX
| AMD CS5536
|  
| AMD Geode™ LX
| —
| TSOP-32
| LPC
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| [http://pcengines.ch/alix6f2.htm PC Engines]
|- bgcolor="#eeeeee"
| [[Board:pcengines/alix6|alix6f]]
| SDHC_TRACE || commonlib/storage || bool || Trace SD/MMC controller operations ||  
| style="background:red" | Unknown
Display the operations performed by the SD/MMC controller
|  
|  
|  
|  
|
| TSOP-32
| LPC
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| [http://www.pcengines.ch/apu1d4.htm PC Engines]
|- bgcolor="#eeeeee"
| [[Board:pcengines/apu1|apu1]]
| SDHCI_ADMA_IN_BOOTBLOCK || commonlib/storage || bool ||  ||  
| style="background:#11ff00" | [[#pcengines/apu1|2018-04-29T18:26:46Z]]
Determine if bootblock is able to use ADMA2 or ADMA64
| AMD Family 14h (AGESA)
| AMD CIMX SB800
| Nuvoton NCT5104D
| AMD Family 14h (AGESA)
| ?
| SOIC-8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| [http://www.pcengines.ch/apu2c2.htm PC Engines]
|- bgcolor="#eeeeee"
| [[Board:pcengines/apu2|apu2 apu3 apu4 apu5]]
| SDHCI_ADMA_IN_ROMSTAGE || commonlib/storage || bool ||  ||  
| style="background:#7Aff00" | [[#pcengines/apu2|2018-01-15T00:44:43Z]]
Determine if romstage is able to use ADMA2 or ADMA64
| AMD 00730F01 (PI)
| AMD PI AVALON
| Nuvoton NCT5104D
| AMD_PI_00730F01
| AMD_PI_00730F01
| SOIC-8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| SAMSUNG
| SDHCI_ADMA_IN_VERSTAGE || commonlib/storage || bool || ||  
( Samsung )
Determine if verstage is able to use ADMA2 or ADMA64
| [[Board:samsung/stumpy|Series 3 Chromebox]]
| style="background:#FFff00" | [[#samsung/stumpy|2014-01-21T04:39:46Z]]
| Intel® SANDYBRIDGE
| Intel® BD82X6X
| ITE™ IT8772F
SMSC® LPC47N207
| Intel® 2nd Gen (Sandybridge) Core i3/i5/i7
| Socket RPGA989
| SOIC-8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| Siemens
| [[Board:siemens/sitemp_g1p1|MB SITEMP-G1 (U1P0/U1P1)]]
| style="background:red" | Unknown
| AMD AMDK8
| AMD RS690
AMD SB600
| ITE™ IT8712F
| AMD Turion™ / X2  Sempron™
| Socket S1G1
| ?
| ?
| ?
| ?
| —


|- bgcolor="#6699dd"
! align="left" | Menu: Security || || || ||
|- bgcolor="#6699dd"
! align="left" | Menu: Verified Boot (vboot) || || || ||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.technexion.com/index.php/embedded-mainboards/amd/tim-5690 Technexion]
| VBOOT || security/vboot || bool || Verify firmware with vboot. ||  
| [[Board:technexion/tim5690|TIM-5690]]
Enabling VBOOT will use vboot to verify the components of the firmware
| style="background:red" | Unknown
(stages, payload, etc).
| AMD AMDK8
| AMD RS690
AMD SB600
| ITE™ IT8712F
| AMD Turion™ / X2  Sempron™
| Socket S1G1
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.technexion.com/index.php/tim-8690 Technexion]
| VBOOT_VBNV_CMOS || security/vboot || bool ||  ||  
| [[Board:technexion/tim8690|TIM-8690]]
VBNV is stored in CMOS
| style="background:red" | Unknown
| AMD AMDK8
| AMD RS690
AMD SB600
| ITE™ IT8712F
| AMD Turion™ / X2 Sempron™
| Socket S1G1
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| [http://www.traverse.com.au/geos11-adsl2-x86-router-appliance Traverse Technologies]
|- bgcolor="#eeeeee"
| [[Board:traverse/geos|Geos]]
| VBOOT_VBNV_OFFSET || security/vboot || hex || ||  
| style="background:red" | Unknown
CMOS offset for VbNv data. This value must match cmos.layout
| AMD LX
in the mainboard directory, minus 14 bytes for the RTC.
| AMD CS5536
|  
| AMD Geode™ LX
| —
| PLCC
| ?
| style="background:lime" | Y
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Win Enterprises
| VBOOT_VBNV_CMOS_BACKUP_TO_FLASH || security/vboot || bool || ||  
| [[Board:winent/mb6047|MB6047]]
Vboot non-volatile storage data will be backed up from CMOS to flash
| style="background:red" | Unknown
and restored from flash if the CMOS is invalid due to power loss.
| AMD AMDK8
| NVIDIA CK804
| Winbond™ W83627THG
| AMD Opteron™
| Socket 940
| ?
| ?
| ?
| ?
| —


|- bgcolor="#6699ff"
||
| colspan="13" | <h4>Mini-ITX / Micro-ITX / Nano-ITX</h4>
|- bgcolor="#eeeeee"
| VBOOT_VBNV_EC || security/vboot || bool ||  ||
VBNV is stored in EC


|- bgcolor="#dddddd"
||
| [http://www.advansus.com.tw/products/247/A785E-I Advansus]
|- bgcolor="#eeeeee"
| [[Board:advansus/a785e-i|A785E-I]]
| VBOOT_VBNV_FLASH || security/vboot || bool || ||  
| style="background:red" | Unknown
VBNV is stored in flash storage
| AMD Family 10h
| AMD RS780
AMD SB800
| Winbond™ W83627HF #COM1, COM2
#FINTEK F81216AD #COM3, COM4
| AMD Turion™ II Neo/Athlon™ II Neo
| ASB2 (BGA812)
| SOIC-8
| SPI
| style="background:red" | N
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| AMD
| VBOOT_STARTS_IN_BOOTBLOCK || security/vboot || bool || ||  
| [[Board:amd/f2950|F2950]]
Firmware verification happens during the end of or right after the
| style="background:red" | Unknown
bootblock. This implies that a static VBOOT2_WORK() buffer must be
| AMD LX
allocated in memlayout.
| AMD CS5536
| Winbond™ W83627HF
| AMD Geode™ LX
| —
| PLCC
| LPC
| style="background:red" | N
| style="background:red" | N
| —


|- bgcolor="#dddddd"
||
| [http://www.asrock.com/mb/overview.asp?Model=E350M1 ASROCK]
|- bgcolor="#eeeeee"
| [[Board:asrock/e350m1|E350M1]]
| VBOOT_STARTS_IN_ROMSTAGE || security/vboot || bool ||  ||  
| style="background:#06ff00" | [[#asrock/e350m1|2018-05-11T00:57:05Z]]
Firmware verification happens during the end of romstage (after
| AMD Family 14h (AGESA)
memory initialization). This implies that vboot working data is
| AMD CIMX SB800
allocated in CBMEM.
| Nuvoton NCT5572D
| AMD Family 14h (AGESA)
| ?
| DIP8
| SPI
| style="background:lime" | Y
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| [http://www.asrock.com/ipc/overview.asp?Model=IMB-A180 ASROCK]
|- bgcolor="#eeeeee"
| [[Board:asrock/imb-a180|IMB-A180]]
| VBOOT_MOCK_SECDATA || security/vboot || bool || Mock secdata for firmware verification ||  
| style="background:#FFff00" | [[#asrock/imb-a180|2017-08-24T10:37:14Z]]
Enabling VBOOT_MOCK_SECDATA will mock secdata for the firmware
| AMD Family 16h KB (AGESA)
verification to avoid access to a secdata storage (typically TPM).
| AMD AGESA YANGTZE
All operations for a secdata storage will be successful. This option
| Winbond™ W83627UHG
can be used during development when a TPM is not present or broken.
| AMD Family 16h KB (AGESA)
THIS SHOULD NOT BE LEFT ON FOR PRODUCTION DEVICES.
| ?
| DIP8
| SPI
| style="background:lime" | Y
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [https://www.asus.com/us/Motherboards/AM1IA/ ASUS]
| VBOOT_DISABLE_DEV_ON_RECOVERY || security/vboot || bool || ||  
| [[Board:asus/am1i-a|AM1I-A]]
When this option is enabled, the Chrome OS device leaves the
| style="background:#0Dff00" | [[#asus/am1i-a|2018-05-03T17:31:02Z]]
developer mode as soon as recovery request is detected. This is
| AMD Family 16h KB (AGESA)
handy on embedded devices with limited input capabilities.
| AMD AGESA YANGTZE
| ITE™ IT8623E
| AMD Family 16h KB (AGESA)
| ?
| DIP8
| SPI
| style="background:lime" | Y
| ?
| —


|- bgcolor="#dddddd"
||
| [http://www.biostar.com.tw/app/en/mb/introduction.php?S_ID=694 Biostar]
|- bgcolor="#eeeeee"
| [[Board:biostar/am1ml|AM1ML]]
| VBOOT_SEPARATE_VERSTAGE || security/vboot || bool || ||  
| style="background:#FFff00" | [[#biostar/am1ml|2015-04-13T11:03:01Z]]
If this option is set, vboot verification runs in a standalone stage
| AMD Family 16h KB (AGESA)
that is loaded from the bootblock and exits into romstage. If it is
| AMD AGESA YANGTZE
not set, the verification code is linked directly into the bootblock
| ITE™ IT8728F
or the romstage and runs as part of that stage (cf. related options
| AMD Family 16h KB (AGESA)
VBOOT_STARTS_IN_BOOTBLOCK/_ROMSTAGE and VBOOT_RETURN_FROM_VERSTAGE).
| ?
| DIP8
| SPI
| style="background:lime" | Y
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| HP
| VBOOT_RETURN_FROM_VERSTAGE || security/vboot || bool ||  ||  
| [[Board:hp/abm|ABM]]
If this is set, the verstage returns back to the calling stage instead
| style="background:red" | Unknown
of exiting to the succeeding stage so that the verstage space can be
| AMD Family 16h KB (AGESA)
reused by the succeeding stage. This is useful if a RAM space is too
| AMD AGESA YANGTZE
small to fit both the verstage and the succeeding stage.
| Nuvoton NCT5104D
| AMD Family 16h KB (AGESA)
| ?
| SOIC8
| SPI
| style="background:lime" | Y
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| [http://www.ibase.com.tw/mb899.htm iBase]
|- bgcolor="#eeeeee"
| [[Board:ibase/mb899|MB899]]
| VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT || security/vboot || bool || ||  
| style="background:red" | Unknown
This option ensures that the recovery request is not lost because of
| Intel® I945
reboots caused after vboot verification is run. e.g. reboots caused by
Intel® SUBTYPE I945GM
FSP components on Intel platforms.
| Intel® I82801GX
| Winbond™ W83627EHG
| Intel® Core™ 2 Duo Mobile, Core™ Duo/Solo, Celeron® M
| Socket mPGA478
| PLCC
| FWH
| style="background:lime" | Y
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=279&proname=J7F2 Jetway]
| VBOOT_OPROM_MATTERS || security/vboot || bool || ||  
| [[Board:jetway/j7f2|J7f2]]
Set this option to indicate to vboot that this platform will skip its
| style="background:red" | Unknown
display initialization on a normal (non-recovery, non-developer) boot.
| VIA CN700
Vboot calls this "oprom matters" because on x86 devices this
| VIA VT8237R
traditionally meant that the video option ROM will not be loaded, but
| FINTEK F71805F
it works functionally the same for other platforms that can skip their
| VIA C7™
native display initialization code instead.
| ?
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=279&proname=J7F4K1G2E Jetway]
| VBOOT_HAS_REC_HASH_SPACE || security/vboot || bool || ||  
| [[Board:jetway/j7f4k1g2e|J7f4K1G2E]]
Set this option to indicate to vboot that recovery data hash space
| style="background:red" | Unknown
is present in TPM.
| VIA CN700
| VIA VT8237R
| FINTEK F71805F
| VIA C7™
| ?
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=279&proname=J7F4K1G5D Jetway]
| VBOOT_EC_SOFTWARE_SYNC || security/vboot || bool || Enable EC software sync ||  
| [[Board:jetway/j7f4k1g5d|J7f4K1G5D]]
EC software sync is a mechanism where the AP helps the EC verify its
| style="background:red" | Unknown
firmware similar to how vboot verifies the main system firmware. This
| VIA CN700
option selects whether vboot should support EC software sync.
| VIA VT8237R
| FINTEK F71805F
| VIA C7™
| ?
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=822&proname=NF81-T56N-LF Jetway]
| VBOOT_EC_SLOW_UPDATE || security/vboot || bool || ||  
| [[Board:jetway/nf81-t56n-lf|NF81-T56N-LF]]
Whether the EC (or PD) is slow to update and needs to display a
| style="background:#FFff00" | [[#jetway/nf81-t56n-lf|2014-03-29T03:40:24Z]]
screen that informs the user the update is happening.
| AMD Family 14h (AGESA)
| AMD CIMX SB800
| FINTEK F71869AD
| AMD Family 14h (AGESA)
| ?
| SOIC8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| [http://www.kontron.de/products/boards-and-mezzanines/embedded-motherboards/mini-itx-motherboards/986lcd-m-mitx.html Kontron]
|- bgcolor="#eeeeee"
| [[Board:kontron/986lcd-m|986LCD-M/mITX]]
| VBOOT_EC_EFS || security/vboot || bool || ||  
| style="background:red" | Unknown
CrosEC can support EFS: Early Firmware Selection. If it's enabled,
| Intel® I945
software sync need to also support it. This setting tells vboot to
Intel® SUBTYPE I945GM
perform EFS software sync.
| Intel® I82801GX
| Winbond™ W83627THG
| Intel® Core™ 2 Duo Mobile, Core™ Duo/Solo, Celeron® M
| Socket mPGA478
| PLCC
| FWH
| style="background:lime" | Y
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| [http://emea.kontron.com/products/boards+and+mezzanines/embedded+motherboards/miniitx+motherboards/kt690mitx+bga.html?searchtermresultpage=kt690%2Fmitx Kontron]
|- bgcolor="#eeeeee"
| [[Board:kontron/kt690|KT690/mITX]]
| VBOOT_PHYSICAL_DEV_SWITCH || security/vboot || bool ||  ||  
| style="background:red" | Unknown
Whether this platform has a physical developer switch. Note that this
| AMD AMDK8
disables virtual dev switch functionality (through secdata). Operation
| AMD RS690
where both a physical pin and the virtual switch get sampled is not
AMD SB600
supported by coreboot.
| Winbond™ W83627DHG
| AMD Turion™ / X2 Sempron™
| Socket S1G1
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| Kontron
|- bgcolor="#eeeeee"
| [[Board:kontron/ktqm77|KTQM77/mITX]]
| VBOOT_PHYSICAL_REC_SWITCH || security/vboot || bool || ||  
| style="background:red" | Unknown
Whether this platform has a physical recovery switch.
| Intel® IVYBRIDGE
| Intel® C216
| Winbond™ W83627DHG
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
| Socket RPGA989
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Sapphire
| VBOOT_LID_SWITCH || security/vboot || bool || ||  
| [[Board:sapphire/pureplatinumh61|Pure Platinum H61]]
Whether this platform has a lid switch. If it does, vboot will not
| style="background:#FFff00" | [[#sapphire/pureplatinumh61|2017-08-26T16:30:37Z]]
decrement try counters for boot failures if the lid is closed.
| Intel® IVYBRIDGE
| Intel® BD82X6X
| FINTEK F71808A
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
| Socket LGA1155
| SOIC-8
| SPI
| style="background:lime" | Y
| style="background:red" | N
| —


|- bgcolor="#dddddd"
||
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=400 VIA]
|- bgcolor="#eeeeee"
| [[Board:via/epia-cn|EPIA-CN10000EG / EPIA-CN13000G]]
| VBOOT_WIPEOUT_SUPPORTED || security/vboot || bool || ||  
| style="background:red" | Unknown
When this option is enabled, the firmware provides the ability to
| VIA CN700
signal the application the need for factory reset (a.k.a. wipe
| VIA VT8237R
out) of the device
| VIA VT1211
| VIA C7™
| ?
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| [http://www.viaembedded.com/en/products/boards/670/1/EPIA-M700_%28EOL%29.html VIA]
|- bgcolor="#eeeeee"
| [[Board:via/epia-m700|EPIA-M700]]
| VBOOT_FWID_MODEL || security/vboot || string || Firmware ID model ||  
| style="background:red" | Unknown
This is the first part of the FWID written to various regions of a
| VIA VX800
vboot firmware image to identify its version.
|  
| Winbond™ W83697HF
| VIA C7™
| ?
| SOIC8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| [http://www.viaembedded.com/en/products/boards/1290/1/EPIA-M850.html VIA]
|- bgcolor="#eeeeee"
| [[Board:via/epia-m850|EPIA-M850]]
| VBOOT_FWID_VERSION || security/vboot || string || Firmware ID version ||  
| style="background:red" | Unknown
This is the second part of the FWID written to various regions of a
| VIA VX900
vboot firmware image to identify its version.
|  
| FINTEK F81865F
| VIA Nano™
| ?
| SOIC8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| [http://www.idot.com.tw/en/products/mb-pc2500e/ VIA]
|- bgcolor="#eeeeee"
| [[Board:via/pc2500e|pc2500e]]
| VBOOT_NO_BOARD_SUPPORT || security/vboot || bool || Allow the use of vboot without board support ||  
| style="background:red" | Unknown
Enable weak functions for get_write_protect_state and
| VIA CN700
get_recovery_mode_switch in order to proceed with refactoring
| VIA VT8237R
of the vboot2 code base. Later on this code is removed and replaced
| ITE™ IT8716F
by interfaces.
| VIA C7™
| ?
| PLCC
| ?
| style="background:lime" | Y
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| WinNET
| RO_REGION_ONLY || security/vboot || string || Additional files that should not be copied to RW ||
( WinNET )
Add a space delimited list of filenames that should only be in the
| [[Board:winnet/g170|G170]]
RO section.
| style="background:red" | Unknown
 
| VIA CN700
||
| VIA VT8237R
|- bgcolor="#6699dd"
| Winbond™ W83697HF
! align="left" | Menu: GBB configuration || || || ||
| VIA C7™
 
| ?
|- bgcolor="#6699dd"
| PLCC
! align="left" | Menu: Vboot Keys || || || ||
| Parallel
| style="background:lime" | Y
| style="background:lime" | Y
| —


|- bgcolor="#6699ff"
| colspan="13" | <h4>Set-top-boxes / Thin clients</h4>


|- bgcolor="#dddddd"
|- bgcolor="#6699dd"
| [http://www.artecgroup.com/thincan/index.php?option=com_content&task=blogcategory&id=15&Itemid=34 Artec Group]
! align="left" | Menu: Trusted Platform Module || || || ||
| [[Board:artecgroup/dbe61|DBE61]]
|- bgcolor="#eeeeee"
| style="background:red" | Unknown
| TPM || security/tpm || bool || ||  
| AMD LX
Enable this option to enable TPM support in coreboot.
| AMD CS5536
 
|  
If unsure, say N.
| AMD Geode™ LX
| —
| ?
| ?
| ?
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Bachmann electronic
| TPM2 || security/tpm || bool || ||  
| [[Board:bachmann/ot200|OT200]]
Enable this option to enable TPM2 support in coreboot.
| style="background:red" | Unknown
 
| AMD LX
If unsure, say N.
| AMD CS5536
|  
| AMD Geode™ LX
| —
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| BCOM
|- bgcolor="#eeeeee"
| [[Board:bcom/winnetp680|WinNET P680]]
| DEBUG_TPM || security/tpm || bool || Output verbose TPM debug messages ||  
| style="background:red" | Unknown
This option enables additional TPM related debug messages.
| VIA CN700
| VIA VT8237R
| Winbond™ W83697HF
| VIA C7™
| ?
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Google
| POWER_OFF_ON_CR50_UPDATE || security/tpm || bool || ||  
( Google )
Power off machine while waiting for CR50 update to take effect.
| [[Board:google/jecht|Jecht Broadwell Chromebox]]
| style="background:red" | Unknown
|
|
| ITE™ IT8772F
|  
|  
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Google
| MAINBOARD_HAS_LPC_TPM || security/tpm || bool || ||  
( Google )
Board has TPM support
| [[Board:google/storm|Storm Qualcomm IPQ806X board]]
| style="background:red" | Unknown
|  
|  
|  
|  
|
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| [http://www.linutop.com Linutop]
|- bgcolor="#eeeeee"
| [[Board:linutop/linutop1|Linutop-1]]
| MAINBOARD_HAS_TPM2 || security/tpm || bool || ||  
| style="background:red" | Unknown
There is a TPM device installed on the mainboard, and it is
| AMD LX
compliant with version 2 TCG TPM specification. Could be connected
| AMD CS5536
over LPC, SPI or I2C.
|  
| AMD Geode™ LX
| —
| ?
| ?
| ?
| style="background:lime" | Y
| —


|- bgcolor="#6699ff"
||
| colspan="13" | <h4>Devel/Eval Boards</h4>


|- bgcolor="#dddddd"
| ADI
| [[Board:adi/rcc-dff|ADI RCC-DFF]]
| style="background:red" | Unknown
| Intel® RANGELEY (FSP)
| Intel® FSP RANGELEY
|
| INTEL_FSP_RANGELEY
| Socket RPGA989
| ?
| SPI
| ?
| style="background:lime" | Y
| —


|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| AMD
| ACPI_SATA_GENERATOR || acpi || bool || ||  
| [[Board:amd/bettong|FP4]]
Use ACPI SATA port generator.
| style="background:red" | Unknown
| AMD 00660F01 (PI)
| AMD PI KERN
|  
| AMD_PI_00660F01
| AMD_PI_00660F01
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| AMD
| ACPI_INTEL_HARDWARE_SLEEP_VALUES || acpi || bool || ||  
| [[Board:amd/bimini_fam10|Bimini (Fam10)]]
Provide common definitions for Intel hardware PM1_CNT register sleep
| style="background:red" | Unknown
values.
| AMD Family 10h
| AMD RS780
AMD SB800
| ITE™ IT8718F
| AMD Turion™ II Neo/Athlon™ II Neo
| ASB2 (BGA812)
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://wwwd.amd.com/amd/devsite.nsf/platforms/db-ft3-lc.htm AMD]
| ACPI_AMD_HARDWARE_SLEEP_VALUES || acpi || bool || ||  
| [[Board:amd/db-ft3b-lc|DB-FT3b-LC]]
Provide common definitions for AMD hardware PM1_CNT register sleep
| style="background:red" | Unknown
values.
| AMD 00730F01 (PI)
| AMD PI AVALON
|  
| AMD_PI_00730F01
| AMD_PI_00730F01
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


||
||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://www.amd.com/us/products/embedded/develop-and-design/Pages/development-boards-lx.aspx AMD]
| BOOT_DEVICE_MEMORY_MAPPED || toplevel || bool || ||  
| [[Board:amd/db800|DB800 (Salsa)]]
Inform system if SPI is memory-mapped or not.
| style="background:red" | Unknown
| AMD LX
| AMD CS5536
| Winbond™ W83627HF
| AMD Geode™ LX
| —
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://support.amd.com/us/ChipsetMotherboard_TechDocs/42655A_S1DBM680T_PB.pdf AMD]
| BOOT_DEVICE_SUPPORTS_WRITES || toplevel || bool ||  ||  
| [[Board:amd/dbm690t|dbM690T (Herring)]]
Indicate that the platform has writable boot device
| style="background:red" | Unknown
support.
| AMD AMDK8
| AMD RS690
AMD SB600
| ITE™ IT8712F
| AMD Turion™ / X2 Sempron™
| Socket S1G1
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#6699dd"
! align="left" | Menu: Console || || || ||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| AMD
| BOOTBLOCK_CONSOLE || console || bool || Enable early (bootblock) console output. ||  
| [[Board:amd/gardenia|GARDENIA]]
Use console during the bootblock if supported
| style="background:#FFff00" | [[#amd/gardenia|2017-01-06T16:30:58Z]]
|
|  
|  
|  
|  
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| AMD
| POSTCAR_CONSOLE || console || bool || Enable console output during postcar. ||  
| [[Board:amd/inagua|Inagua]]
Use console during the postcar if supported
| style="background:red" | Unknown
| AMD Family 14h (AGESA)
| AMD CIMX SB800
| SMSC® KBC1100
| AMD Family 14h (AGESA)
| ?
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| AMD
| SQUELCH_EARLY_SMP || console || bool || Squelch AP CPUs from early console. ||  
| [[Board:amd/lamar|DB-FP3 (Lamar)]]
When selected only the BSP CPU will output to early console.
| style="background:#FFff00" | [[#amd/lamar|2015-04-30T02:12:19Z]]
| AMD 00630F01 (PI)
| AMD PI BOLTON
| FINTEK F81216H
| AMD_PI_00630F01
| AMD_PI_00630F01
| SOIC-8
| SPI
| style="background:red" | N
| ?
| —


Console drivers have unpredictable behaviour if multiple threads
attempt to share the same resources without a spinlock.
If unsure, say Y.
||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| AMD
| CONSOLE_SERIAL || console || bool || Serial port console output ||  
| [[Board:amd/mahogany|DB780E (Mahogany)]]
Send coreboot debug output to a serial port.
| style="background:red" | Unknown
 
| AMD AMDK8
The type of serial port driver selected based on your configuration is
| AMD RS780
shown on the following menu line. Supporting multiple different types
AMD SB700
of UARTs in one build is not supported.
| ITE™ IT8718F
| ?
| Socket AM2
| ?
| SPI
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
| || || (comment) || || I/O mapped, 8250-compatible ||
|- bgcolor="#eeeeee"
| || || (comment) || || memory mapped, 8250-compatible ||
|- bgcolor="#eeeeee"
| || || (comment) || || device-specific UART ||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| AMD
| UART_FOR_CONSOLE || console || int || Index for UART port to use for console ||  
| [[Board:amd/mahogany_fam10|Mahogany (Fam10)]]
Select an I/O port to use for serial console:
| style="background:red" | Unknown
0 = 0x3f8, 1 = 0x2f8, 2 = 0x3e8, 3 = 0x2e8
| AMD Family 10h
| AMD RS780
AMD SB700
| ITE™ IT8718F
| AMD Athlon™ 64 / X2 / FX, Sempron™
| Socket AM2+
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| AMD
| TTYS0_BASE || console || hex || ||  
| [[Board:amd/norwich|Norwich]]
Map the COM port number to the respective I/O port.
| style="background:red" | Unknown
| AMD LX
| AMD CS5536
|  
| AMD Geode™ LX
| —
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
| || || (comment) || || Serial port base address = 0x3f8 ||
|- bgcolor="#eeeeee"
| || || (comment) || || Serial port base address = 0x2f8 ||
|- bgcolor="#eeeeee"
| || || (comment) || || Serial port base address = 0x3e8 ||
|- bgcolor="#eeeeee"
| || || (comment) || || Serial port base address = 0x2e8 ||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| AMD
| UART_OVERRIDE_BAUDRATE || console || boolean || ||  
| [[Board:amd/olivehill|DB-FT3]]
Set to "y" when the platform overrides the baudrate by providing
| style="background:#FFff00" | [[#amd/olivehill|2014-10-08T13:44:17Z]]
a get_uart_baudrate routine.
| AMD Family 16h KB (AGESA)
| AMD AGESA YANGTZE
|  
| AMD Family 16h KB (AGESA)
| ?
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_921600 || console || bool || 921600 ||
Set serial port Baud rate to 921600.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_460800 || console || bool || 460800 ||
Set serial port Baud rate to 460800.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_230400 || console || bool || 230400 ||
Set serial port Baud rate to 230400.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_115200 || console || bool || 115200 ||
Set serial port Baud rate to 115200.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_57600 || console || bool || 57600 ||
Set serial port Baud rate to 57600.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_38400 || console || bool || 38400 ||
Set serial port Baud rate to 38400.
||
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_19200 || console || bool || 19200 ||
Set serial port Baud rate to 19200.
||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| [http://wwwd.amd.com/amd/devsite.nsf/platforms/DB-FT3.htm AMD]
| CONSOLE_SERIAL_9600 || console || bool || 9600 ||  
| [[Board:amd/olivehillplus|DB-FT3b (Olive Hill+)]]
Set serial port Baud rate to 9600.
| style="background:#FFff00" | [[#amd/olivehillplus|2014-09-24T05:58:25Z]]
| AMD 00730F01 (PI)
| AMD PI AVALON
|  
| AMD_PI_00730F01
| AMD_PI_00730F01
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| AMD
| TTYS0_BAUD || console || int || ||  
| [[Board:amd/parmer|DB-FS1r2 (Parmer)]]
Map the Baud rates to an integer.
| style="background:red" | Unknown
| AMD Family 15h TN (AGESA)
| AMD AGESA HUDSON
|  
| AMD Family 15h TN (AGESA)
| ?
| SOIC-8
| SPI
| style="background:red" | N
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| AMD
| SPKMODEM || console || bool || spkmodem (console on speaker) console output ||  
| [[Board:amd/persimmon|DBFT1-00-EVAL-KT (Persimmon)]]
Send coreboot debug output through speaker
| style="background:#FFff00" | [[#amd/persimmon|2017-08-29T11:37:06Z]]
| AMD Family 14h (AGESA)
| AMD CIMX SB800
| FINTEK F81865F
| AMD Family 14h (AGESA)
| ?
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| AMD
| CONSOLE_USB || console || bool || USB dongle console output ||  
| [[Board:amd/pistachio|Pistachio]]
Send coreboot debug output to USB.
| style="background:red" | Unknown
 
| AMD AMDK8
Configuration for USB hardware is under menu Generic Drivers.
| AMD RS690
AMD SB600
|  
| ?
| Socket AM2
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| AMD
| ONBOARD_VGA_IS_PRIMARY || console || bool || Use onboard VGA as primary video device ||  
| [[Board:amd/south_station|South Station]]
If not selected, the last adapter found will be used.
| style="background:red" | Unknown
| AMD Family 14h (AGESA)
| AMD CIMX SB800
| FINTEK F81865F
| AMD Family 14h (AGESA)
| ?
| SOIC8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| AMD
| CONSOLE_NE2K || console || bool || Network console over NE2000 compatible Ethernet adapter ||  
| [[Board:amd/thatcher|DB-FP2 (Thatcher)]]
Send coreboot debug output to a Ethernet console, it works
| style="background:#FFff00" | [[#amd/thatcher|2016-02-04T18:30:40Z]]
same way as Linux netconsole, packets are received to UDP
| AMD Family 15h TN (AGESA)
port 6666 on IP/MAC specified with options bellow.
| AMD AGESA HUDSON
Use following netcat command: nc -u -l -p 6666
| SMSC® LPC47N217
| AMD Family 15h TN (AGESA)
| ?
| SOIC-8
| SPI
| style="background:red" | N
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| AMD
| CONSOLE_NE2K_DST_MAC || console || string || Destination MAC address of remote system ||  
| [[Board:amd/tilapia_fam10|Tilapia (Fam10)]]
Type in either MAC address of logging system or MAC address
| style="background:red" | Unknown
of the router.
| AMD Family 10h
| AMD RS780
AMD SB700
| ITE™ IT8718F
| AMD Athlon™ 64 / FX / X2
| Socket AM3
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| AMD
| CONSOLE_NE2K_DST_IP || console || string || Destination IP of logging system ||  
| [[Board:amd/torpedo|Torpedo]]
This is IP address of the system running for example
| style="background:red" | Unknown
netcat command to dump the packets.
| AMD Family 12h (AGESA)
| AMD CIMX SB900
| SMSC® KBC1100
| AMD Family 12h (AGESA)
| ?
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| AMD
| CONSOLE_NE2K_SRC_IP || console || string || IP address of coreboot system ||  
| [[Board:amd/union_station|Union Station]]
This is the IP of the coreboot system
| style="background:red" | Unknown
| AMD Family 14h (AGESA)
| AMD CIMX SB800
|  
| AMD Family 14h (AGESA)
| ?
| SOIC8
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| BAP
|- bgcolor="#eeeeee"
| [[Board:bap/ode_e20XX|ODE_E20XX]]
| CONSOLE_NE2K_IO_PORT || console || hex || NE2000 adapter fixed IO port address ||  
| style="background:red" | Unknown
This is the IO port address for the IO port
| AMD Family 16h KB (AGESA)
on the card, please select some non-conflicting region,
| AMD AGESA YANGTZE
32 bytes of IO spaces will be used (and align on 32 bytes
| FINTEK F81866D
boundary, qemu needs broader align)
| AMD Family 16h KB (AGESA)
| ?
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| [http://www.unibap.com/advanced-heterogeneous-computing-modules/ BAP]
|- bgcolor="#eeeeee"
| [[Board:bap/ode_e21XX|ODE_e21xx]]
| CONSOLE_CBMEM || console || bool || Send console output to a CBMEM buffer ||  
| style="background:red" | Unknown
Enable this to save the console output in a CBMEM buffer. This would
| AMD 00730F01 (PI)
allow to see coreboot console output from Linux space.
| AMD PI AVALON
| FINTEK F81866D
| AMD_PI_00730F01
| AMD_PI_00730F01
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Biostar
| CONSOLE_CBMEM_BUFFER_SIZE || console || hex || Room allocated for console output in CBMEM ||  
| [[Board:biostar/a68n_5200|A68N5200]]
Space allocated for console output storage in CBMEM. The default
| style="background:red" | Unknown
value (128K or 0x20000 bytes) is large enough to accommodate
| AMD Family 16h KB (AGESA)
even the BIOS_SPEW level.
| AMD AGESA YANGTZE
| ITE™ IT8728F
| AMD Family 16h KB (AGESA)
| ?
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| Broadcom
|- bgcolor="#eeeeee"
| [[Board:broadcom/blast|Blast]]
| CONSOLE_CBMEM_DUMP_TO_UART || console || bool || Dump CBMEM console on resets ||  
| style="background:red" | Unknown
Enable this to have CBMEM console buffer contents dumped on the
| AMD AMDK8
serial output in case serial console is disabled and the device
| BROADCOM BCM5780
resets itself while trying to boot the payload.
BROADCOM BCM5785
| NSC PC87417
| AMD Opteron™
| Socket 940
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| GizmoSphere
| CONSOLE_SPI_FLASH || console || bool || SPI Flash console output ||  
| [[Board:gizmosphere/gizmo2|Gizmo2]]
Send coreboot debug output to the SPI Flash in the FMAP CONSOLE area
| style="background:red" | Unknown
| AMD Family 16h KB (AGESA)
| AMD AGESA YANGTZE
|  
| AMD Family 16h KB (AGESA)
| ?
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
This option can cause premature wear on the SPI flash and should not
| Google
be used as a normal means of debugging. It is only to be enabled and
( Google )
used when porting a new motherboard which has no other console
| [[Board:google/cheza|Cheza Qualcomm SDM845 reference board]]
available (no UART, no POST, no cbmem access(non bootable)). Since
| style="background:red" | Unknown
a non bootable machine will require the use of an external SPI Flash
|
programmer, the developer can grab the console log at the same time.
|
|
|
|
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
The flash console will not be erased on reboot, so once it is full,
| Google
the flashconsole driver will stop writing to it. This is to avoid
( Google )
wear on the flash, and to avoid erasing sectors (which may freeze
| [[Board:google/foster|Foster Nvidia Tegra210 reference board]]
the SPI controller on skylake).
| style="background:red" | Unknown
|
|
|
|
|
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
The 'CONSOLE' area can be extracted from the FMAP with :
| Google
cbfstool rom.bin read -r CONSOLE -f console.log
( Google )
| [[Board:google/gale|Gale]]
| style="background:red" | Unknown
|
|
|
|
|
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| Google
|- bgcolor="#eeeeee"
( Google )
| CONSOLE_SPI_FLASH_BUFFER_SIZE || console || hex || Room allocated for console output in FMAP ||  
| [[Board:google/gru|Gru Rockchip RK3399 reference board]]
Space allocated for console output storage in FMAP. The default
| style="background:red" | Unknown
value (128K or 0x20000 bytes) is large enough to accommodate
|  
even the BIOS_SPEW level.
|  
|  
|  
|
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| Google
|- bgcolor="#eeeeee"
| [[Board:google/kahlee|KAHLEE]]
| CONSOLE_QEMU_DEBUGCON || console || bool || QEMU debug console output ||  
| style="background:red" | Unknown
Send coreboot debug output to QEMU's isa-debugcon device:
|  
|  
|  
|  
|
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
qemu-system-x86_64 \
| Google
-chardev file,id=debugcon,path=/dir/file.log \
( Google )
-device isa-debugcon,iobase=0x402,chardev=debugcon
| [[Board:google/purin|Purin Broadcom Cygnus reference board]]
| style="background:red" | Unknown
|
|
|
|
|
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| Google
|- bgcolor="#eeeeee"
( Google )
| SPI_CONSOLE || console || bool || SPI debug console output ||  
| [[Board:google/urara|Urara Imgtec Pistachio reference board]]
Enable support for the debug console on the Dediprog EM100Pro.
| style="background:red" | Unknown
This is currently working only in ramstage due to how the spi
|  
drivers are written.
|  
|  
| IMGTEC_PISTACHIO
| IMGTEC_PISTACHIO
| ?
| SPI
| style="background:red" | N
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Intel
| CONSOLE_OVERRIDE_LOGLEVEL || console || boolean || ||  
( Intel )
Set to "y" when the platform overrides the loglevel by providing
| [[Board:intel/apollolake_rvp|Apollolake RVP Reference Board]]
a get_console_loglevel routine.
| style="background:red" | Unknown
|  
|  
|  
|  
|  
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Intel
| DEFAULT_CONSOLE_LOGLEVEL_8 || console || bool || 8: SPEW ||
| [[Board:intel/baskingridge|BASKING RIDGE]]
Way too many details.
| style="background:red" | Unknown
||
| Intel® HASWELL
|- bgcolor="#eeeeee"
| Intel® LYNXPOINT
| DEFAULT_CONSOLE_LOGLEVEL_7 || console || bool || 7: DEBUG ||  
|  
Debug-level messages.
| Intel® 4th Gen (Haswell) Core i3/i5/i7
||
| ?
|- bgcolor="#eeeeee"
| ?
| DEFAULT_CONSOLE_LOGLEVEL_6 || console || bool || 6: INFO ||
| ?
Informational messages.
| ?
||
| ?
|- bgcolor="#eeeeee"
| —
| DEFAULT_CONSOLE_LOGLEVEL_5 || console || bool || 5: NOTICE ||  
Normal but significant conditions.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_4 || console || bool || 4: WARNING ||  
Warning conditions.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_3 || console || bool || 3: ERR ||
Error conditions.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_2 || console || bool || 2: CRIT ||
Critical conditions.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_1 || console || bool || 1: ALERT ||
Action must be taken immediately.
||
|- bgcolor="#eeeeee"
| DEFAULT_CONSOLE_LOGLEVEL_0 || console || bool || 0: EMERG ||
System is unusable.


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Intel
| DEFAULT_CONSOLE_LOGLEVEL || console || int || ||  
| [[Board:intel/bayleybay_fsp|Bayley Bay]]
Map the log level config names to an integer.
| style="background:#FFff00" | [[#intel/bayleybay_fsp|2014-06-25T23:32:28Z]]
|  
|  
|  
|  
|  
| ?
| SPI
| style="background:red" | N
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Intel
| CMOS_POST || console || bool || Store post codes in CMOS for debugging ||  
| [[Board:intel/camelbackmountain_fsp|Camelback Mountain]]
If enabled, coreboot will store post codes in CMOS and switch between
| style="background:#0Dff00" | [[#intel/camelbackmountain_fsp|2018-05-04T10:30:24Z]]
two offsets on each boot so the last post code in the previous boot
|  
can be retrieved.  This uses 3 bytes of CMOS.
|  
|  
|  
|  
| ?
| SPI
| yes
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Intel
| CMOS_POST_OFFSET || console || hex || Offset into CMOS to store POST codes ||  
( Intel )
If CMOS_POST is enabled then an offset into CMOS must be provided.
| [[Board:intel/cannonlake_rvp|Cannonlake rvp]]
If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value
| style="background:red" | Unknown
defined in the mainboard option table.
|
|
|  
|  
|  
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Intel
| CMOS_POST_EXTRA || console || bool || Store extra logging info into CMOS ||  
| [[Board:intel/cougar_canyon2|Cougar Canyon 2]]
This will enable extra logging of work that happens between post
| style="background:red" | Unknown
codes into CMOS for debug.  This uses an additional 8 bytes of CMOS.
| Intel® IVYBRIDGE (FSP)
| Intel® FSP BD82X6X
| SMSC® SIO1007
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
| Socket RPGA989
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Intel
| CONSOLE_POST || console || bool || Show POST codes on the debug console ||  
| [[Board:intel/emeraldlake2|EMERALD LAKE 2]]
If enabled, coreboot will additionally print POST codes (which are
| style="background:red" | Unknown
usually displayed using a so-called "POST card" ISA/PCI/PCI-E
| Intel® IVYBRIDGE
device) on the debug console.
| Intel® C216
| SMSC® SIO1007
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
| Socket RPGA989
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Intel
| POST_IO || console || bool || Send POST codes to an IO port ||  
( Intel )
If enabled, POST codes will be written to an IO port.
| [[Board:intel/harcuvar|Harcuvar]]
| style="background:red" | Unknown
|
|
|  
|
|  
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Intel
| POST_IO_PORT || console || hex || IO port for POST codes ||  
( Intel )
POST codes on x86 are typically written to the LPC bus on port
| [[Board:intel/kblrvp|Kabylake RVP Reference Board]]
0x80. However, it may be desirable to change the port number
| style="background:red" | Unknown
depending on the presence of coprocessors/microcontrollers or if the
|  
platform does not support IO in the conventional x86 manner.
|  
|  
|  
|
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Intel
| NO_EARLY_BOOTBLOCK_POSTCODES || console || hex || ||  
( Intel )
Some chipsets require that the routing for the port 80h POST
| [[Board:intel/leafhill|Leafhill Reference Board]]
code be configured before any POST codes are sent out.
| style="background:red" | Unknown
This can be done in the boot block, but there are a couple of
|  
POST codes that go out before the chipset's bootblock initialization
|  
can happen.  This option suppresses those POST codes.
|
 
|
||
|
| ?
| SPI
| style="background:lime" | Y
| style="background:lime" | Y
| —


|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Intel
| ACPI_HUGE_LOWMEM_BACKUP || toplevel || bool || ||  
| [[Board:intel/littleplains|Little Plains]]
On S3 resume path, backup low memory from RAMBASE..RAMTOP in CBMEM.
| style="background:red" | Unknown
| Intel® RANGELEY (FSP)
| Intel® FSP RANGELEY
|  
| INTEL_FSP_RANGELEY
| Socket RPGA989
| ?
| SPI
| ?
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Intel
| RESUME_PATH_SAME_AS_BOOT || toplevel || bool || ||  
( Intel )
This option indicates that when a system resumes it takes the
| [[Board:intel/minnow3|MinnowBoard 3]]
same path as a regular boot. e.g. an x86 system runs from the
| style="background:red" | Unknown
reset vector at 0xfffffff0 on both resume and warm/cold boot.
|  
|
|  
|  
|  
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Intel
| HAVE_HARD_RESET || toplevel || bool || ||  
| [[Board:intel/mohonpeak|Mohon Peak CRB]]
This variable specifies whether a given board has a hard_reset
| style="background:red" | Unknown
function, no matter if it's provided by board code or chipset code.
| Intel® RANGELEY (FSP)
| Intel® FSP RANGELEY
|  
| INTEL_FSP_RANGELEY
| Socket RPGA989
| ?
| SPI
| ?
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Intel
| HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK || toplevel || bool ||  ||  
( Intel )
This should be enabled on certain plaforms, such as the AMD
| [[Board:intel/saddlebrook|Saddle Brook Skylake Reference Board]]
SR565x, that cannot handle concurrent CBFS accesses from
| style="background:red" | Unknown
multiple APs during early startup.
|  
|  
| Nuvoton NCT6776
Nuvoton  NCT6776 COM A
|
|  
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Intel
| HAVE_MONOTONIC_TIMER || toplevel || bool || ||  
| [[Board:intel/stargo2|Stargo2]]
The board/chipset provides a monotonic timer.
| style="background:red" | Unknown
| Intel® IVYBRIDGE (FSP)
| Intel® FSP I89XX
| Winbond™ WPCD376I
INTEL I8900
| INTEL_SOCKET_BGA1284
| INTEL_SOCKET_BGA1284
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Intel
| GENERIC_UDELAY || toplevel || bool || ||  
| [[Board:intel/wtm2|WHITETIP MOUNTAIN 2]]
The board/chipset uses a generic udelay function utilizing the
| style="background:red" | Unknown
monotonic timer.
|  
|  
|  
|  
|
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| [https://www.google.com/search?q=Tutorial+for+the+debug+preview+of+lowRISC&oq=Tutorial+for+the+debug+preview+of+lowRISC&btnI lowrisc]
|- bgcolor="#eeeeee"
| [[Board:lowrisc/nexys4ddr|lowrisc nexys4ddr]]
| TIMER_QUEUE || toplevel || bool || ||  
| style="background:red" | Unknown
Provide a timer queue for performing time-based callbacks.
|  
|  
|  
|  
|  
| ?
| ?
| ?
| ?
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| NVIDIA
| COOP_MULTITASKING || toplevel || bool || ||  
| [[Board:nvidia/l1_2pvv|l1_2pvv]]
Cooperative multitasking allows callbacks to be multiplexed on the
| style="background:red" | Unknown
main thread of ramstage. With this enabled it allows for multiple
| AMD AMDK8
execution paths to take place when they have udelay() calls within
| NVIDIA MCP55
their code.
| Winbond™ W83627EHG
| AMD Opteron™
| Socket F
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| [https://www.crowdsupply.com/sifive/hifive-unleashed SiFive]
|- bgcolor="#eeeeee"
| [[Board:sifive/hifive-unleashed|HiFive Unleashed]]
| NUM_THREADS || toplevel || int || ||  
| style="background:red" | Unknown
How many execution threads to cooperatively multitask with.
|  
|  
|  
|  
|  
| SOIC-16
| SPI
| style="background:red" | N
| style="background:red" | N
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| VIA
| HAVE_OPTION_TABLE || toplevel || bool || ||  
| [[Board:via/vt8454c|VT8454c]]
This variable specifies whether a given board has a cmos.layout
| style="background:red" | Unknown
file containing NVRAM/CMOS bit definitions.
| VIA CX700
It defaults to 'n' but can be selected in mainboard/*/Kconfig.
|  
| VIA VT1211
| VIA C7™
| ?
| ?
| ?
| ?
| ?
| —


|- bgcolor="#6699ff"
||
| colspan="13" | <h4>Single-Board computer</h4>
|- bgcolor="#eeeeee"
| GFXUMA || toplevel || bool ||  ||  
Enable Unified Memory Architecture for graphics.


|- bgcolor="#dddddd"
||
| CompuLab
|- bgcolor="#eeeeee"
( CompuLab )
| HAVE_ACPI_TABLES || toplevel || bool || ||  
| [[Board:compulab/intense_pc|Intense-PC]]
This variable specifies whether a given board has ACPI table support.
| style="background:red" | Unknown
It is usually set in mainboard/*/Kconfig.
| Intel® IVYBRIDGE
| Intel® C216
| SMSC® SIO1007
| INTEL_SOCKET_FCBGA1023
| INTEL_SOCKET_FCBGA1023
| SOIC-16
| SPI
| style="background:red" | N
| style="background:red" | N
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Cubietech
| HAVE_MP_TABLE || toplevel || bool || ||  
| [[Board:cubietech/cubieboard|Cubieboard A10]]
This variable specifies whether a given board has MP table support.
| style="background:red" | Unknown
It is usually set in mainboard/*/Kconfig.
|  
Whether or not the MP table is actually generated by coreboot
|  
is configurable by the user via GENERATE_MP_TABLE.
|  
| Allwinner A10
| ?
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| ELMEX
|- bgcolor="#eeeeee"
| [[Board:elmex/pcm205400|PCM205400]]
| HAVE_PIRQ_TABLE || toplevel || bool || ||  
| style="background:red" | Unknown
This variable specifies whether a given board has PIRQ table support.
| AMD Family 14h (AGESA)
It is usually set in mainboard/*/Kconfig.
| AMD CIMX SB800
Whether or not the PIRQ table is actually generated by coreboot
| FINTEK F81865F
is configurable by the user via GENERATE_PIRQ_TABLE.
| AMD Family 14h (AGESA)
| ?
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| ELMEX
|- bgcolor="#eeeeee"
| [[Board:elmex/pcm205401|PCM205401]]
| MAX_PIRQ_LINKS || toplevel || int || ||  
| style="background:red" | Unknown
This variable specifies the number of PIRQ interrupt links which are
|  
routable. On most chipsets, this is 4, INTA through INTD. Some
|  
chipsets offer more than four links, commonly up to INTH. They may
|  
also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
|  
table specifies links greater than 4, pirq_route_irqs will not
|
function properly, unless this variable is correctly set.
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| electronic system design
| ACPI_NHLT || toplevel || bool || ||  
| [[Board:esd/atom15|esd atom15]]
Build support for NHLT (non HD Audio) ACPI table generation.
| style="background:red" | Unknown
|
|  
|  
|  
|  
| ?
| SPI
| ?
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| Intel
|- bgcolor="#6699dd"
| [[Board:intel/galileo|Galileo]]
! align="left" | Menu: System tables || || || ||
| style="background:red" | Unknown
|- bgcolor="#eeeeee"
|  
| GENERATE_MP_TABLE || toplevel || bool || Generate an MP table ||  
|  
Generate an MP table (conforming to the Intel MultiProcessor
|  
specification 1.4) for this board.
|  
|  
| ?
| SPI
| ?
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
If unsure, say Y.
| Intel
| [[Board:intel/minnowmax|Minnow Max]]
| style="background:#FDff00" | [[#intel/minnowmax|2017-09-06T06:53:39Z]]
|
|
|
|
|
| ?
| SPI
| ?
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| TI
| GENERATE_PIRQ_TABLE || toplevel || bool || Generate a PIRQ table ||  
| [[Board:ti/beaglebone|Beaglebone]]
Generate a PIRQ table for this board.
| style="background:red" | Unknown
|  
|  
|  
| TI AM335X
| ?
| ?
| ?
| ?
| ?
| —


|- bgcolor="#6699ff"
If unsure, say Y.
| colspan="13" | <h4>Emulation</h4>


|- bgcolor="#dddddd"
||
| [http://wiki.qemu.org/Main_Page Emulation]
|- bgcolor="#eeeeee"
| [[Board:emulation/qemu-armv7|QEMU armv7 (vexpress-a9)]]
| GENERATE_SMBIOS_TABLES || toplevel || bool || Generate SMBIOS tables ||  
| style="background:red" | Unknown
Generate SMBIOS tables for this board.
|  
|  
|  
| ARM Cortex A9
| ?
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
If unsure, say Y.
| [http://wiki.qemu.org/Main_Page Emulation]
| [[Board:emulation/qemu-i440fx|QEMU x86 i440fx/piix4]]
| style="background:#FFff00" | [[#emulation/qemu-i440fx|2017-05-17T17:09:18Z]]
|
| Intel® I82371EB
|
| QEMU x86
| —
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| Emulation
|- bgcolor="#eeeeee"
| [[Board:emulation/qemu-power8|QEMU POWER8]]
| MAINBOARD_SERIAL_NUMBER || toplevel || string || SMBIOS Serial Number ||  
| style="background:red" | Unknown
The Serial Number to store in SMBIOS structures.
|  
|  
|  
|  
|  
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| [http://wiki.qemu.org/Main_Page Emulation]
|- bgcolor="#eeeeee"
| [[Board:emulation/qemu-q35|QEMU x86 q35/ich9]]
| MAINBOARD_VERSION || toplevel || string || SMBIOS Version Number ||  
| style="background:#64ff00" | [[#emulation/qemu-q35|2018-02-06T06:14:30Z]]
The Version Number to store in SMBIOS structures.
|  
| Intel® I82801IX
|  
| QEMU x86
| —
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| [https://github.com/riscv/riscv-qemu Emulation]
|- bgcolor="#eeeeee"
| [[Board:emulation/qemu-riscv|QEMU RISCV]]
| MAINBOARD_SMBIOS_MANUFACTURER || toplevel || string || SMBIOS Manufacturer ||  
| style="background:red" | Unknown
Override the default Manufacturer stored in SMBIOS structures.
|  
|  
|  
|  
|  
| ?
| ?
| ?
| ?
| —


|- bgcolor="#dddddd"
||
| [https://github.com/riscv/riscv-isa-sim Emulation]
|- bgcolor="#eeeeee"
| [[Board:emulation/spike-riscv|Spike RISCV]]
| MAINBOARD_SMBIOS_PRODUCT_NAME || toplevel || string || SMBIOS Product name ||  
| style="background:red" | Unknown
Override the default Product name stored in SMBIOS structures.
|  
|  
|  
|  
|  
| ?
| ?
| ?
| ?
| —


|- bgcolor="#6699ff"
||
| colspan="13" | <h4>Miscellaneous</h4>
|- bgcolor="#eeeeee"
| SMBIOS_ENCLOSURE_TYPE || toplevel || hex ||  ||  
System Enclosure or Chassis Types as defined in SMBIOS specification.
The default value is SMBIOS_ENCLOSURE_DESKTOP (0x03) or
SMBIOS_ENCLOSURE_LAPTOP (0x09) if SYSTEM_TYPE_LAPTOP is set.


|- bgcolor="#dddddd"
||
| Google
 
( Google )
|- bgcolor="#6699dd"
| [[Board:google/smaug|Smaug Nvidia Tegra210 tablet]]
! align="left" | Menu: Payload || || || ||
| style="background:red" | Unknown
|- bgcolor="#eeeeee"
|  
| PAYLOAD_NONE || payloads || bool || None ||  
|  
Select this option if you want to create an "empty" coreboot
|  
ROM image for a certain mainboard, i.e. a coreboot ROM image
|  
which does not yet contain a payload.
|  
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
For such an image to be useful, you have to use 'cbfstool'
| Google
to add a payload to the ROM image later.
( Google )
| [[Board:google/veyron|Veyron Rockchip RK3288 boards]]
| style="background:red" | Unknown
|
|
|
|
|
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
||
| Google
|- bgcolor="#eeeeee"
( Google )
| PAYLOAD_ELF || payloads || bool || An ELF executable payload ||  
| [[Board:google/veyron_mickey|Veyron Mickey Rockchip RK3288 board]]
Select this option if you have a payload image (an ELF file)
| style="background:red" | Unknown
which coreboot should run as soon as the basic hardware
|  
initialization is completed.
|  
|  
|  
|
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


|- bgcolor="#dddddd"
You will be able to specify the location and file name of the
| Google
payload image later.
( Google )
| [[Board:google/veyron_rialto|Veyron Rialto Rockchip RK3288 board]]
| style="background:red" | Unknown
|
|
|
|
|
| ?
| SPI
| style="background:red" | N
| style="background:lime" | Y
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Siemens
| PAYLOAD_BAYOU || payloads || bool || Bayou ||  
( Siemens )
Select this option if you want to set bayou as your primary
| [[Board:siemens/mc_apl1|MC APL1]]
payload.
| style="background:red" | Unknown
|  
|  
|  
|  
|
| ?
| SPI
| no
| yes
| —


||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Siemens
| PAYLOAD_UBOOT || payloads/external/U-Boot.name || bool || U-Boot (Experimental) ||  
| [[Board:siemens/mc_bdx1|MC BDX1]]
Select this option if you want to build a coreboot image
| style="background:red" | Unknown
with a U-Boot payload.
|  
|  
|  
|  
|
| ?
| SPI
| no
| ?
| —


See https://coreboot.org/Payloads and U-Boot's documentation
at http://git.denx.de/?p=u-boot.git;a=blob;f=doc/README.x86
for more information.
||
||
|- bgcolor="#eeeeee"
|- bgcolor="#eeeeee"
| Siemens
| PAYLOAD_SEABIOS || payloads/external/SeaBIOS.name || bool || SeaBIOS ||  
| [[Board:siemens/mc_tcu3|TCU3]]
Select this option if you want to build a coreboot image
| style="background:#FFff00" | [[#siemens/mc_tcu3|2016-05-09T06:14:45Z]]
with a SeaBIOS payload. If you don't know what this is
|  
about, just leave it enabled.
|  
|  
|  
|  
| ?
| SPI
| style="background:red" | N
| ?
| —


|- bgcolor="#6699ff"
See https://coreboot.org/Payloads for more information.
| colspan="13" | <h4>Unclassified</h4>


|}
||
<small>
||
<sup>1</sup> ROM chip package (PLCC, DIP32, DIP8, SOIC8).<br />
|- bgcolor="#eeeeee"
<sup>2</sup> ROM chip protocol/type (parallel flash, LPC, FWH, SPI).<br />
| PAYLOAD_FILO || payloads/external/FILO.name || bool || FILO ||
<sup>3</sup> ROM chip socketed (Y/N)?<br />
Select this option if you want to build a coreboot image
<sup>4</sup> Board supported by [http://www.flashrom.org flashrom] (Y/N)?<br />
with a FILO payload. If you don't know what this is
<sup>5</sup> Vendor Cooperation Score.<br />
about, just leave it enabled.
<sup>6</sup> [http://www.flashrom.org flashrom] does not work when the vendor BIOS is booted, but it does work when the machine is booted with coreboot.<br />
 
<sup>7</sup> Some boards have ROM sockets, others are soldered.<br />
See https://coreboot.org/Payloads for more information.
</small>
 
= 2018W20 =
||
<span id="lenovo/x230"></span>
||
[[Board:lenovo/x230|lenovo/x230]] at Wed May 16 07:45:28 UTC 2018
|- bgcolor="#eeeeee"
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=d8ec973fd24e091d0038d7060bfb516bad7534f0 upstream tree] (
| PAYLOAD_LINUX || payloads/external/linux.name || bool || A Linux payload ||
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x230/4.8-5-gfaafbfb81e-dirty/2018-05-16T07_45_28Z/cbfs.txt cbfs.txt]
Select this option if you have a Linux bzImage which coreboot
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x230/4.8-5-gfaafbfb81e-dirty/2018-05-16T07_45_28Z/config.short.txt config.short.txt]
should run as soon as the basic hardware initialization
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x230/4.8-5-gfaafbfb81e-dirty/2018-05-16T07_45_28Z/config.txt config.txt]
is completed.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x230/4.8-5-gfaafbfb81e-dirty/2018-05-16T07_45_28Z/coreboot_console.txt coreboot_console.txt]
 
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x230/4.8-5-gfaafbfb81e-dirty/2018-05-16T07_45_28Z/coreboot_timestamps.txt coreboot_timestamps.txt]
You will be able to specify the location and file name of the
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x230/4.8-5-gfaafbfb81e-dirty/2018-05-16T07_45_28Z/kernel_log.txt kernel_log.txt]
payload image later.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x230/4.8-5-gfaafbfb81e-dirty/2018-05-16T07_45_28Z/payload_config.txt payload_config.txt]
 
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x230/4.8-5-gfaafbfb81e-dirty/2018-05-16T07_45_28Z/rom_checksum.txt rom_checksum.txt]
||
)
||
|- bgcolor="#eeeeee"
| PAYLOAD_TIANOCORE || payloads/external/tianocore.name || bool || Tianocore coreboot payload package ||
Select this option if you want to build a coreboot image
with a Tianocore payload. If you don't know what this is
about, just leave it enabled.
 
See https://coreboot.org/Payloads for more information.
 
||
||
|- bgcolor="#eeeeee"
| PAYLOAD_GRUB2 || payloads/external/GRUB2.name || bool || GRUB2 ||
Select this option if you want to build a coreboot image
with a GRUB2 payload. If you don't know what this is
about, just leave it enabled.
 
See https://coreboot.org/Payloads for more information.
 
||
||
|- bgcolor="#eeeeee"
| PAYLOAD_DEPTHCHARGE || payloads/external/depthcharge.name || bool || Depthcharge ||
Select this option if you want to build a coreboot image
with a depthcharge payload.
 
See https://coreboot.org/Payloads for more information.
 
||
 
||
|- bgcolor="#eeeeee"
| UBOOT_STABLE || payloads/external/U-Boot || bool || v2016.1 ||
Stable U-Boot version
 
||
|- bgcolor="#eeeeee"
| UBOOT_MASTER || payloads/external/U-Boot || bool || master ||
Newest U-Boot version
 
||
|- bgcolor="#eeeeee"
| PAYLOAD_CONFIGFILE || payloads/external/U-Boot || string || U-Boot config file ||
This option allows a platform to set Kconfig options for a basic
U-Boot payload.  In general, if the option is used, the default
would be "$(top)/src/mainboard/$(MAINBOARDDIR)/config_uboot"
for a config stored in the coreboot mainboard directory, or
"$(project_dir)/configs/coreboot-x86_defconfig" to use a config
from the U-Boot config directory
 
||
|- bgcolor="#eeeeee"
| SEABIOS_STABLE || payloads/external/SeaBIOS || bool || 1.11.1 ||
Stable SeaBIOS version
||
|- bgcolor="#eeeeee"
| SEABIOS_MASTER || payloads/external/SeaBIOS || bool || master ||
Newest SeaBIOS version
||
|- bgcolor="#eeeeee"
| SEABIOS_REVISION || payloads/external/SeaBIOS || bool || git revision ||
Select this option if you have a specific commit or branch
that you want to use as the revision from which to
build SeaBIOS.
 
You will be able to specify the name of a branch or a commit id
later.
 
||
|- bgcolor="#eeeeee"
| SEABIOS_REVISION_ID || payloads/external/SeaBIOS || string || Insert a commit's SHA-1 or a branch name ||
The commit's SHA-1 or branch name of the revision to use.
 
||
|- bgcolor="#eeeeee"
| SEABIOS_PS2_TIMEOUT || payloads/external/SeaBIOS || int || PS/2 keyboard controller initialization timeout (milliseconds) ||
Some PS/2 keyboard controllers don't respond to commands immediately
after powering on. This specifies how long SeaBIOS will wait for the
keyboard controller to become ready before giving up.
 
||
|- bgcolor="#eeeeee"
| SEABIOS_THREAD_OPTIONROMS || payloads/external/SeaBIOS || bool || Hardware init during option ROM execution ||
Allow hardware init to run in parallel with optionrom execution.
 
This can reduce boot time, but can cause some timing
variations during option ROM code execution. It is not
known if all option ROMs will behave properly with this option.
 
||
|- bgcolor="#eeeeee"
| SEABIOS_VGA_COREBOOT || payloads/external/SeaBIOS || bool || Include generated option rom that implements legacy VGA BIOS compatibility ||
coreboot can initialize the GPU of some mainboards.
 
After initializing the GPU, the information about it can be passed to the payload.
Provide an option rom that implements this legacy VGA BIOS compatibility requirement.
 
||
|- bgcolor="#eeeeee"
| PAYLOAD_CONFIGFILE || payloads/external/SeaBIOS || string || SeaBIOS config file ||
This option allows a platform to set Kconfig options for a basic
SeaBIOS payload.  In general, if the option is used, the default
would be "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios"
 
||
|- bgcolor="#eeeeee"
| SEABIOS_BOOTORDER_FILE || payloads/external/SeaBIOS || string || SeaBIOS bootorder file ||
Add a SeaBIOS bootorder file. From the wiki:
"The bootorder file may be used to configure the boot up order. The file
should be ASCII text and contain one line per boot method. The description
of each boot method follows an Open Firmware device path format. SeaBIOS
will attempt to boot from each item in the file - first line of the file
first."
 
See: https://www.coreboot.org/SeaBIOS#Configuring_boot_order
 
If used, a typical value would be:
$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder
 
||
|- bgcolor="#eeeeee"
| SEABIOS_DEBUG_LEVEL || payloads/external/SeaBIOS || int || SeaBIOS debug level (verbosity) ||
The higher the number, the more verbose SeaBIOS will be. See the table
below for the current values corresponding to various items as of SeaBIOS
version 1.10.1. Set this value to -1 to use SeaBIOS' default.
 
Output at various SeaBIOS log levels:
level 0  - Logging disabled
level 1  - Basic output, interrupts 5, 18h, 19h, 40h, SMP, PNP, PMM
level 2  - AHCI, Floppy, Basic ps2, interrupts 11h, 12h, 14h, 17h
level 3  - bootsplash, initializations, SeaBIOS VGA BIOS interrupts
level 4 - bios tables, more optionrom
level 5  - Extra bootsplash, more XHCI
level 6  - ATA commands, extra optionrom
level 7  - extra ps2 commands, more OHCI &amp; EHCI
level 8 - extra malloc info, more AHCI
level 9  - interrupts 15h, 16h, 1ah, APM, PCI, SMIs, PCIBIOS,
USB-HID commands, SDcard commands, Floppy commands
level 10 - interrupt 13h (Drives other than floppy)
level 20 - interrupt 10h (Display)
 
||
|- bgcolor="#eeeeee"
| || || (comment) || || Using default SeaBIOS log level ||
|- bgcolor="#eeeeee"
| || || (comment) || || SeaBIOS logging disabled ||
|- bgcolor="#6699dd"
! align="left" | Menu: PXE Options || || || ||
|- bgcolor="#eeeeee"
| PXE_ROM || payloads/external/iPXE || bool || Add an existing PXE ROM image ||
Select this option if you have a PXE ROM image that you would
like to add to your ROM.
 
||
|- bgcolor="#eeeeee"
| BUILD_IPXE || payloads/external/iPXE || bool || Build and add an iPXE ROM ||
Select this option to fetch and build a ROM from the iPXE project.
 
||
|- bgcolor="#eeeeee"
| IPXE_STABLE || payloads/external/iPXE || bool || 2017.3 ||
iPXE uses a rolling release with no stable version, for
reproducibility, use the last commit of a given month as the
'stable' version.
This is iPXE from the end of March, 2017.
 
||
|- bgcolor="#eeeeee"
| IPXE_MASTER || payloads/external/iPXE || bool || master ||
Newest iPXE version.
 
||
|- bgcolor="#eeeeee"
| PXE_ROM_FILE || payloads/external/iPXE || string || PXE ROM filename ||
The path and filename of the file to use as PXE ROM.
 
||
|- bgcolor="#eeeeee"
| PXE_ROM_ID || payloads/external/iPXE || string || network card PCI IDs ||
The comma-separated PCI vendor and device ID that would associate
your PXE ROM to your network card.
 
Example: 10ec,8168
 
In the above example 10ec is the PCI vendor ID (in hex, but without
the "0x" prefix) and 8168 specifies the PCI device ID of the
network card (also in hex, without "0x" prefix).
 
Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.
 
||
 
|- bgcolor="#eeeeee"
| FILO_STABLE || payloads/external/FILO || bool || 0.6.0 ||
Stable FILO version
 
||
|- bgcolor="#eeeeee"
| FILO_MASTER || payloads/external/FILO || bool || HEAD ||
Newest FILO version
 
||
|- bgcolor="#eeeeee"
| PAYLOAD_FILE || payloads/external/linux || string || Linux path and filename ||
The path and filename of the bzImage kernel to use as payload.
 
||
|- bgcolor="#eeeeee"
| LINUX_COMMAND_LINE || payloads/external/linux || string || Linux command line ||
A command line to add to the Linux kernel.
 
||
|- bgcolor="#eeeeee"
| LINUX_INITRD || payloads/external/linux || string || Linux initrd ||
An initrd image to add to the Linux kernel.
 
||
|- bgcolor="#eeeeee"
| PAYLOAD_FILE || payloads/external/tianocore || string || Tianocore binary ||
The result of a corebootPkg build
 
||
|- bgcolor="#eeeeee"
| PAYLOAD_FILE || payloads/external/tianocore || string || Tianocore version ||
Select which version of Tianocore to build (default is to build stable)
stable: a version of Tianocore that builds without any errors
master: most recent version from upstream Tianocore repository
revision: use specific commit or branch to build Tianocore (specified by user)
 
||
|- bgcolor="#eeeeee"
| TIANOCORE_STABLE || payloads/external/tianocore || bool || stable ||
Select this option to build the stable tianocore version
i.e. a version of Tianocore that builds without any errors
 
||
|- bgcolor="#eeeeee"
| TIANOCORE_MASTER || payloads/external/tianocore || bool || master ||
Select this option to build the master tianocore version
i.e. most recent version from upstream Tianocore repository
 
||
|- bgcolor="#eeeeee"
| TIANOCORE_REVISION || payloads/external/tianocore || bool || git revision ||
Select this option if you have a specific commit or branch
that you want to use as the revision from which to
build Tianocore.
 
You will be able to specify the name of a branch or a commit id
later.
 
||
|- bgcolor="#eeeeee"
| TIANOCORE_REVISION_ID || payloads/external/tianocore || string || Insert a commit's SHA-1 or a branch name ||
The commit's SHA-1 or branch name of the revision to use.
 
||
|- bgcolor="#eeeeee"
| TIANOCORE_REVISION_ID || payloads/external/tianocore || string || Target architecture ||
The Tianocore coreboot Payload Package binary can be
built for either only IA32 or both X64 and IA32 architectures.
Select which architecture(s) to build for; default is to build
for both X64 and IA32.
 
||
|- bgcolor="#eeeeee"
| TIANOCORE_TARGET_IA32 || payloads/external/tianocore || bool || IA32 ||
By selecting this option, the target architecture will be built
for only IA32.
 
||
|- bgcolor="#eeeeee"
| TIANOCORE_TARGET_X64 || payloads/external/tianocore || bool || X64 ||
By selecting this option, the target architecture will be built
for X64 and IA32.
 
||
|- bgcolor="#eeeeee"
| TIANOCORE_TARGET_X64 || payloads/external/tianocore || bool || Tianocore build ||
Select whether to generate a debug or release build for
Tianocore; default is to generate a release build.
 
||
|- bgcolor="#eeeeee"
| TIANOCORE_DEBUG || payloads/external/tianocore || bool || Generate Tianocore debug build ||
Generate a debug build.
 
||
|- bgcolor="#eeeeee"
| TIANOCORE_RELEASE || payloads/external/tianocore || bool || Generate Tianocore release build ||
Generate a release build.
 
||
|- bgcolor="#eeeeee"
| GRUB2_STABLE || payloads/external/GRUB2 || bool || 2.02 ||
Stable GRUB2 version
 
||
|- bgcolor="#eeeeee"
| GRUB2_MASTER || payloads/external/GRUB2 || bool || HEAD ||
Newest GRUB2 version
 
||
|- bgcolor="#eeeeee"
| GRUB2_REVISION || payloads/external/GRUB2 || bool || git revision ||
Select this option if you have a specific commit or branch
that you want to use as the revision from which to
build GRUB2.
 
You will be able to specify the name of a branch or a commit id
later.
||
|- bgcolor="#eeeeee"
| GRUB2_REVISION_ID || payloads/external/GRUB2 || string || Insert a commit's SHA-1 or a branch name ||
The commit's SHA-1 or branch name of the revision to use.
 
||
|- bgcolor="#eeeeee"
| GRUB2_EXTRA_MODULES || payloads/external/GRUB2 || string || Extra modules to include in GRUB image ||
Space-separated list of additional modules to include. Few common
ones:
* bsd for *BSD
* png/jpg for PNG/JPG images
* gfxmenu for graphical menus (you'll need a theme as well)
* gfxterm_background for setting background
 
||
|- bgcolor="#eeeeee"
| GRUB2_INCLUDE_RUNTIME_CONFIG_FILE || payloads/external/GRUB2 || bool || Include GRUB2 runtime config file into ROM image ||
The GRUB2 payload reads its runtime configuration file from etc/grub.cfg
stored in the CBFS on the flash ROM chip. Without that, it’ll just drop
into a rescue shell.
 
This configuration may need to be coreboot specific.
 
Select this option, if you want to include the GRUB2 runtime
configuration file into CBFS as `etc/grub.cfg` automatically.
 
You will be able to specify the path of the configuration file later.
 
Without this option you would need to add this file manually with
build/cbfstool build/coreboot.rom add -f grub.cfg -n etc/grub.cfg -t raw
 
||
|- bgcolor="#eeeeee"
| GRUB2_RUNTIME_CONFIG_FILE || payloads/external/GRUB2 || string || Path of grub.cfg ||
The path of the GRUB2 runtime configuration file to be added to CBFS.
 
||
|- bgcolor="#eeeeee"
| DEPTHCHARGE_STABLE || payloads/external/depthcharge || bool || stable ||
Latest stable version.
 
||
|- bgcolor="#eeeeee"
| DEPTHCHARGE_MASTER || payloads/external/depthcharge || bool || master ||
Newest Depthcharge version.
 
||
|- bgcolor="#eeeeee"
| DEPTHCHARGE_REVISION || payloads/external/depthcharge || bool || git revision ||
Select this option if you have a specific commit or branch that
you want to use as the revision from which to build Depthcharge.
 
You will be able to specify the name of a branch or a commit SHA
later.
 
||
|- bgcolor="#eeeeee"
| DEPTHCHARGE_REVISION_ID || payloads/external/depthcharge || string || Insert a commit's SHA-1 or a branch name ||
The commit's SHA-1 or branch name of the revision to use.
 
||
|- bgcolor="#eeeeee"
| LP_DEFCONFIG_OVERRIDE || payloads/external/depthcharge || bool || Use default libpayload config ||
The Depthcharge makefile looks for a file config.&lt;boardname&gt; in the
libpayload/configs directory.  Say Y here to use the file defconfig
instead.  This is can be a convenience for development purposes, or
if the defaults in defconfig are sufficient for your system.
 
||
|- bgcolor="#eeeeee"
| PAYLOAD_FILE || payloads || string || Payload path and filename ||
The path and filename of the ELF executable file to use as payload.
 
||
|- bgcolor="#eeeeee"
| PAYLOAD_FILE || payloads || string || Payload compression algorithm ||
Choose the compression algorithm for the chosen payloads.
You can choose between LZMA and LZ4.
 
||
|- bgcolor="#eeeeee"
| COMPRESSED_PAYLOAD_LZMA || payloads || bool || Use LZMA compression for payloads ||
In order to reduce the size payloads take up in the ROM chip
coreboot can compress them using the LZMA algorithm.
 
||
|- bgcolor="#eeeeee"
| COMPRESSED_PAYLOAD_LZ4 || payloads || bool || Use LZ4 compression for payloads ||
In order to reduce the size payloads take up in the ROM chip
coreboot can compress them using the LZ4 algorithm.
||
|- bgcolor="#eeeeee"
| PAYLOAD_OPTIONS || payloads || string ||  ||
Additional cbfstool options for the payload
 
||
|- bgcolor="#eeeeee"
| PAYLOAD_IS_FLAT_BINARY || payloads || string ||  ||
Add the payload to cbfs as a flat binary type instead of as an
elf payload
 
||
|- bgcolor="#eeeeee"
| COMPRESS_SECONDARY_PAYLOAD || payloads || bool || Use LZMA compression for secondary payloads ||
In order to reduce the size secondary payloads take up in the
ROM chip they can be compressed using the LZMA algorithm.
 
||
|- bgcolor="#6699dd"
! align="left" | Menu: Secondary Payloads || || || ||
|- bgcolor="#eeeeee"
| COREINFO_SECONDARY_PAYLOAD || payloads || bool || Load coreinfo as a secondary payload ||
coreinfo can be loaded as a secondary payload under SeaBIOS, GRUB,
or any other payload that can load additional payloads.
 
||
|- bgcolor="#eeeeee"
| MEMTEST_SECONDARY_PAYLOAD || payloads || bool || Load Memtest86+ as a secondary payload ||
Memtest86+ can be loaded as a secondary payload under SeaBIOS, GRUB,
or any other payload that can load additional payloads.
 
||
|- bgcolor="#eeeeee"
| MEMTEST_STABLE || payloads || bool || Stable ||
Stable Memtest86+ version.
 
For reproducible builds, this option must be selected.
||
|- bgcolor="#eeeeee"
| MEMTEST_MASTER || payloads || bool || Master ||
Newest Memtest86+ version.
 
This option will fetch the newest version of the Memtest86+ code,
updating as new changes are committed. This makes the build
non-reproducible, as it can fetch different code each time.
||
|- bgcolor="#eeeeee"
| NVRAMCUI_SECONDARY_PAYLOAD || payloads || bool || Load nvramcui as a secondary payload ||
nvramcui can be loaded as a secondary payload under SeaBIOS, GRUB,
or any other payload that can load additional payloads.
 
||
|- bgcolor="#eeeeee"
| TINT_SECONDARY_PAYLOAD || payloads || bool || Load tint as a secondary payload ||
tint can be loaded as a secondary payload under SeaBIOS, GRUB,
or any other payload that can load additional payloads.
 
||
 
 
|- bgcolor="#6699dd"
! align="left" | Menu: Debugging || || || ||
|- bgcolor="#eeeeee"
| GDB_STUB || toplevel || bool || GDB debugging support ||
If enabled, you will be able to set breakpoints for gdb debugging.
See src/arch/x86/lib/c_start.S for details.
 
||
|- bgcolor="#eeeeee"
| GDB_WAIT || toplevel || bool || Wait for a GDB connection in the ramstage ||
If enabled, coreboot will wait for a GDB connection in the ramstage.
 
 
||
|- bgcolor="#eeeeee"
| FATAL_ASSERTS || toplevel || bool || Halt when hitting a BUG() or assertion error ||
If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
 
||
|- bgcolor="#eeeeee"
| DEBUG_CBFS || toplevel || bool || Output verbose CBFS debug messages ||
This option enables additional CBFS related debug messages.
 
||
|- bgcolor="#eeeeee"
| DEBUG_RAM_SETUP || toplevel || bool || Output verbose RAM init debug messages ||
This option enables additional RAM init related debug messages.
It is recommended to enable this when debugging issues on your
board which might be RAM init related.
 
Note: This option will increase the size of the coreboot image.


<span id="lenovo/x201"></span>
If unsure, say N.
[[Board:lenovo/x201|lenovo/x201]] at Wed May 16 06:19:34 UTC 2018
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=d8ec973fd24e091d0038d7060bfb516bad7534f0 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x201/4.8-6-gd8ec973fd2/2018-05-16T06_19_34Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x201/4.8-6-gd8ec973fd2/2018-05-16T06_19_34Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x201/4.8-6-gd8ec973fd2/2018-05-16T06_19_34Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x201/4.8-6-gd8ec973fd2/2018-05-16T06_19_34Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x201/4.8-6-gd8ec973fd2/2018-05-16T06_19_34Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x201/4.8-6-gd8ec973fd2/2018-05-16T06_19_34Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x201/4.8-6-gd8ec973fd2/2018-05-16T06_19_34Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x201/4.8-6-gd8ec973fd2/2018-05-16T06_19_34Z/rom_checksum.txt rom_checksum.txt]
)


<span id="lenovo/x60"></span>
||
[[Board:lenovo/x60|lenovo/x60]] at Tue May 15 03:57:13 UTC 2018
|- bgcolor="#eeeeee"
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=1edd66c1ef5a44b71d7fbe4de567905788e94e79 upstream tree] (
| DEBUG_CAR || toplevel || bool || Output verbose Cache-as-RAM debug messages ||
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x60/4.7-1183-g1edd66c1ef/2018-05-15T03_57_13Z/cbfs.txt cbfs.txt]
This option enables additional CAR related debug messages.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x60/4.7-1183-g1edd66c1ef/2018-05-15T03_57_13Z/config.short.txt config.short.txt]
||
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x60/4.7-1183-g1edd66c1ef/2018-05-15T03_57_13Z/config.txt config.txt]
|- bgcolor="#eeeeee"
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x60/4.7-1183-g1edd66c1ef/2018-05-15T03_57_13Z/coreboot_console.txt coreboot_console.txt]
| DEBUG_PIRQ || toplevel || bool || Check PIRQ table consistency ||
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x60/4.7-1183-g1edd66c1ef/2018-05-15T03_57_13Z/coreboot_timestamps.txt coreboot_timestamps.txt]
If unsure, say N.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x60/4.7-1183-g1edd66c1ef/2018-05-15T03_57_13Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x60/4.7-1183-g1edd66c1ef/2018-05-15T03_57_13Z/rom_checksum.txt rom_checksum.txt]
)


= 2018W19 =
||
<span id="asrock/e350m1"></span>
|- bgcolor="#eeeeee"
[[Board:asrock/e350m1|asrock/e350m1]] at Fri May 11 00:57:05 UTC 2018
| DEBUG_SMBUS || toplevel || bool || Output verbose SMBus debug messages ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=d319b982797752231d0ea37c08490ba630312bb8 upstream tree] (
This option enables additional SMBus (and SPD) debug messages.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/e350m1/4.7-1125-g925b91a807/2018-05-11T00_57_05Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/e350m1/4.7-1125-g925b91a807/2018-05-11T00_57_05Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/e350m1/4.7-1125-g925b91a807/2018-05-11T00_57_05Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/e350m1/4.7-1125-g925b91a807/2018-05-11T00_57_05Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/e350m1/4.7-1125-g925b91a807/2018-05-11T00_57_05Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/e350m1/4.7-1125-g925b91a807/2018-05-11T00_57_05Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/e350m1/4.7-1125-g925b91a807/2018-05-11T00_57_05Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/e350m1/4.7-1125-g925b91a807/2018-05-11T00_57_05Z/rom_checksum.txt rom_checksum.txt]
)


<span id="lenovo/t400"></span>
Note: This option will increase the size of the coreboot image.
[[Board:lenovo/t400|lenovo/t400]] at Sun May  6 22:17:02 UTC 2018
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=c48b70f74401784e851adbf0ea519eda394b54ce upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t400/4.7-1039-gc48b70f744-dirty/2018-05-06T22_17_02Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t400/4.7-1039-gc48b70f744-dirty/2018-05-06T22_17_02Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t400/4.7-1039-gc48b70f744-dirty/2018-05-06T22_17_02Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t400/4.7-1039-gc48b70f744-dirty/2018-05-06T22_17_02Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t400/4.7-1039-gc48b70f744-dirty/2018-05-06T22_17_02Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t400/4.7-1039-gc48b70f744-dirty/2018-05-06T22_17_02Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t400/4.7-1039-gc48b70f744-dirty/2018-05-06T22_17_02Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t400/4.7-1039-gc48b70f744-dirty/2018-05-06T22_17_02Z/rom_checksum.txt rom_checksum.txt]
)


= 2018W18 =
If unsure, say N.
<span id="intel/d510mo"></span>
[[Board:intel/d510mo|intel/d510mo]] at Sun May  6 06:18:48 UTC 2018
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=c48b70f74401784e851adbf0ea519eda394b54ce upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/d510mo/4.7-1039-gc48b70f744/2018-05-06T06_18_48Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/d510mo/4.7-1039-gc48b70f744/2018-05-06T06_18_48Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/d510mo/4.7-1039-gc48b70f744/2018-05-06T06_18_48Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/d510mo/4.7-1039-gc48b70f744/2018-05-06T06_18_48Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/d510mo/4.7-1039-gc48b70f744/2018-05-06T06_18_48Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/d510mo/4.7-1039-gc48b70f744/2018-05-06T06_18_48Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/d510mo/4.7-1039-gc48b70f744/2018-05-06T06_18_48Z/rom_checksum.txt rom_checksum.txt]
)


<span id="gigabyte/ga-g41m-es2l"></span>
||
[[Board:gigabyte/ga-g41m-es2l|gigabyte/ga-g41m-es2l]] at Sun May  6 06:18:48 UTC 2018
|- bgcolor="#eeeeee"
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=c48b70f74401784e851adbf0ea519eda394b54ce upstream tree] (
| DEBUG_SMI || toplevel || bool || Output verbose SMI debug messages ||
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-g41m-es2l/4.7-1039-gc48b70f744/2018-05-06T06_18_48Z/cbfs.txt cbfs.txt]
This option enables additional SMI related debug messages.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-g41m-es2l/4.7-1039-gc48b70f744/2018-05-06T06_18_48Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-g41m-es2l/4.7-1039-gc48b70f744/2018-05-06T06_18_48Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-g41m-es2l/4.7-1039-gc48b70f744/2018-05-06T06_18_48Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-g41m-es2l/4.7-1039-gc48b70f744/2018-05-06T06_18_48Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-g41m-es2l/4.7-1039-gc48b70f744/2018-05-06T06_18_48Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-g41m-es2l/4.7-1039-gc48b70f744/2018-05-06T06_18_48Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-g41m-es2l/4.7-1039-gc48b70f744/2018-05-06T06_18_48Z/rom_checksum.txt rom_checksum.txt]
)


<span id="intel/camelbackmountain_fsp"></span>
Note: This option will increase the size of the coreboot image.
[[Board:intel/camelbackmountain_fsp|intel/camelbackmountain_fsp]] at Fri May  4 10:30:24 UTC 2018
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=4f5bed5210a82eb5f422b72514f9c123a2234876 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/camelbackmountain_fsp/4.7-1024-g4f5bed5210/2018-05-04T10_30_24Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/camelbackmountain_fsp/4.7-1024-g4f5bed5210/2018-05-04T10_30_24Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/camelbackmountain_fsp/4.7-1024-g4f5bed5210/2018-05-04T10_30_24Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/camelbackmountain_fsp/4.7-1024-g4f5bed5210/2018-05-04T10_30_24Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/camelbackmountain_fsp/4.7-1024-g4f5bed5210/2018-05-04T10_30_24Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/camelbackmountain_fsp/4.7-1024-g4f5bed5210/2018-05-04T10_30_24Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/camelbackmountain_fsp/4.7-1024-g4f5bed5210/2018-05-04T10_30_24Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/camelbackmountain_fsp/4.7-1024-g4f5bed5210/2018-05-04T10_30_24Z/rom_checksum.txt rom_checksum.txt]
)


<span id="asus/kgpe-d16"></span>
If unsure, say N.
[[Board:asus/kgpe-d16|asus/kgpe-d16]] at Thu May  3 17:31:02 UTC 2018
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=e93634caa0ac8bd9286cf0eeb36ea960d738de2e upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kgpe-d16/4.7-988-ge1221c06e0/2018-05-03T17_31_02Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kgpe-d16/4.7-988-ge1221c06e0/2018-05-03T17_31_02Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kgpe-d16/4.7-988-ge1221c06e0/2018-05-03T17_31_02Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kgpe-d16/4.7-988-ge1221c06e0/2018-05-03T17_31_02Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kgpe-d16/4.7-988-ge1221c06e0/2018-05-03T17_31_02Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kgpe-d16/4.7-988-ge1221c06e0/2018-05-03T17_31_02Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kgpe-d16/4.7-988-ge1221c06e0/2018-05-03T17_31_02Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kgpe-d16/4.7-988-ge1221c06e0/2018-05-03T17_31_02Z/rom_checksum.txt rom_checksum.txt]
)


<span id="asus/am1i-a"></span>
||
[[Board:asus/am1i-a|asus/am1i-a]] at Thu May  3 17:31:02 UTC 2018
|- bgcolor="#eeeeee"
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=e93634caa0ac8bd9286cf0eeb36ea960d738de2e upstream tree] (
| DEBUG_SMM_RELOCATION || toplevel || bool || Debug SMM relocation code ||
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/am1i-a/4.7-988-ge1221c06e0/2018-05-03T17_31_02Z/cbfs.txt cbfs.txt]
This option enables additional SMM handler relocation related
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/am1i-a/4.7-988-ge1221c06e0/2018-05-03T17_31_02Z/config.short.txt config.short.txt]
debug messages.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/am1i-a/4.7-988-ge1221c06e0/2018-05-03T17_31_02Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/am1i-a/4.7-988-ge1221c06e0/2018-05-03T17_31_02Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/am1i-a/4.7-988-ge1221c06e0/2018-05-03T17_31_02Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/am1i-a/4.7-988-ge1221c06e0/2018-05-03T17_31_02Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/am1i-a/4.7-988-ge1221c06e0/2018-05-03T17_31_02Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/am1i-a/4.7-988-ge1221c06e0/2018-05-03T17_31_02Z/rom_checksum.txt rom_checksum.txt]
)


= 2018W17 =
Note: This option will increase the size of the coreboot image.
<span id="pcengines/apu1"></span>
[[Board:pcengines/apu1|pcengines/apu1]] at Sun Apr 29 18:26:46 UTC 2018
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=621abec1e842acd69d122b2b451b35b14d3c5049 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/apu1/4.7-919-g621abec1e8/2018-04-29T18_26_46Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/apu1/4.7-919-g621abec1e8/2018-04-29T18_26_46Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/apu1/4.7-919-g621abec1e8/2018-04-29T18_26_46Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/apu1/4.7-919-g621abec1e8/2018-04-29T18_26_46Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/apu1/4.7-919-g621abec1e8/2018-04-29T18_26_46Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/apu1/4.7-919-g621abec1e8/2018-04-29T18_26_46Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/apu1/4.7-919-g621abec1e8/2018-04-29T18_26_46Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/apu1/4.7-919-g621abec1e8/2018-04-29T18_26_46Z/rom_checksum.txt rom_checksum.txt]
)


= 2018W16 =
If unsure, say N.
<span id="asus/kcma-d8"></span>
[[Board:asus/kcma-d8|asus/kcma-d8]] at Thu Apr 19 15:05:08 UTC 2018
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=51895d183861234db9500bd1ee33634776e91e93 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kcma-d8/4.7-789-g51895d1838/2018-04-19T15_05_08Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kcma-d8/4.7-789-g51895d1838/2018-04-19T15_05_08Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kcma-d8/4.7-789-g51895d1838/2018-04-19T15_05_08Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kcma-d8/4.7-789-g51895d1838/2018-04-19T15_05_08Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kcma-d8/4.7-789-g51895d1838/2018-04-19T15_05_08Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kcma-d8/4.7-789-g51895d1838/2018-04-19T15_05_08Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kcma-d8/4.7-789-g51895d1838/2018-04-19T15_05_08Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kcma-d8/4.7-789-g51895d1838/2018-04-19T15_05_08Z/rom_checksum.txt rom_checksum.txt]
)


= 2018W15 =
||
<span id="msi/ms7721"></span>
|- bgcolor="#eeeeee"
[[Board:msi/ms7721|msi/ms7721]] at Mon Apr  9 12:06:51 UTC 2018
| DEBUG_MALLOC || toplevel || bool || Output verbose malloc debug messages ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=5e32f41b438d92d47d777cb8df70c02ea45e8f70 upstream tree] (
This option enables additional malloc related debug messages.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/msi/ms7721/4.7-673-g5e32f41b43/2018-04-09T12_06_51Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/msi/ms7721/4.7-673-g5e32f41b43/2018-04-09T12_06_51Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/msi/ms7721/4.7-673-g5e32f41b43/2018-04-09T12_06_51Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/msi/ms7721/4.7-673-g5e32f41b43/2018-04-09T12_06_51Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/msi/ms7721/4.7-673-g5e32f41b43/2018-04-09T12_06_51Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/msi/ms7721/4.7-673-g5e32f41b43/2018-04-09T12_06_51Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/msi/ms7721/4.7-673-g5e32f41b43/2018-04-09T12_06_51Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/msi/ms7721/4.7-673-g5e32f41b43/2018-04-09T12_06_51Z/rom_checksum.txt rom_checksum.txt]
)


<span id="lenovo/g505s"></span>
Note: This option will increase the size of the coreboot image.
[[Board:lenovo/g505s|lenovo/g505s]] at Mon Apr  9 01:03:12 UTC 2018
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=b90c0d90cff03e5f7cbf2c3413f8766983589762 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/g505s/4.7-662-gb90c0d90cf/2018-04-09T01_03_12Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/g505s/4.7-662-gb90c0d90cf/2018-04-09T01_03_12Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/g505s/4.7-662-gb90c0d90cf/2018-04-09T01_03_12Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/g505s/4.7-662-gb90c0d90cf/2018-04-09T01_03_12Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/g505s/4.7-662-gb90c0d90cf/2018-04-09T01_03_12Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/g505s/4.7-662-gb90c0d90cf/2018-04-09T01_03_12Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/g505s/4.7-662-gb90c0d90cf/2018-04-09T01_03_12Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/g505s/4.7-662-gb90c0d90cf/2018-04-09T01_03_12Z/rom_checksum.txt rom_checksum.txt]
)


= 2018W14 =
If unsure, say N.
<span id="asus/maximus_iv_gene-z"></span>
[[Board:asus/maximus_iv_gene-z|asus/maximus_iv_gene-z]] at Fri Apr  6 10:29:01 UTC 2018
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=b90c0d90cff03e5f7cbf2c3413f8766983589762 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/maximus_iv_gene-z/4.7-662-gb90c0d90cf/2018-04-06T10_29_01Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/maximus_iv_gene-z/4.7-662-gb90c0d90cf/2018-04-06T10_29_01Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/maximus_iv_gene-z/4.7-662-gb90c0d90cf/2018-04-06T10_29_01Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/maximus_iv_gene-z/4.7-662-gb90c0d90cf/2018-04-06T10_29_01Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/maximus_iv_gene-z/4.7-662-gb90c0d90cf/2018-04-06T10_29_01Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/maximus_iv_gene-z/4.7-662-gb90c0d90cf/2018-04-06T10_29_01Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/maximus_iv_gene-z/4.7-662-gb90c0d90cf/2018-04-06T10_29_01Z/rom_checksum.txt rom_checksum.txt]
)


<span id="lenovo/t430"></span>
||
[[Board:lenovo/t430|lenovo/t430]] at Tue Apr  3 21:38:40 UTC 2018
|- bgcolor="#eeeeee"
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=03c7b05a5a1838da1e792cb127a549358c5193d4 upstream tree] (
| DEBUG_ACPI || toplevel || bool || Output verbose ACPI debug messages ||
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t430/4.7-624-g03c7b05a5a-dirty/2018-04-03T21_38_40Z/cbfs.txt cbfs.txt]
This option enables additional ACPI related debug messages.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t430/4.7-624-g03c7b05a5a-dirty/2018-04-03T21_38_40Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t430/4.7-624-g03c7b05a5a-dirty/2018-04-03T21_38_40Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t430/4.7-624-g03c7b05a5a-dirty/2018-04-03T21_38_40Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t430/4.7-624-g03c7b05a5a-dirty/2018-04-03T21_38_40Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t430/4.7-624-g03c7b05a5a-dirty/2018-04-03T21_38_40Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t430/4.7-624-g03c7b05a5a-dirty/2018-04-03T21_38_40Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t430/4.7-624-g03c7b05a5a-dirty/2018-04-03T21_38_40Z/rom_checksum.txt rom_checksum.txt]
)


= 2018W13 =
Note: This option will slightly increase the size of the coreboot image.
<span id="hp/folio_9470m"></span>
[[Board:hp/folio_9470m|hp/folio_9470m]] at Mon Mar 26 10:25:58 UTC 2018
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=be78775a9302f9526df6eb61f8a430f4298f0e97 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/folio_9470m/4.7-589-gbe78775a93/2018-03-26T10_25_58Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/folio_9470m/4.7-589-gbe78775a93/2018-03-26T10_25_58Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/folio_9470m/4.7-589-gbe78775a93/2018-03-26T10_25_58Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/folio_9470m/4.7-589-gbe78775a93/2018-03-26T10_25_58Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/folio_9470m/4.7-589-gbe78775a93/2018-03-26T10_25_58Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/folio_9470m/4.7-589-gbe78775a93/2018-03-26T10_25_58Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/folio_9470m/4.7-589-gbe78775a93/2018-03-26T10_25_58Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/folio_9470m/4.7-589-gbe78775a93/2018-03-26T10_25_58Z/rom_checksum.txt rom_checksum.txt]
)


= 2018W09 =
If unsure, say N.
<span id="msi/ms7135"></span>
[[Board:msi/ms7135|msi/ms7135]] at Fri Mar  2 15:21:54 UTC 2018
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=8b84f437b197caf07f710ce9abbc6f445c05e739 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/msi/ms7135/4.7-440-g277f4b9974/2018-03-02T15_21_54Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/msi/ms7135/4.7-440-g277f4b9974/2018-03-02T15_21_54Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/msi/ms7135/4.7-440-g277f4b9974/2018-03-02T15_21_54Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/msi/ms7135/4.7-440-g277f4b9974/2018-03-02T15_21_54Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/msi/ms7135/4.7-440-g277f4b9974/2018-03-02T15_21_54Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/msi/ms7135/4.7-440-g277f4b9974/2018-03-02T15_21_54Z/rom_checksum.txt rom_checksum.txt]
)


= 2018W07 =
||
<span id="asus/kfsn4-dre"></span>
|- bgcolor="#eeeeee"
[[Board:asus/kfsn4-dre|asus/kfsn4-dre]] at Thu Feb 15 18:30:23 UTC 2018
| REALMODE_DEBUG || toplevel || bool || Enable debug messages for option ROM execution ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=af15268c103642f32461d939cc4a9b836ad8db94 upstream tree] (
This option enables additional x86emu related debug messages.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kfsn4-dre/4.7-329-gaf15268/2018-02-15T18_30_23Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kfsn4-dre/4.7-329-gaf15268/2018-02-15T18_30_23Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kfsn4-dre/4.7-329-gaf15268/2018-02-15T18_30_23Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kfsn4-dre/4.7-329-gaf15268/2018-02-15T18_30_23Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kfsn4-dre/4.7-329-gaf15268/2018-02-15T18_30_23Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kfsn4-dre/4.7-329-gaf15268/2018-02-15T18_30_23Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kfsn4-dre/4.7-329-gaf15268/2018-02-15T18_30_23Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kfsn4-dre/4.7-329-gaf15268/2018-02-15T18_30_23Z/rom_checksum.txt rom_checksum.txt]
)


= 2018W06 =
Note: This option will increase the time to emulate a ROM.
<span id="lenovo/x220"></span>
[[Board:lenovo/x220|lenovo/x220]] at Tue Feb  6 15:30:49 UTC 2018
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=f9d9781292aab5ea6c4a5058aca895b575e279a7 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x220/4.7-263-gf9d9781292/2018-02-06T15_30_49Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x220/4.7-263-gf9d9781292/2018-02-06T15_30_49Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x220/4.7-263-gf9d9781292/2018-02-06T15_30_49Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x220/4.7-263-gf9d9781292/2018-02-06T15_30_49Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x220/4.7-263-gf9d9781292/2018-02-06T15_30_49Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x220/4.7-263-gf9d9781292/2018-02-06T15_30_49Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x220/4.7-263-gf9d9781292/2018-02-06T15_30_49Z/rom_checksum.txt rom_checksum.txt]
)


<span id="emulation/qemu-q35"></span>
If unsure, say N.
[[Board:emulation/qemu-q35|emulation/qemu-q35]] at Tue Feb  6 06:14:30 UTC 2018
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=da6f4ae0b98313aae9e6295e412d87b11199501f upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/emulation/qemu-q35/4.7-251-gda6f4ae/2018-02-06T06_14_30Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/emulation/qemu-q35/4.7-251-gda6f4ae/2018-02-06T06_14_30Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/emulation/qemu-q35/4.7-251-gda6f4ae/2018-02-06T06_14_30Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/emulation/qemu-q35/4.7-251-gda6f4ae/2018-02-06T06_14_30Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/emulation/qemu-q35/4.7-251-gda6f4ae/2018-02-06T06_14_30Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/emulation/qemu-q35/4.7-251-gda6f4ae/2018-02-06T06_14_30Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/emulation/qemu-q35/4.7-251-gda6f4ae/2018-02-06T06_14_30Z/rom_checksum.txt rom_checksum.txt]
)


= 2018W05 =
||
<span id="hp/2570p"></span>
|- bgcolor="#eeeeee"
[[Board:hp/2570p|hp/2570p]] at Mon Jan 29 09:41:35 UTC 2018
| X86EMU_DEBUG || toplevel || bool || Output verbose x86emu debug messages ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=0f68b23aafc102926ccc833b228d098f5613f3e8 upstream tree] (
This option enables additional x86emu related debug messages.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/2570p/4.7-163-g0f68b23aaf/2018-01-29T09_41_35Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/2570p/4.7-163-g0f68b23aaf/2018-01-29T09_41_35Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/2570p/4.7-163-g0f68b23aaf/2018-01-29T09_41_35Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/2570p/4.7-163-g0f68b23aaf/2018-01-29T09_41_35Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/2570p/4.7-163-g0f68b23aaf/2018-01-29T09_41_35Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/2570p/4.7-163-g0f68b23aaf/2018-01-29T09_41_35Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/2570p/4.7-163-g0f68b23aaf/2018-01-29T09_41_35Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/2570p/4.7-163-g0f68b23aaf/2018-01-29T09_41_35Z/rom_checksum.txt rom_checksum.txt]
)


= 2018W03 =
Note: This option will increase the size of the coreboot image.
<span id="pcengines/apu2"></span>
[[Board:pcengines/apu2|pcengines/apu2]] at Mon Jan 15 00:44:43 UTC 2018
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=29c657f4c6c24899579dfda4de0ca553fde08c51 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/apu2/4.7/2018-01-15T00_44_43Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/apu2/4.7/2018-01-15T00_44_43Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/apu2/4.7/2018-01-15T00_44_43Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/apu2/4.7/2018-01-15T00_44_43Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/apu2/4.7/2018-01-15T00_44_43Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/apu2/4.7/2018-01-15T00_44_43Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/apu2/4.7/2018-01-15T00_44_43Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/apu2/4.7/2018-01-15T00_44_43Z/rom_checksum.txt rom_checksum.txt]
)


<span id="pcengines/alix2d"></span>
If unsure, say N.
[[Board:pcengines/alix2d|pcengines/alix2d]] at Mon Jan 15 00:44:43 UTC 2018
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=8735d1bdc7ff76ee643472012af026e92d82477a upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/alix2d/4.7/2018-01-15T00_44_43Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/alix2d/4.7/2018-01-15T00_44_43Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/alix2d/4.7/2018-01-15T00_44_43Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/alix2d/4.7/2018-01-15T00_44_43Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/alix2d/4.7/2018-01-15T00_44_43Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/alix2d/4.7/2018-01-15T00_44_43Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/alix2d/4.7/2018-01-15T00_44_43Z/rom_checksum.txt rom_checksum.txt]
)


<span id="pcengines/alix1c"></span>
||
[[Board:pcengines/alix1c|pcengines/alix1c]] at Mon Jan 15 00:44:43 UTC 2018
|- bgcolor="#eeeeee"
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=8735d1bdc7ff76ee643472012af026e92d82477a upstream tree] (
| X86EMU_DEBUG_JMP || toplevel || bool || Trace JMP/RETF ||  
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/alix1c/4.7/2018-01-15T00_44_43Z/cbfs.txt cbfs.txt]
Print information about JMP and RETF opcodes from x86emu.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/alix1c/4.7/2018-01-15T00_44_43Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/alix1c/4.7/2018-01-15T00_44_43Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/alix1c/4.7/2018-01-15T00_44_43Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/alix1c/4.7/2018-01-15T00_44_43Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/alix1c/4.7/2018-01-15T00_44_43Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/pcengines/alix1c/4.7/2018-01-15T00_44_43Z/rom_checksum.txt rom_checksum.txt]
)


= 2018W02 =
Note: This option will increase the size of the coreboot image.
<span id="hp/revolve_810_g1"></span>
[[Board:hp/revolve_810_g1|hp/revolve_810_g1]] at Sat Jan 13 04:50:11 UTC 2018
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=1291c44abd4d7dfa23789653895e0940f0af86ab upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/revolve_810_g1/4.6-2553-g1291c44abd-dirty/2018-01-13T04_50_11Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/revolve_810_g1/4.6-2553-g1291c44abd-dirty/2018-01-13T04_50_11Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/revolve_810_g1/4.6-2553-g1291c44abd-dirty/2018-01-13T04_50_11Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/revolve_810_g1/4.6-2553-g1291c44abd-dirty/2018-01-13T04_50_11Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/revolve_810_g1/4.6-2553-g1291c44abd-dirty/2018-01-13T04_50_11Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/revolve_810_g1/4.6-2553-g1291c44abd-dirty/2018-01-13T04_50_11Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/revolve_810_g1/4.6-2553-g1291c44abd-dirty/2018-01-13T04_50_11Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/revolve_810_g1/4.6-2553-g1291c44abd-dirty/2018-01-13T04_50_11Z/rom_checksum.txt rom_checksum.txt]
)


<span id="lenovo/t60"></span>
If unsure, say N.
[[Board:lenovo/t60|lenovo/t60]] at Mon Jan  8 19:44:33 UTC 2018
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=e9be44e6d897602c1a714c7f7f25be1686b175b4 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t60/4.6-2510-ge9be44e6d8/2018-01-08T19_44_33Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t60/4.6-2510-ge9be44e6d8/2018-01-08T19_44_33Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t60/4.6-2510-ge9be44e6d8/2018-01-08T19_44_33Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t60/4.6-2510-ge9be44e6d8/2018-01-08T19_44_33Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t60/4.6-2510-ge9be44e6d8/2018-01-08T19_44_33Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t60/4.6-2510-ge9be44e6d8/2018-01-08T19_44_33Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t60/4.6-2510-ge9be44e6d8/2018-01-08T19_44_33Z/rom_checksum.txt rom_checksum.txt]
)


= 2017W50 =
||
<span id="asus/p2b"></span>
|- bgcolor="#eeeeee"
[[Board:asus/p2b|asus/p2b]] at Fri Dec 15 03:32:04 UTC 2017
| X86EMU_DEBUG_TRACE || toplevel || bool || Trace all opcodes ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=0cc28d7e61fc90be6bc0f5c1ba2cf4c535627527 upstream tree] (
Print _all_ opcodes that are executed by x86emu.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p2b/4.6-2379-g0cc28d7e61/2017-12-15T03_32_04Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p2b/4.6-2379-g0cc28d7e61/2017-12-15T03_32_04Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p2b/4.6-2379-g0cc28d7e61/2017-12-15T03_32_04Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p2b/4.6-2379-g0cc28d7e61/2017-12-15T03_32_04Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p2b/4.6-2379-g0cc28d7e61/2017-12-15T03_32_04Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p2b/4.6-2379-g0cc28d7e61/2017-12-15T03_32_04Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p2b/4.6-2379-g0cc28d7e61/2017-12-15T03_32_04Z/rom_checksum.txt rom_checksum.txt]
)


<span id="foxconn/g41s-k"></span>
WARNING: This will produce a LOT of output and take a long time.
[[Board:foxconn/g41s-k|foxconn/g41s-k]] at Mon Dec 11 07:06:21 UTC 2017
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=f6bbc603fadf4fdb6c9c86775739ff1b32ab5f1e upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/foxconn/g41s-k/4.6-2343-g641900fe88/2017-12-11T07_06_21Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/foxconn/g41s-k/4.6-2343-g641900fe88/2017-12-11T07_06_21Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/foxconn/g41s-k/4.6-2343-g641900fe88/2017-12-11T07_06_21Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/foxconn/g41s-k/4.6-2343-g641900fe88/2017-12-11T07_06_21Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/foxconn/g41s-k/4.6-2343-g641900fe88/2017-12-11T07_06_21Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/foxconn/g41s-k/4.6-2343-g641900fe88/2017-12-11T07_06_21Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/foxconn/g41s-k/4.6-2343-g641900fe88/2017-12-11T07_06_21Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/foxconn/g41s-k/4.6-2343-g641900fe88/2017-12-11T07_06_21Z/rom_checksum.txt rom_checksum.txt]
)


= 2017W49 =
Note: This option will increase the size of the coreboot image.
<span id="asus/m2v-mx_se"></span>
[[Board:asus/m2v-mx_se|asus/m2v-mx_se]] at Sat Dec  9 03:28:27 UTC 2017
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=950252675ab4148621b6be092a4240f2d96ffba0 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/m2v-mx_se/4.6-2321-g950252675a/2017-12-09T03_28_27Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/m2v-mx_se/4.6-2321-g950252675a/2017-12-09T03_28_27Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/m2v-mx_se/4.6-2321-g950252675a/2017-12-09T03_28_27Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/m2v-mx_se/4.6-2321-g950252675a/2017-12-09T03_28_27Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/m2v-mx_se/4.6-2321-g950252675a/2017-12-09T03_28_27Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/m2v-mx_se/4.6-2321-g950252675a/2017-12-09T03_28_27Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/m2v-mx_se/4.6-2321-g950252675a/2017-12-09T03_28_27Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/m2v-mx_se/4.6-2321-g950252675a/2017-12-09T03_28_27Z/rom_checksum.txt rom_checksum.txt]
)


<span id="lenovo/x200"></span>
If unsure, say N.
[[Board:lenovo/x200|lenovo/x200]] at Tue Dec  5 19:47:14 UTC 2017
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=2bd52ff0bd0c3837db7a3b5d26539d1b90036f2f upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x200/4.6-2254-g2bd52ff0bd/2017-12-05T19_47_14Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x200/4.6-2254-g2bd52ff0bd/2017-12-05T19_47_14Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x200/4.6-2254-g2bd52ff0bd/2017-12-05T19_47_14Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x200/4.6-2254-g2bd52ff0bd/2017-12-05T19_47_14Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x200/4.6-2254-g2bd52ff0bd/2017-12-05T19_47_14Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x200/4.6-2254-g2bd52ff0bd/2017-12-05T19_47_14Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x200/4.6-2254-g2bd52ff0bd/2017-12-05T19_47_14Z/rom_checksum.txt rom_checksum.txt]
)


<span id="lenovo/x1_carbon_gen1"></span>
||
[[Board:lenovo/x1_carbon_gen1|lenovo/x1_carbon_gen1]] at Tue Dec  5 00:29:49 UTC 2017
|- bgcolor="#eeeeee"
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=e90e2e5e66e1b7b1efbf88ea14a0b9d7d107321b upstream tree] (
| X86EMU_DEBUG_PNP || toplevel || bool || Log Plug&amp;Play accesses ||
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x1_carbon_gen1/4.6-2241-ge90e2e5e66-dirty/2017-12-05T00_29_49Z/cbfs.txt cbfs.txt]
Print Plug And Play accesses made by option ROMs.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x1_carbon_gen1/4.6-2241-ge90e2e5e66-dirty/2017-12-05T00_29_49Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x1_carbon_gen1/4.6-2241-ge90e2e5e66-dirty/2017-12-05T00_29_49Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x1_carbon_gen1/4.6-2241-ge90e2e5e66-dirty/2017-12-05T00_29_49Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x1_carbon_gen1/4.6-2241-ge90e2e5e66-dirty/2017-12-05T00_29_49Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x1_carbon_gen1/4.6-2241-ge90e2e5e66-dirty/2017-12-05T00_29_49Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x1_carbon_gen1/4.6-2241-ge90e2e5e66-dirty/2017-12-05T00_29_49Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/x1_carbon_gen1/4.6-2241-ge90e2e5e66-dirty/2017-12-05T00_29_49Z/rom_checksum.txt rom_checksum.txt]
)


= 2017W47 =
Note: This option will increase the size of the coreboot image.
<span id="lenovo/t430s"></span>
[[Board:lenovo/t430s|lenovo/t430s]] at Tue Nov 21 01:38:42 UTC 2017
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=ece69f212375c6895e70e86fb3fd8d4c45f51cbf upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t430s/4.6-2153-gece69f2123/2017-11-21T01_38_42Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t430s/4.6-2153-gece69f2123/2017-11-21T01_38_42Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t430s/4.6-2153-gece69f2123/2017-11-21T01_38_42Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t430s/4.6-2153-gece69f2123/2017-11-21T01_38_42Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t430s/4.6-2153-gece69f2123/2017-11-21T01_38_42Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t430s/4.6-2153-gece69f2123/2017-11-21T01_38_42Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t430s/4.6-2153-gece69f2123/2017-11-21T01_38_42Z/rom_checksum.txt rom_checksum.txt]
)


= 2017W46 =
If unsure, say N.
<span id="gigabyte/ga-b75m-d3v"></span>
[[Board:gigabyte/ga-b75m-d3v|gigabyte/ga-b75m-d3v]] at Sun Nov 19 01:50:13 UTC 2017
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=da6b1bc9e26df88e1c7b841f72307dd4997e09a5 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-b75m-d3v/4.6-2144-gda6b1bc9e2/2017-11-19T01_50_13Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-b75m-d3v/4.6-2144-gda6b1bc9e2/2017-11-19T01_50_13Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-b75m-d3v/4.6-2144-gda6b1bc9e2/2017-11-19T01_50_13Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-b75m-d3v/4.6-2144-gda6b1bc9e2/2017-11-19T01_50_13Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-b75m-d3v/4.6-2144-gda6b1bc9e2/2017-11-19T01_50_13Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-b75m-d3v/4.6-2144-gda6b1bc9e2/2017-11-19T01_50_13Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-b75m-d3v/4.6-2144-gda6b1bc9e2/2017-11-19T01_50_13Z/rom_checksum.txt rom_checksum.txt]
)


<span id="gigabyte/ga-b75m-d3h"></span>
||
[[Board:gigabyte/ga-b75m-d3h|gigabyte/ga-b75m-d3h]] at Sun Nov 19 01:50:13 UTC 2017
|- bgcolor="#eeeeee"
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=da6b1bc9e26df88e1c7b841f72307dd4997e09a5 upstream tree] (
| X86EMU_DEBUG_DISK || toplevel || bool || Log Disk I/O ||  
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-b75m-d3h/4.6-2144-gda6b1bc9e2/2017-11-19T01_50_13Z/cbfs.txt cbfs.txt]
Print Disk I/O related messages.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-b75m-d3h/4.6-2144-gda6b1bc9e2/2017-11-19T01_50_13Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-b75m-d3h/4.6-2144-gda6b1bc9e2/2017-11-19T01_50_13Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-b75m-d3h/4.6-2144-gda6b1bc9e2/2017-11-19T01_50_13Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-b75m-d3h/4.6-2144-gda6b1bc9e2/2017-11-19T01_50_13Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-b75m-d3h/4.6-2144-gda6b1bc9e2/2017-11-19T01_50_13Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-b75m-d3h/4.6-2144-gda6b1bc9e2/2017-11-19T01_50_13Z/rom_checksum.txt rom_checksum.txt]
)


<span id="asrock/939a785gmh"></span>
Note: This option will increase the size of the coreboot image.
[[Board:asrock/939a785gmh|asrock/939a785gmh]] at Sun Nov 19 01:50:13 UTC 2017
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=da6b1bc9e26df88e1c7b841f72307dd4997e09a5 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/939a785gmh/4.6-2144-gda6b1bc9e2/2017-11-19T01_50_13Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/939a785gmh/4.6-2144-gda6b1bc9e2/2017-11-19T01_50_13Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/939a785gmh/4.6-2144-gda6b1bc9e2/2017-11-19T01_50_13Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/939a785gmh/4.6-2144-gda6b1bc9e2/2017-11-19T01_50_13Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/939a785gmh/4.6-2144-gda6b1bc9e2/2017-11-19T01_50_13Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/939a785gmh/4.6-2144-gda6b1bc9e2/2017-11-19T01_50_13Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/939a785gmh/4.6-2144-gda6b1bc9e2/2017-11-19T01_50_13Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/939a785gmh/4.6-2144-gda6b1bc9e2/2017-11-19T01_50_13Z/rom_checksum.txt rom_checksum.txt]
)


<span id="hp/8460p"></span>
If unsure, say N.
[[Board:hp/8460p|hp/8460p]] at Sat Nov 18 12:59:33 UTC 2017
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=b045d4cd7bc9337e34cf29dd1e57c3f6647c7ca7 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/8460p/4.6-1287-g3d9de62bc7-dirty/2017-11-18T12_59_33Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/8460p/4.6-1287-g3d9de62bc7-dirty/2017-11-18T12_59_33Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/8460p/4.6-1287-g3d9de62bc7-dirty/2017-11-18T12_59_33Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/8460p/4.6-1287-g3d9de62bc7-dirty/2017-11-18T12_59_33Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/8460p/4.6-1287-g3d9de62bc7-dirty/2017-11-18T12_59_33Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/8460p/4.6-1287-g3d9de62bc7-dirty/2017-11-18T12_59_33Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/8460p/4.6-1287-g3d9de62bc7-dirty/2017-11-18T12_59_33Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/8460p/4.6-1287-g3d9de62bc7-dirty/2017-11-18T12_59_33Z/rom_checksum.txt rom_checksum.txt]
)


= 2017W41 =
||
<span id="asrock/b75pro3-m"></span>
|- bgcolor="#eeeeee"
[[Board:asrock/b75pro3-m|asrock/b75pro3-m]] at Thu Oct 12 02:45:41 UTC 2017
| X86EMU_DEBUG_PMM || toplevel || bool || Log PMM ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=f73bc0b2d103705a557142461d19496b59adda81 upstream tree] (
Print messages related to POST Memory Manager (PMM).
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/b75pro3-m/4.6-1730-gf73bc0b/2017-10-12T02_45_41Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/b75pro3-m/4.6-1730-gf73bc0b/2017-10-12T02_45_41Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/b75pro3-m/4.6-1730-gf73bc0b/2017-10-12T02_45_41Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/b75pro3-m/4.6-1730-gf73bc0b/2017-10-12T02_45_41Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/b75pro3-m/4.6-1730-gf73bc0b/2017-10-12T02_45_41Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/b75pro3-m/4.6-1730-gf73bc0b/2017-10-12T02_45_41Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/b75pro3-m/4.6-1730-gf73bc0b/2017-10-12T02_45_41Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/b75pro3-m/4.6-1730-gf73bc0b/2017-10-12T02_45_41Z/rom_checksum.txt rom_checksum.txt]
)


<span id="getac/p470"></span>
Note: This option will increase the size of the coreboot image.
[[Board:getac/p470|getac/p470]] at Mon Oct  9 20:20:40 UTC 2017
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=219ebb969bb52eb88d49d6ce31dbfc0d7cabfc49 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/getac/p470/4.6-1720-g219ebb969b/2017-10-09T20_20_40Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/getac/p470/4.6-1720-g219ebb969b/2017-10-09T20_20_40Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/getac/p470/4.6-1720-g219ebb969b/2017-10-09T20_20_40Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/getac/p470/4.6-1720-g219ebb969b/2017-10-09T20_20_40Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/getac/p470/4.6-1720-g219ebb969b/2017-10-09T20_20_40Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/getac/p470/4.6-1720-g219ebb969b/2017-10-09T20_20_40Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/getac/p470/4.6-1720-g219ebb969b/2017-10-09T20_20_40Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/getac/p470/4.6-1720-g219ebb969b/2017-10-09T20_20_40Z/rom_checksum.txt rom_checksum.txt]
)


<span id="lenovo/s230u"></span>
If unsure, say N.
[[Board:lenovo/s230u|lenovo/s230u]] at Mon Oct  9 07:10:54 UTC 2017
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=22579596ffa77889062d7655a366682cfeae84f7 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/s230u/4.6-1718-g22579596ff/2017-10-09T07_10_54Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/s230u/4.6-1718-g22579596ff/2017-10-09T07_10_54Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/s230u/4.6-1718-g22579596ff/2017-10-09T07_10_54Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/s230u/4.6-1718-g22579596ff/2017-10-09T07_10_54Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/s230u/4.6-1718-g22579596ff/2017-10-09T07_10_54Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/s230u/4.6-1718-g22579596ff/2017-10-09T07_10_54Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/s230u/4.6-1718-g22579596ff/2017-10-09T07_10_54Z/rom_checksum.txt rom_checksum.txt]
)


= 2017W40 =
<span id="winnet/g170"></span>
[[Board:winnet/g170|winnet/g170]] at Thu Oct  5 02:49:09 UTC 2017
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=0d3b11898b3ea117696b49c8a27854228e471902 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/winnet/g170/4.6-1689-g0d3b11898b/2017-10-05T02_49_09Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/winnet/g170/4.6-1689-g0d3b11898b/2017-10-05T02_49_09Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/winnet/g170/4.6-1689-g0d3b11898b/2017-10-05T02_49_09Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/winnet/g170/4.6-1689-g0d3b11898b/2017-10-05T02_49_09Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/winnet/g170/4.6-1689-g0d3b11898b/2017-10-05T02_49_09Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/winnet/g170/4.6-1689-g0d3b11898b/2017-10-05T02_49_09Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/winnet/g170/4.6-1689-g0d3b11898b/2017-10-05T02_49_09Z/rom_checksum.txt rom_checksum.txt]
)


= 2017W39 =
||
<span id="hp/2760p"></span>
|- bgcolor="#eeeeee"
[[Board:hp/2760p|hp/2760p]] at Sat Sep 30 20:34:28 UTC 2017
| X86EMU_DEBUG_VBE || toplevel || bool || Debug VESA BIOS Extensions ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=e9b862eb2c5918f097ff03498959e74130671c67 upstream tree] (
Print messages related to VESA BIOS Extension (VBE) functions.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/2760p/4.6-1643-ge9b862eb2c/2017-09-30T20_34_28Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/2760p/4.6-1643-ge9b862eb2c/2017-09-30T20_34_28Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/2760p/4.6-1643-ge9b862eb2c/2017-09-30T20_34_28Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/2760p/4.6-1643-ge9b862eb2c/2017-09-30T20_34_28Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/2760p/4.6-1643-ge9b862eb2c/2017-09-30T20_34_28Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/2760p/4.6-1643-ge9b862eb2c/2017-09-30T20_34_28Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/2760p/4.6-1643-ge9b862eb2c/2017-09-30T20_34_28Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/2760p/4.6-1643-ge9b862eb2c/2017-09-30T20_34_28Z/rom_checksum.txt rom_checksum.txt]
)


<span id="intel/d945gclf"></span>
Note: This option will increase the size of the coreboot image.
[[Board:intel/d945gclf|intel/d945gclf]] at Sat Sep 30 01:24:47 UTC 2017
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=c060fb5aace8b3445bb79bbaf74145a022022e57 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/d945gclf/4.6-1640-gc060fb5aac/2017-09-30T01_24_47Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/d945gclf/4.6-1640-gc060fb5aac/2017-09-30T01_24_47Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/d945gclf/4.6-1640-gc060fb5aac/2017-09-30T01_24_47Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/d945gclf/4.6-1640-gc060fb5aac/2017-09-30T01_24_47Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/d945gclf/4.6-1640-gc060fb5aac/2017-09-30T01_24_47Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/d945gclf/4.6-1640-gc060fb5aac/2017-09-30T01_24_47Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/d945gclf/4.6-1640-gc060fb5aac/2017-09-30T01_24_47Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/d945gclf/4.6-1640-gc060fb5aac/2017-09-30T01_24_47Z/rom_checksum.txt rom_checksum.txt]
)


= 2017W38 =
If unsure, say N.
<span id="intel/dg43gt"></span>
[[Board:intel/dg43gt|intel/dg43gt]] at Sat Sep 23 22:29:35 UTC 2017
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=8b64e7ae21f2042f837f3af222754e1e8ef5b3d6 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/dg43gt/4.6-1563-g8b64e7ae21/2017-09-23T22_29_35Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/dg43gt/4.6-1563-g8b64e7ae21/2017-09-23T22_29_35Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/dg43gt/4.6-1563-g8b64e7ae21/2017-09-23T22_29_35Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/dg43gt/4.6-1563-g8b64e7ae21/2017-09-23T22_29_35Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/dg43gt/4.6-1563-g8b64e7ae21/2017-09-23T22_29_35Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/dg43gt/4.6-1563-g8b64e7ae21/2017-09-23T22_29_35Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/dg43gt/4.6-1563-g8b64e7ae21/2017-09-23T22_29_35Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/dg43gt/4.6-1563-g8b64e7ae21/2017-09-23T22_29_35Z/rom_checksum.txt rom_checksum.txt]
)


= 2017W37 =
||
<span id="asus/p3b-f"></span>
|- bgcolor="#eeeeee"
[[Board:asus/p3b-f|asus/p3b-f]] at Wed Sep 13 17:26:27 UTC 2017
| X86EMU_DEBUG_INT10 || toplevel || bool || Redirect INT10 output to console ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=a097fb8fff28232e77aa8398edcb7810bbd72b44 upstream tree] (
Let INT10 (i.e. character output) calls print messages to debug output.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p3b-f/4.6-1437-ga097fb8fff/2017-09-13T17_26_27Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p3b-f/4.6-1437-ga097fb8fff/2017-09-13T17_26_27Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p3b-f/4.6-1437-ga097fb8fff/2017-09-13T17_26_27Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p3b-f/4.6-1437-ga097fb8fff/2017-09-13T17_26_27Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p3b-f/4.6-1437-ga097fb8fff/2017-09-13T17_26_27Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p3b-f/4.6-1437-ga097fb8fff/2017-09-13T17_26_27Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p3b-f/4.6-1437-ga097fb8fff/2017-09-13T17_26_27Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p3b-f/4.6-1437-ga097fb8fff/2017-09-13T17_26_27Z/rom_checksum.txt rom_checksum.txt]
)


<span id="asus/p2b-ls"></span>
Note: This option will increase the size of the coreboot image.
[[Board:asus/p2b-ls|asus/p2b-ls]] at Wed Sep 13 17:26:27 UTC 2017
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=a097fb8fff28232e77aa8398edcb7810bbd72b44 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p2b-ls/4.6-1437-ga097fb8fff/2017-09-13T17_26_27Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p2b-ls/4.6-1437-ga097fb8fff/2017-09-13T17_26_27Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p2b-ls/4.6-1437-ga097fb8fff/2017-09-13T17_26_27Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p2b-ls/4.6-1437-ga097fb8fff/2017-09-13T17_26_27Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p2b-ls/4.6-1437-ga097fb8fff/2017-09-13T17_26_27Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p2b-ls/4.6-1437-ga097fb8fff/2017-09-13T17_26_27Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p2b-ls/4.6-1437-ga097fb8fff/2017-09-13T17_26_27Z/rom_checksum.txt rom_checksum.txt]
)


= 2017W36 =
If unsure, say N.
<span id="intel/minnowmax"></span>
[[Board:intel/minnowmax|intel/minnowmax]] at Wed Sep  6 06:53:39 UTC 2017
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=3fd259c91d54fbfcd45e1cfe73ddfbf2359ddd78 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/minnowmax/4.6-1358-g49d117c69f/2017-09-06T06_53_39Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/minnowmax/4.6-1358-g49d117c69f/2017-09-06T06_53_39Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/minnowmax/4.6-1358-g49d117c69f/2017-09-06T06_53_39Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/minnowmax/4.6-1358-g49d117c69f/2017-09-06T06_53_39Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/minnowmax/4.6-1358-g49d117c69f/2017-09-06T06_53_39Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/minnowmax/4.6-1358-g49d117c69f/2017-09-06T06_53_39Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/minnowmax/4.6-1358-g49d117c69f/2017-09-06T06_53_39Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/minnowmax/4.6-1358-g49d117c69f/2017-09-06T06_53_39Z/rom_checksum.txt rom_checksum.txt]
)


<span id="asus/f2a85-m"></span>
||
[[Board:asus/f2a85-m|asus/f2a85-m]] at Mon Sep  4 11:13:36 UTC 2017
|- bgcolor="#eeeeee"
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=f516dd8b40a5221780865b40ed51d16cbbc91e56 upstream tree] (
| X86EMU_DEBUG_INTERRUPTS || toplevel || bool || Log intXX calls ||
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/f2a85-m/4.6-1308-gf4062dbd74-dirty/2017-09-04T11_13_36Z/cbfs.txt cbfs.txt]
Print messages related to interrupt handling.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/f2a85-m/4.6-1308-gf4062dbd74-dirty/2017-09-04T11_13_36Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/f2a85-m/4.6-1308-gf4062dbd74-dirty/2017-09-04T11_13_36Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/f2a85-m/4.6-1308-gf4062dbd74-dirty/2017-09-04T11_13_36Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/f2a85-m/4.6-1308-gf4062dbd74-dirty/2017-09-04T11_13_36Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/f2a85-m/4.6-1308-gf4062dbd74-dirty/2017-09-04T11_13_36Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/f2a85-m/4.6-1308-gf4062dbd74-dirty/2017-09-04T11_13_36Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/f2a85-m/4.6-1308-gf4062dbd74-dirty/2017-09-04T11_13_36Z/rom_checksum.txt rom_checksum.txt]
)


= 2017W35 =
Note: This option will increase the size of the coreboot image.
<span id="lippert/frontrunner-af"></span>
[[Board:lippert/frontrunner-af|lippert/frontrunner-af]] at Fri Sep  1 05:15:05 UTC 2017
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=d37ebddfd84699464d076642f35fce0ef21cd1d5 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lippert/frontrunner-af/4.6-1304-gd37ebdd/2017-09-01T05_15_05Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lippert/frontrunner-af/4.6-1304-gd37ebdd/2017-09-01T05_15_05Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lippert/frontrunner-af/4.6-1304-gd37ebdd/2017-09-01T05_15_05Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lippert/frontrunner-af/4.6-1304-gd37ebdd/2017-09-01T05_15_05Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lippert/frontrunner-af/4.6-1304-gd37ebdd/2017-09-01T05_15_05Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lippert/frontrunner-af/4.6-1304-gd37ebdd/2017-09-01T05_15_05Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lippert/frontrunner-af/4.6-1304-gd37ebdd/2017-09-01T05_15_05Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lippert/frontrunner-af/4.6-1304-gd37ebdd/2017-09-01T05_15_05Z/rom_checksum.txt rom_checksum.txt]
)


<span id="asrock/g41c-gs"></span>
If unsure, say N.
[[Board:asrock/g41c-gs|asrock/g41c-gs]] at Thu Aug 31 13:23:34 UTC 2017
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=b045d4cd7bc9337e34cf29dd1e57c3f6647c7ca7 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/g41c-gs/4.6-1287-g3d9de62bc7-dirty/2017-08-31T13_23_34Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/g41c-gs/4.6-1287-g3d9de62bc7-dirty/2017-08-31T13_23_34Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/g41c-gs/4.6-1287-g3d9de62bc7-dirty/2017-08-31T13_23_34Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/g41c-gs/4.6-1287-g3d9de62bc7-dirty/2017-08-31T13_23_34Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/g41c-gs/4.6-1287-g3d9de62bc7-dirty/2017-08-31T13_23_34Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/g41c-gs/4.6-1287-g3d9de62bc7-dirty/2017-08-31T13_23_34Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/g41c-gs/4.6-1287-g3d9de62bc7-dirty/2017-08-31T13_23_34Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/g41c-gs/4.6-1287-g3d9de62bc7-dirty/2017-08-31T13_23_34Z/rom_checksum.txt rom_checksum.txt]
)


<span id="amd/persimmon"></span>
||
[[Board:amd/persimmon|amd/persimmon]] at Tue Aug 29 11:37:06 UTC 2017
|- bgcolor="#eeeeee"
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=2900d4b92ecab16483b5a899d792e2c6716d397d upstream tree] (
| X86EMU_DEBUG_CHECK_VMEM_ACCESS || toplevel || bool || Log special memory accesses ||
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/persimmon/4.6-1260-g7bb032588459-dirty/2017-08-29T11_37_06Z/cbfs.txt cbfs.txt]
Print messages related to accesses to certain areas of the virtual
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/persimmon/4.6-1260-g7bb032588459-dirty/2017-08-29T11_37_06Z/config.short.txt config.short.txt]
memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/persimmon/4.6-1260-g7bb032588459-dirty/2017-08-29T11_37_06Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/persimmon/4.6-1260-g7bb032588459-dirty/2017-08-29T11_37_06Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/persimmon/4.6-1260-g7bb032588459-dirty/2017-08-29T11_37_06Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/persimmon/4.6-1260-g7bb032588459-dirty/2017-08-29T11_37_06Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/persimmon/4.6-1260-g7bb032588459-dirty/2017-08-29T11_37_06Z/rom_checksum.txt rom_checksum.txt]
)


= 2017W34 =
Note: This option will increase the size of the coreboot image.
<span id="sapphire/pureplatinumh61"></span>
[[Board:sapphire/pureplatinumh61|sapphire/pureplatinumh61]] at Sat Aug 26 16:30:37 UTC 2017
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=3f3025d7f1adc0fa1a405f14a0cbb6e4e319afe0 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/sapphire/pureplatinumh61/4.6-1237-g3f3025d7f1/2017-08-26T16_30_37Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/sapphire/pureplatinumh61/4.6-1237-g3f3025d7f1/2017-08-26T16_30_37Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/sapphire/pureplatinumh61/4.6-1237-g3f3025d7f1/2017-08-26T16_30_37Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/sapphire/pureplatinumh61/4.6-1237-g3f3025d7f1/2017-08-26T16_30_37Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/sapphire/pureplatinumh61/4.6-1237-g3f3025d7f1/2017-08-26T16_30_37Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/sapphire/pureplatinumh61/4.6-1237-g3f3025d7f1/2017-08-26T16_30_37Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/sapphire/pureplatinumh61/4.6-1237-g3f3025d7f1/2017-08-26T16_30_37Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/sapphire/pureplatinumh61/4.6-1237-g3f3025d7f1/2017-08-26T16_30_37Z/rom_checksum.txt rom_checksum.txt]
)


<span id="gizmosphere/gizmo"></span>
If unsure, say N.
[[Board:gizmosphere/gizmo|gizmosphere/gizmo]] at Fri Aug 25 20:33:26 UTC 2017
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=f61ffcf9a489fa5d971f8584450be0869e6ca78d upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gizmosphere/gizmo/4.6-1233-gf61ffcf/2017-08-25T20_33_26Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gizmosphere/gizmo/4.6-1233-gf61ffcf/2017-08-25T20_33_26Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gizmosphere/gizmo/4.6-1233-gf61ffcf/2017-08-25T20_33_26Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gizmosphere/gizmo/4.6-1233-gf61ffcf/2017-08-25T20_33_26Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gizmosphere/gizmo/4.6-1233-gf61ffcf/2017-08-25T20_33_26Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gizmosphere/gizmo/4.6-1233-gf61ffcf/2017-08-25T20_33_26Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gizmosphere/gizmo/4.6-1233-gf61ffcf/2017-08-25T20_33_26Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gizmosphere/gizmo/4.6-1233-gf61ffcf/2017-08-25T20_33_26Z/rom_checksum.txt rom_checksum.txt]
)


<span id="hp/8470p"></span>
||
[[Board:hp/8470p|hp/8470p]] at Thu Aug 24 12:08:03 UTC 2017
|- bgcolor="#eeeeee"
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=2900d4b92ecab16483b5a899d792e2c6716d397d upstream tree] (
| X86EMU_DEBUG_MEM || toplevel || bool || Log all memory accesses ||
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/8470p/4.6-1185-g2900d4b92e-dirty/2017-08-24T12_08_03Z/cbfs.txt cbfs.txt]
Print memory accesses made by option ROM.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/8470p/4.6-1185-g2900d4b92e-dirty/2017-08-24T12_08_03Z/config.short.txt config.short.txt]
Note: This also includes accesses to fetch instructions.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/8470p/4.6-1185-g2900d4b92e-dirty/2017-08-24T12_08_03Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/8470p/4.6-1185-g2900d4b92e-dirty/2017-08-24T12_08_03Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/8470p/4.6-1185-g2900d4b92e-dirty/2017-08-24T12_08_03Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/8470p/4.6-1185-g2900d4b92e-dirty/2017-08-24T12_08_03Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/8470p/4.6-1185-g2900d4b92e-dirty/2017-08-24T12_08_03Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/8470p/4.6-1185-g2900d4b92e-dirty/2017-08-24T12_08_03Z/rom_checksum.txt rom_checksum.txt]
)


<span id="asrock/imb-a180"></span>
Note: This option will increase the size of the coreboot image.
[[Board:asrock/imb-a180|asrock/imb-a180]] at Thu Aug 24 10:37:14 UTC 2017
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=74e854ca782304f6ec926eec6143d9fb72bd1e35 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/imb-a180/4.6-1184-g74e854c/2017-08-24T10_37_14Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/imb-a180/4.6-1184-g74e854c/2017-08-24T10_37_14Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/imb-a180/4.6-1184-g74e854c/2017-08-24T10_37_14Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/imb-a180/4.6-1184-g74e854c/2017-08-24T10_37_14Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/imb-a180/4.6-1184-g74e854c/2017-08-24T10_37_14Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/imb-a180/4.6-1184-g74e854c/2017-08-24T10_37_14Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/imb-a180/4.6-1184-g74e854c/2017-08-24T10_37_14Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asrock/imb-a180/4.6-1184-g74e854c/2017-08-24T10_37_14Z/rom_checksum.txt rom_checksum.txt]
)


= 2017W24 =
If unsure, say N.
<span id="asus/p5gc-mx"></span>
[[Board:asus/p5gc-mx|asus/p5gc-mx]] at Sat Jun 17 18:00:03 UTC 2017
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=9a848dde8b34a854af716670f5c993c49c1ab22e upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p5gc-mx/4.6-468-g9a848dd/2017-06-17T18_00_03Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p5gc-mx/4.6-468-g9a848dd/2017-06-17T18_00_03Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p5gc-mx/4.6-468-g9a848dd/2017-06-17T18_00_03Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p5gc-mx/4.6-468-g9a848dd/2017-06-17T18_00_03Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p5gc-mx/4.6-468-g9a848dd/2017-06-17T18_00_03Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p5gc-mx/4.6-468-g9a848dd/2017-06-17T18_00_03Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p5gc-mx/4.6-468-g9a848dd/2017-06-17T18_00_03Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/p5gc-mx/4.6-468-g9a848dd/2017-06-17T18_00_03Z/rom_checksum.txt rom_checksum.txt]
)


= 2017W20 =
||
<span id="emulation/qemu-i440fx"></span>
|- bgcolor="#eeeeee"
[[Board:emulation/qemu-i440fx|emulation/qemu-i440fx]] at Wed May 17 17:09:18 UTC 2017
| X86EMU_DEBUG_IO || toplevel || bool || Log IO accesses ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=c5eab98e78878b25e01f374d63ab161555447c41 upstream tree] (
Print I/O accesses made by option ROM.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/emulation/qemu-i440fx/4.6-136-gc5eab98-dirty/2017-05-17T17_09_18Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/emulation/qemu-i440fx/4.6-136-gc5eab98-dirty/2017-05-17T17_09_18Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/emulation/qemu-i440fx/4.6-136-gc5eab98-dirty/2017-05-17T17_09_18Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/emulation/qemu-i440fx/4.6-136-gc5eab98-dirty/2017-05-17T17_09_18Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/emulation/qemu-i440fx/4.6-136-gc5eab98-dirty/2017-05-17T17_09_18Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/emulation/qemu-i440fx/4.6-136-gc5eab98-dirty/2017-05-17T17_09_18Z/rom_checksum.txt rom_checksum.txt]
)


= 2017W17 =
Note: This option will increase the size of the coreboot image.
<span id="lenovo/t420"></span>
[[Board:lenovo/t420|lenovo/t420]] at Tue Apr 25 04:15:46 UTC 2017
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=7e438af99575365a97f87f59e83e1224571ac5c2 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t420/4.5-1640-g7e438af995/2017-04-25T04_15_46Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t420/4.5-1640-g7e438af995/2017-04-25T04_15_46Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t420/4.5-1640-g7e438af995/2017-04-25T04_15_46Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t420/4.5-1640-g7e438af995/2017-04-25T04_15_46Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t420/4.5-1640-g7e438af995/2017-04-25T04_15_46Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t420/4.5-1640-g7e438af995/2017-04-25T04_15_46Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t420/4.5-1640-g7e438af995/2017-04-25T04_15_46Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t420/4.5-1640-g7e438af995/2017-04-25T04_15_46Z/rom_checksum.txt rom_checksum.txt]
)


= 2017W16 =
If unsure, say N.
<span id="gigabyte/m57sli"></span>
[[Board:gigabyte/m57sli|gigabyte/m57sli]] at Mon Apr 17 16:31:52 UTC 2017
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=7b58319e9c320426f7dee202bf9201b6628bf958 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/m57sli/4.5-1526-g76e3c9810e/2017-04-17T16_31_52Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/m57sli/4.5-1526-g76e3c9810e/2017-04-17T16_31_52Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/m57sli/4.5-1526-g76e3c9810e/2017-04-17T16_31_52Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/m57sli/4.5-1526-g76e3c9810e/2017-04-17T16_31_52Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/m57sli/4.5-1526-g76e3c9810e/2017-04-17T16_31_52Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/m57sli/4.5-1526-g76e3c9810e/2017-04-17T16_31_52Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/m57sli/4.5-1526-g76e3c9810e/2017-04-17T16_31_52Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/m57sli/4.5-1526-g76e3c9810e/2017-04-17T16_31_52Z/rom_checksum.txt rom_checksum.txt]
)


<span id="gigabyte/ga-945gcm-s2l"></span>
||
[[Board:gigabyte/ga-945gcm-s2l|gigabyte/ga-945gcm-s2l]] at Mon Apr 17 16:12:02 UTC 2017
|- bgcolor="#eeeeee"
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=7b58319e9c320426f7dee202bf9201b6628bf958 upstream tree] (
| X86EMU_DEBUG_TIMINGS || toplevel || bool || Output timing information ||
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-945gcm-s2l/4.5-1568-g7b58319e9c/2017-04-17T16_12_02Z/cbfs.txt cbfs.txt]
Print timing information needed by i915tool.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-945gcm-s2l/4.5-1568-g7b58319e9c/2017-04-17T16_12_02Z/config.short.txt config.short.txt]
 
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-945gcm-s2l/4.5-1568-g7b58319e9c/2017-04-17T16_12_02Z/config.txt config.txt]
If unsure, say N.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-945gcm-s2l/4.5-1568-g7b58319e9c/2017-04-17T16_12_02Z/coreboot_console.txt coreboot_console.txt]
 
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-945gcm-s2l/4.5-1568-g7b58319e9c/2017-04-17T16_12_02Z/coreboot_timestamps.txt coreboot_timestamps.txt]
||
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-945gcm-s2l/4.5-1568-g7b58319e9c/2017-04-17T16_12_02Z/kernel_log.txt kernel_log.txt]
|- bgcolor="#eeeeee"
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-945gcm-s2l/4.5-1568-g7b58319e9c/2017-04-17T16_12_02Z/payload_config.txt payload_config.txt]
| DEBUG_SPI_FLASH || toplevel || bool || Output verbose SPI flash debug messages ||
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ga-945gcm-s2l/4.5-1568-g7b58319e9c/2017-04-17T16_12_02Z/rom_checksum.txt rom_checksum.txt]
This option enables additional SPI flash related debug messages.
)


= 2017W14 =
||
<span id="purism/librem13"></span>
|- bgcolor="#eeeeee"
[[Board:purism/librem13|purism/librem13]] at Fri Apr  7 19:59:53 UTC 2017
| DEBUG_USBDEBUG || toplevel || bool || Output verbose USB 2.0 EHCI debug dongle messages ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=fe41ae936ab0d520fa5319a0442252260d971fda upstream tree] (
This option enables additional USB 2.0 debug dongle related messages.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/purism/librem13/4.5-1503-gfe41ae9/2017-04-07T19_59_53Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/purism/librem13/4.5-1503-gfe41ae9/2017-04-07T19_59_53Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/purism/librem13/4.5-1503-gfe41ae9/2017-04-07T19_59_53Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/purism/librem13/4.5-1503-gfe41ae9/2017-04-07T19_59_53Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/purism/librem13/4.5-1503-gfe41ae9/2017-04-07T19_59_53Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/purism/librem13/4.5-1503-gfe41ae9/2017-04-07T19_59_53Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/purism/librem13/4.5-1503-gfe41ae9/2017-04-07T19_59_53Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/purism/librem13/4.5-1503-gfe41ae9/2017-04-07T19_59_53Z/rom_checksum.txt rom_checksum.txt]
)


<span id="google/slippy"></span>
Select this to debug the connection of usbdebug dongle. Note that
[[Board:google/slippy|google/slippy]] at Tue Apr  4 20:03:46 UTC 2017
you need some other working console to receive the messages.
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=b85ddc787ee2e82712b95b2eb3b90f4b56698e41 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/slippy/4.5-1441-g1e05435-dirty/2017-04-04T20_03_46Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/slippy/4.5-1441-g1e05435-dirty/2017-04-04T20_03_46Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/slippy/4.5-1441-g1e05435-dirty/2017-04-04T20_03_46Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/slippy/4.5-1441-g1e05435-dirty/2017-04-04T20_03_46Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/slippy/4.5-1441-g1e05435-dirty/2017-04-04T20_03_46Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/slippy/4.5-1441-g1e05435-dirty/2017-04-04T20_03_46Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/slippy/4.5-1441-g1e05435-dirty/2017-04-04T20_03_46Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/slippy/4.5-1441-g1e05435-dirty/2017-04-04T20_03_46Z/rom_checksum.txt rom_checksum.txt]
)


= 2017W11 =
||
<span id="samsung/lumpy"></span>
|- bgcolor="#eeeeee"
[[Board:samsung/lumpy|samsung/lumpy]] at Fri Mar 17 21:13:34 UTC 2017
| DEBUG_INTEL_ME || toplevel || bool || Verbose logging for Intel Management Engine ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=216712ae01993e83265470de1e29744a0970e4fa upstream tree] (
Enable verbose logging for Intel Management Engine driver that
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/samsung/lumpy/4.5-1342-g216712ae01/2017-03-17T21_13_34Z/cbfs.txt cbfs.txt]
is present on Intel 6-series chipsets.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/samsung/lumpy/4.5-1342-g216712ae01/2017-03-17T21_13_34Z/config.short.txt config.short.txt]
||
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/samsung/lumpy/4.5-1342-g216712ae01/2017-03-17T21_13_34Z/config.txt config.txt]
|- bgcolor="#eeeeee"
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/samsung/lumpy/4.5-1342-g216712ae01/2017-03-17T21_13_34Z/coreboot_console.txt coreboot_console.txt]
| TRACE || toplevel || bool || Trace function calls ||
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/samsung/lumpy/4.5-1342-g216712ae01/2017-03-17T21_13_34Z/coreboot_timestamps.txt coreboot_timestamps.txt]
If enabled, every function will print information to console once
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/samsung/lumpy/4.5-1342-g216712ae01/2017-03-17T21_13_34Z/kernel_log.txt kernel_log.txt]
the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/samsung/lumpy/4.5-1342-g216712ae01/2017-03-17T21_13_34Z/payload_config.txt payload_config.txt]
the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/samsung/lumpy/4.5-1342-g216712ae01/2017-03-17T21_13_34Z/rom_checksum.txt rom_checksum.txt]
of calling function. Please note some printk related functions
)
are omitted from trace to have good looking console dumps.


= 2017W01 =
||
<span id="lenovo/t500"></span>
|- bgcolor="#eeeeee"
[[Board:lenovo/t500|lenovo/t500]] at Sun Jan  8 20:18:39 UTC 2017
| DEBUG_COVERAGE || toplevel || bool || Debug code coverage ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=e39a8a9c092ed66686632d591ec84ed7a6165a50 upstream tree] (
If enabled, the code coverage hooks in coreboot will output some
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t500/4.5-322-ge39a8a9c09-dirty/2017-01-08T20_18_39Z/cbfs.txt cbfs.txt]
information about the coverage data that is dumped.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t500/4.5-322-ge39a8a9c09-dirty/2017-01-08T20_18_39Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t500/4.5-322-ge39a8a9c09-dirty/2017-01-08T20_18_39Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t500/4.5-322-ge39a8a9c09-dirty/2017-01-08T20_18_39Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t500/4.5-322-ge39a8a9c09-dirty/2017-01-08T20_18_39Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t500/4.5-322-ge39a8a9c09-dirty/2017-01-08T20_18_39Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t500/4.5-322-ge39a8a9c09-dirty/2017-01-08T20_18_39Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t500/4.5-322-ge39a8a9c09-dirty/2017-01-08T20_18_39Z/rom_checksum.txt rom_checksum.txt]
)


<span id="amd/gardenia"></span>
||
[[Board:amd/gardenia|amd/gardenia]] at Fri Jan  6 16:30:58 UTC 2017
|- bgcolor="#eeeeee"
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=49342cd6880b3f2a8e20957d976914cd4ee7b43d upstream tree] (
| DEBUG_BOOT_STATE || toplevel || bool || Debug boot state machine ||
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/gardenia/4.5-762-g49342cd/2017-01-06T16_30_58Z/cbfs.txt cbfs.txt]
Control debugging of the boot state machine. When selected displays
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/gardenia/4.5-762-g49342cd/2017-01-06T16_30_58Z/config.short.txt config.short.txt]
the state boundaries in ramstage.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/gardenia/4.5-762-g49342cd/2017-01-06T16_30_58Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/gardenia/4.5-762-g49342cd/2017-01-06T16_30_58Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/gardenia/4.5-762-g49342cd/2017-01-06T16_30_58Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/gardenia/4.5-762-g49342cd/2017-01-06T16_30_58Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/gardenia/4.5-762-g49342cd/2017-01-06T16_30_58Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/gardenia/4.5-762-g49342cd/2017-01-06T16_30_58Z/rom_checksum.txt rom_checksum.txt]
)


= 2016W48 =
||
<span id="aopen/dxplplusu"></span>
|- bgcolor="#eeeeee"
[[Board:aopen/dxplplusu|aopen/dxplplusu]] at Sun Dec  4 02:03:58 UTC 2016
| DEBUG_ADA_CODE || toplevel || bool || Compile debug code in Ada sources ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=52896c6c33250036928406d9dc38aa2ce1906b05 upstream tree] (
Add the compiler switch `-gnata` to compile code guarded by
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/aopen/dxplplusu/4.5-485-g52896c6/2016-12-04T02_03_58Z/cbfs.txt cbfs.txt]
`pragma Debug`.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/aopen/dxplplusu/4.5-485-g52896c6/2016-12-04T02_03_58Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/aopen/dxplplusu/4.5-485-g52896c6/2016-12-04T02_03_58Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/aopen/dxplplusu/4.5-485-g52896c6/2016-12-04T02_03_58Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/aopen/dxplplusu/4.5-485-g52896c6/2016-12-04T02_03_58Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/aopen/dxplplusu/4.5-485-g52896c6/2016-12-04T02_03_58Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/aopen/dxplplusu/4.5-485-g52896c6/2016-12-04T02_03_58Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/aopen/dxplplusu/4.5-485-g52896c6/2016-12-04T02_03_58Z/rom_checksum.txt rom_checksum.txt]
)


= 2016W47 =
||
<span id="google/peppy"></span>
[[Board:google/peppy|google/peppy]] at Mon Nov 21 01:21:17 UTC 2016
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=378d79eb30f1fd990a17b26840741adfce35a8a2 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/peppy/4.5-341-g378d79e/2016-11-21T01_21_17Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/peppy/4.5-341-g378d79e/2016-11-21T01_21_17Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/peppy/4.5-341-g378d79e/2016-11-21T01_21_17Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/peppy/4.5-341-g378d79e/2016-11-21T01_21_17Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/peppy/4.5-341-g378d79e/2016-11-21T01_21_17Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/peppy/4.5-341-g378d79e/2016-11-21T01_21_17Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/peppy/4.5-341-g378d79e/2016-11-21T01_21_17Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/peppy/4.5-341-g378d79e/2016-11-21T01_21_17Z/rom_checksum.txt rom_checksum.txt]
)


= 2016W34 =
|- bgcolor="#eeeeee"
<span id="asus/kfsn4-dre_k8"></span>
| NO_EDID_FILL_FB || lib || bool ||  ||
[[Board:asus/kfsn4-dre_k8|asus/kfsn4-dre_k8]] at Mon Aug 22 02:19:24 UTC 2016
Don't include default fill_lb_framebuffer() implementation. Select
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=1bc2b0bed0f75c81153ace65679e761a4cb1438c upstream tree] (
this if your drivers uses MAINBOARD_DO_NATIVE_VGA_INIT but provides
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kfsn4-dre_k8/4.4-1290-g1bc2b0b/2016-08-22T02_19_24Z/cbfs.txt cbfs.txt]
its own fill_lb_framebuffer() implementation.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kfsn4-dre_k8/4.4-1290-g1bc2b0b/2016-08-22T02_19_24Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kfsn4-dre_k8/4.4-1290-g1bc2b0b/2016-08-22T02_19_24Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kfsn4-dre_k8/4.4-1290-g1bc2b0b/2016-08-22T02_19_24Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kfsn4-dre_k8/4.4-1290-g1bc2b0b/2016-08-22T02_19_24Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kfsn4-dre_k8/4.4-1290-g1bc2b0b/2016-08-22T02_19_24Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kfsn4-dre_k8/4.4-1290-g1bc2b0b/2016-08-22T02_19_24Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/kfsn4-dre_k8/4.4-1290-g1bc2b0b/2016-08-22T02_19_24Z/rom_checksum.txt rom_checksum.txt]
)


= 2016W19 =
||
<span id="siemens/mc_tcu3"></span>
|- bgcolor="#eeeeee"
[[Board:siemens/mc_tcu3|siemens/mc_tcu3]] at Mon May 9 06:14:45 UTC 2016
| RAMSTAGE_ADA || lib || bool || ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=d2ea674635def43f639af6343e7cd3905314563d upstream tree] (
Selected by features that use Ada code in ramstage.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/siemens/mc_tcu3/4.4-108-g0d4e124/2016-05-09T06_14_45Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/siemens/mc_tcu3/4.4-108-g0d4e124/2016-05-09T06_14_45Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/siemens/mc_tcu3/4.4-108-g0d4e124/2016-05-09T06_14_45Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/siemens/mc_tcu3/4.4-108-g0d4e124/2016-05-09T06_14_45Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/siemens/mc_tcu3/4.4-108-g0d4e124/2016-05-09T06_14_45Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/siemens/mc_tcu3/4.4-108-g0d4e124/2016-05-09T06_14_45Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/siemens/mc_tcu3/4.4-108-g0d4e124/2016-05-09T06_14_45Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/siemens/mc_tcu3/4.4-108-g0d4e124/2016-05-09T06_14_45Z/rom_checksum.txt rom_checksum.txt]
)


= 2016W16 =
||
<span id="google/panther"></span>
|- bgcolor="#eeeeee"
[[Board:google/panther|google/panther]] at Mon Apr 18 13:11:58 UTC 2016
| RAMSTAGE_LIBHWBASE || lib || bool ||  ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=41f0e0fd4dcb630f48d11dc5d7c6fde87ae1c995 upstream tree] (
Selected by features that require `libhwbase` in ramstage.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/panther/4.3-777-g4774bb9/2016-04-18T13_11_58Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/panther/4.3-777-g4774bb9/2016-04-18T13_11_58Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/panther/4.3-777-g4774bb9/2016-04-18T13_11_58Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/panther/4.3-777-g4774bb9/2016-04-18T13_11_58Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/panther/4.3-777-g4774bb9/2016-04-18T13_11_58Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/panther/4.3-777-g4774bb9/2016-04-18T13_11_58Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/panther/4.3-777-g4774bb9/2016-04-18T13_11_58Z/rom_checksum.txt rom_checksum.txt]
)


= 2016W09 =
||
<span id="lenovo/t520"></span>
|- bgcolor="#eeeeee"
[[Board:lenovo/t520|lenovo/t520]] at Thu Mar 3 08:19:11 UTC 2016
| FLATTENED_DEVICE_TREE || lib || bool || ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=ebf732b4a52874cf1579153d6f3d24e2b94e15dc upstream tree] (
Selected by features that require to parse and manipulate a flattened
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t520/4.3-352-gebf732b-dirty/2016-03-03T08_19_11Z/cbfs.txt cbfs.txt]
devicetree in ramstage.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t520/4.3-352-gebf732b-dirty/2016-03-03T08_19_11Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t520/4.3-352-gebf732b-dirty/2016-03-03T08_19_11Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t520/4.3-352-gebf732b-dirty/2016-03-03T08_19_11Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t520/4.3-352-gebf732b-dirty/2016-03-03T08_19_11Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t520/4.3-352-gebf732b-dirty/2016-03-03T08_19_11Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t520/4.3-352-gebf732b-dirty/2016-03-03T08_19_11Z/rom_checksum.txt rom_checksum.txt]
)


= 2016W05 =
||
<span id="amd/thatcher"></span>
|- bgcolor="#eeeeee"
[[Board:amd/thatcher|amd/thatcher]] at Thu Feb 4 18:30:40 UTC 2016
| POWER_BUTTON_DEFAULT_ENABLE || toplevel || bool || ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=380e1676802825fa0b9429c3438f366d413f1297 upstream tree] (
Select when the board has a power button which can optionally be
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/thatcher/4.3-102-g380e167/2016-02-04T18_30_40Z/cbfs.txt cbfs.txt]
disabled by the user.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/thatcher/4.3-102-g380e167/2016-02-04T18_30_40Z/config.short.txt config.short.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/thatcher/4.3-102-g380e167/2016-02-04T18_30_40Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/thatcher/4.3-102-g380e167/2016-02-04T18_30_40Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/thatcher/4.3-102-g380e167/2016-02-04T18_30_40Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/thatcher/4.3-102-g380e167/2016-02-04T18_30_40Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/thatcher/4.3-102-g380e167/2016-02-04T18_30_40Z/payload_config.txt payload_config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/thatcher/4.3-102-g380e167/2016-02-04T18_30_40Z/rom_checksum.txt rom_checksum.txt]
)


= 2015W43 =
||
<span id="asus/m4a785t-m"></span>
|- bgcolor="#eeeeee"
[[Board:asus/m4a785t-m|asus/m4a785t-m]] at Thu Oct 22 18:20:48 UTC 2015
| POWER_BUTTON_DEFAULT_DISABLE || toplevel || bool ||  ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=a4ffe8aa4981130b240eee5ed22c5bbfa1c7598b upstream tree] (
Select when the board has a power button which can optionally be
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/m4a785t-m/4.1-782-ga4ffe8a/2015-10-22T18:20:48Z/cbfs.txt cbfs.txt]
enabled by the user, e.g. when the board ships with a jumper over
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/m4a785t-m/4.1-782-ga4ffe8a/2015-10-22T18:20:48Z/config.short.txt config.short.txt]
the power switch contacts.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/m4a785t-m/4.1-782-ga4ffe8a/2015-10-22T18:20:48Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/m4a785t-m/4.1-782-ga4ffe8a/2015-10-22T18:20:48Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/m4a785t-m/4.1-782-ga4ffe8a/2015-10-22T18:20:48Z/kernel_log.txt kernel_log.txt]
)


= 2015W27 =
||
<span id="gigabyte/ma785gmt"></span>
|- bgcolor="#eeeeee"
[[Board:gigabyte/ma785gmt|gigabyte/ma785gmt]] at Thu Jul 2 05:20:16 UTC 2015
| POWER_BUTTON_FORCE_ENABLE || toplevel || bool || ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id= upstream tree] (
Select when the board requires that the power button is always
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ma785gmt/4.0-8824-g5a25e1b-dirty/2015-07-02T05:20:16Z/cbfs.txt cbfs.txt]
enabled.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ma785gmt/4.0-8824-g5a25e1b-dirty/2015-07-02T05:20:16Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ma785gmt/4.0-8824-g5a25e1b-dirty/2015-07-02T05:20:16Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ma785gmt/4.0-8824-g5a25e1b-dirty/2015-07-02T05:20:16Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/gigabyte/ma785gmt/4.0-8824-g5a25e1b-dirty/2015-07-02T05:20:16Z/kernel_log.txt kernel_log.txt]
)


= 2015W18 =
||
<span id="amd/lamar"></span>
|- bgcolor="#eeeeee"
[[Board:amd/lamar|amd/lamar]] at Thu Apr 30 02:12:19 UTC 2015
| POWER_BUTTON_FORCE_DISABLE || toplevel || bool ||  ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=ae5ab604d51815bfed964017fad815c002aca9fe upstream tree] (
Select when the board requires that the power button is always
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/lamar/4.0-9540-gae5ab60/2015-04-30T02:12:19Z/cbfs.txt cbfs.txt]
disabled, e.g. when it has been hardwired to ground.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/lamar/4.0-9540-gae5ab60/2015-04-30T02:12:19Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/lamar/4.0-9540-gae5ab60/2015-04-30T02:12:19Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/lamar/4.0-9540-gae5ab60/2015-04-30T02:12:19Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/lamar/4.0-9540-gae5ab60/2015-04-30T02:12:19Z/kernel_log.txt kernel_log.txt]
)


= 2015W16 =
||
<span id="biostar/am1ml"></span>
|- bgcolor="#eeeeee"
[[Board:biostar/am1ml|biostar/am1ml]] at Mon Apr 13 11:03:01 UTC 2015
| POWER_BUTTON_IS_OPTIONAL || toplevel || bool ||  ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=36fd82dfc4523adc08cce5d553b8ae8575e77ab5 upstream tree] (
Internal option that controls ENABLE_POWER_BUTTON visibility.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/biostar/am1ml/4.0-9113-g36fd82d/2015-04-13T11:03:01Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/biostar/am1ml/4.0-9113-g36fd82d/2015-04-13T11:03:01Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/biostar/am1ml/4.0-9113-g36fd82d/2015-04-13T11:03:01Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/biostar/am1ml/4.0-9113-g36fd82d/2015-04-13T11:03:01Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/biostar/am1ml/4.0-9113-g36fd82d/2015-04-13T11:03:01Z/kernel_log.txt kernel_log.txt]
)


= 2014W49 =
||
<span id="hp/pavilion_m6_1035dx"></span>
|- bgcolor="#eeeeee"
[[Board:hp/pavilion_m6_1035dx|hp/pavilion_m6_1035dx]] at Sat Dec 6 10:30:54 UTC 2014
| REG_SCRIPT || toplevel || bool || ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=4568f19d1fb0d118e5fcebbe82b7878951c4bfff upstream tree] (
Internal option that controls whether we compile in register scripts.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/pavilion_m6_1035dx/4.0-7494-g4568f19-dirty/2014-12-06T10:30:54Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/pavilion_m6_1035dx/4.0-7494-g4568f19-dirty/2014-12-06T10:30:54Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/pavilion_m6_1035dx/4.0-7494-g4568f19-dirty/2014-12-06T10:30:54Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/pavilion_m6_1035dx/4.0-7494-g4568f19-dirty/2014-12-06T10:30:54Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/hp/pavilion_m6_1035dx/4.0-7494-g4568f19-dirty/2014-12-06T10:30:54Z/kernel_log.txt kernel_log.txt]
)


= 2014W46 =
||
<span id="google/falco"></span>
|- bgcolor="#eeeeee"
[[Board:google/falco|google/falco]] at Fri Nov 14 10:47:14 UTC 2014
| MAX_REBOOT_CNT || toplevel || int ||  ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=5c3452b80032eb81cc458d1fae63089ccc96d95a upstream tree] (
Internal option that sets the maximum number of bootblock executions allowed
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/falco/4.0-6588-g4acd8ea-dirty/2014-11-14T10:47:14Z/cbfs.txt cbfs.txt]
with the normal image enabled before assuming the normal image is defective
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/falco/4.0-6588-g4acd8ea-dirty/2014-11-14T10:47:14Z/config.txt config.txt]
and switching to the fallback image.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/falco/4.0-6588-g4acd8ea-dirty/2014-11-14T10:47:14Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/falco/4.0-6588-g4acd8ea-dirty/2014-11-14T10:47:14Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/falco/4.0-6588-g4acd8ea-dirty/2014-11-14T10:47:14Z/kernel_log.txt kernel_log.txt]
)


= 2014W41 =
||
<span id="amd/olivehill"></span>
|- bgcolor="#eeeeee"
[[Board:amd/olivehill|amd/olivehill]] at Wed Oct 8 13:44:17 UTC 2014
| CREATE_BOARD_CHECKLIST || toplevel || bool || ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=b9a0809faeeef67e46cda17cf8f7a839c6fe614c upstream tree] (
When selected, creates a webpage showing the implementation status for
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/olivehill/4.0-7005-gb9a0809/2014-10-08T13:44:17Z/cbfs.txt cbfs.txt]
the board. Routines highlighted in green are complete, yellow are
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/olivehill/4.0-7005-gb9a0809/2014-10-08T13:44:17Z/config.txt config.txt]
optional and red are required and must be implemented. A table is
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/olivehill/4.0-7005-gb9a0809/2014-10-08T13:44:17Z/coreboot_console.txt coreboot_console.txt]
produced for each stage of the boot process except the bootblock. The
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/olivehill/4.0-7005-gb9a0809/2014-10-08T13:44:17Z/coreboot_timestamps.txt coreboot_timestamps.txt]
red items may be used as an implementation checklist for the board.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/olivehill/4.0-7005-gb9a0809/2014-10-08T13:44:17Z/kernel_log.txt kernel_log.txt]
)


= 2014W39 =
||
<span id="amd/olivehillplus"></span>
|- bgcolor="#eeeeee"
[[Board:amd/olivehillplus|amd/olivehillplus]] at Wed Sep 24 05:58:25 UTC 2014
| MAKE_CHECKLIST_PUBLIC || toplevel || bool ||  ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=ea8f3b4aa0029871ee36a953a927c1af081343c5 upstream tree] (
When selected, build/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/olivehillplus/4.0-6958-gea8f3b4/2014-09-24T05:58:25Z/cbfs.txt cbfs.txt]
is copied into the Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/olivehillplus/4.0-6958-gea8f3b4/2014-09-24T05:58:25Z/config.txt config.txt]
directory.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/olivehillplus/4.0-6958-gea8f3b4/2014-09-24T05:58:25Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/olivehillplus/4.0-6958-gea8f3b4/2014-09-24T05:58:25Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/amd/olivehillplus/4.0-6958-gea8f3b4/2014-09-24T05:58:25Z/kernel_log.txt kernel_log.txt]
)


= 2014W37 =
||
<span id="google/parrot"></span>
|- bgcolor="#eeeeee"
[[Board:google/parrot|google/parrot]] at Sat Sep 13 00:21:02 UTC 2014
| CHECKLIST_DATA_FILE_LOCATION || toplevel || string ||  ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=85620db107d587a8341987162d403f4b7aee9a81 upstream tree] (
Location of the &lt;stage&gt;_complete.dat and &lt;stage&gt;_optional.dat files
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/parrot/4.0-6919-g85620db/2014-09-13T00:21:02Z/cbfs.txt cbfs.txt]
that are consumed during checklist processing. &lt;stage&gt;_complete.dat
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/parrot/4.0-6919-g85620db/2014-09-13T00:21:02Z/config.txt config.txt]
contains the symbols that are expected to be in the resulting image.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/parrot/4.0-6919-g85620db/2014-09-13T00:21:02Z/coreboot_console.txt coreboot_console.txt]
&lt;stage&gt;_optional.dat is a subset of &lt;stage&gt;_complete.dat and contains
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/parrot/4.0-6919-g85620db/2014-09-13T00:21:02Z/coreboot_timestamps.txt coreboot_timestamps.txt]
a list of weak symbols which the resulting image may consume. Other
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/parrot/4.0-6919-g85620db/2014-09-13T00:21:02Z/kernel_log.txt kernel_log.txt]
symbols contained only in &lt;stage&gt;_complete.dat will be flagged as
)
required and not implemented if a weak implementation is found in the
resulting image.


<span id="lenovo/t530"></span>
||
[[Board:lenovo/t530|lenovo/t530]] at Thu Sep 11 14:20:53 UTC 2014
|- bgcolor="#eeeeee"
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=955ca5d948519e89573b1508bb85d3b01353ac60 upstream tree] (
| NO_XIP_EARLY_STAGES || toplevel || bool ||  ||
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t530/4.0-6896-g955ca5d/2014-09-11T14:20:53Z/cbfs.txt cbfs.txt]
Identify if early stages are eXecute-In-Place(XIP).
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t530/4.0-6896-g955ca5d/2014-09-11T14:20:53Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t530/4.0-6896-g955ca5d/2014-09-11T14:20:53Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t530/4.0-6896-g955ca5d/2014-09-11T14:20:53Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/lenovo/t530/4.0-6896-g955ca5d/2014-09-11T14:20:53Z/kernel_log.txt kernel_log.txt]
)


= 2014W34 =
||
<span id="apple/macbook21"></span>
|- bgcolor="#eeeeee"
[[Board:apple/macbook21|apple/macbook21]] at Sun Aug 17 22:05:53 UTC 2014
| EARLY_CBMEM_LIST || toplevel || bool ||  ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=7aa704b822008efbbd540e97ae73f1c7d95e2c7d upstream tree] (
Enable display of CBMEM during romstage and postcar.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/apple/macbook21/4.0-6741-g7aa704b/2014-08-17T22:05:53Z/cbfs.txt cbfs.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/apple/macbook21/4.0-6741-g7aa704b/2014-08-17T22:05:53Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/apple/macbook21/4.0-6741-g7aa704b/2014-08-17T22:05:53Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/apple/macbook21/4.0-6741-g7aa704b/2014-08-17T22:05:53Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/apple/macbook21/4.0-6741-g7aa704b/2014-08-17T22:05:53Z/kernel_log.txt kernel_log.txt]
)


= 2014W31 =
||
<span id="packardbell/ms2290"></span>
|- bgcolor="#eeeeee"
[[Board:packardbell/ms2290|packardbell/ms2290]] at Fri Aug 1 17:32:20 UTC 2014
| RELOCATABLE_MODULES || toplevel || bool || ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=b98ab4a893798a5bda9d143943f6930ffaae2b68 upstream tree] (
If RELOCATABLE_MODULES is selected then support is enabled for
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/packardbell/ms2290/4.0-6558-gb98ab4a/2014-08-01T17:32:20Z/cbfs.txt cbfs.txt]
building relocatable modules in the RAM stage. Those modules can be
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/packardbell/ms2290/4.0-6558-gb98ab4a/2014-08-01T17:32:20Z/config.txt config.txt]
loaded anywhere and all the relocations are handled automatically.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/packardbell/ms2290/4.0-6558-gb98ab4a/2014-08-01T17:32:20Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/packardbell/ms2290/4.0-6558-gb98ab4a/2014-08-01T17:32:20Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/packardbell/ms2290/4.0-6558-gb98ab4a/2014-08-01T17:32:20Z/kernel_log.txt kernel_log.txt]
)


= 2014W26 =
||
<span id="intel/bayleybay_fsp"></span>
|- bgcolor="#eeeeee"
[[Board:intel/bayleybay_fsp|intel/bayleybay_fsp]] at Wed Jun 25 23:32:28 UTC 2014
| NO_STAGE_CACHE || toplevel || bool ||  ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=bcd09930d8ff78704cb98ad18805788d02687a31 upstream tree] (
Do not save any component in stage cache for resume path. On resume,
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/bayleybay_fsp/4.0-6293-g0b4b230/2014-06-25T23:32:28Z/cbfs.txt cbfs.txt]
all components would be read back from CBFS again.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/bayleybay_fsp/4.0-6293-g0b4b230/2014-06-25T23:32:28Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/bayleybay_fsp/4.0-6293-g0b4b230/2014-06-25T23:32:28Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/bayleybay_fsp/4.0-6293-g0b4b230/2014-06-25T23:32:28Z/intel_baytrail_fsp.txt intel_baytrail_fsp.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/bayleybay_fsp/4.0-6293-g0b4b230/2014-06-25T23:32:28Z/kernel_log.txt kernel_log.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/bayleybay_fsp/4.0-6293-g0b4b230/2014-06-25T23:32:28Z/seabios.config seabios.config]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/intel/bayleybay_fsp/4.0-6293-g0b4b230/2014-06-25T23:32:28Z/seabios_revision.txt seabios_revision.txt]
)


= 2014W13 =
||
<span id="jetway/nf81-t56n-lf"></span>
|- bgcolor="#eeeeee"
[[Board:jetway/nf81-t56n-lf|jetway/nf81-t56n-lf]] at Sat Mar 29 03:40:24 UTC 2014
| GENERIC_GPIO_LIB || toplevel || bool ||  ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=fccfee3bce901dfe78af8c36656f09973c2f3846 upstream tree] (
If enabled, compile the generic GPIO library. A "generic" GPIO
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/jetway/nf81-t56n-lf/4.0-5682-gfccfee3-dirty/2014-03-29T03:40:24Z/config.txt config.txt]
implies configurability usually found on SoCs, particularly the
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/jetway/nf81-t56n-lf/4.0-5682-gfccfee3-dirty/2014-03-29T03:40:24Z/coreboot_console.txt coreboot_console.txt]
ability to control internal pull resistors.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/jetway/nf81-t56n-lf/4.0-5682-gfccfee3-dirty/2014-03-29T03:40:24Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/jetway/nf81-t56n-lf/4.0-5682-gfccfee3-dirty/2014-03-29T03:40:24Z/kernel_log.txt kernel_log.txt]
)


<span id="google/butterfly"></span>
||
[[Board:google/butterfly|google/butterfly]] at Fri Mar 28 20:20:38 UTC 2014
|- bgcolor="#eeeeee"
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=fccfee3bce901dfe78af8c36656f09973c2f3846 upstream tree] (
| GENERIC_SPD_BIN || toplevel || bool ||  ||
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/butterfly/4.0-5682-gfccfee3-dirty/2014-03-28T20:20:38Z/config.txt config.txt]
If enabled, add support for adding spd.hex files in cbfs as spd.bin
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/butterfly/4.0-5682-gfccfee3-dirty/2014-03-28T20:20:38Z/coreboot_console.txt coreboot_console.txt]
and locating it runtime to load SPD. Additionally provide provision to
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/butterfly/4.0-5682-gfccfee3-dirty/2014-03-28T20:20:38Z/coreboot_timestamps.txt coreboot_timestamps.txt]
fetch SPD over SMBus.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/google/butterfly/4.0-5682-gfccfee3-dirty/2014-03-28T20:20:38Z/kernel_log.txt kernel_log.txt]
)


= 2014W09 =
||
<span id="asus/a8n_e"></span>
|- bgcolor="#eeeeee"
[[Board:asus/a8n_e|asus/a8n_e]] at Tue Feb 25 19:03:49 UTC 2014
| DIMM_MAX || toplevel || int ||  ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=cf6c9cc29cedfd533da8cfaa8481560bce739097 upstream tree] (
Total number of memory DIMM slots available on motherboard.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/a8n_e/4.0-5562-gcf6c9cc/2014-02-25T19:03:49Z/config.txt config.txt]
It is multiplication of number of channel to number of DIMMs per
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/a8n_e/4.0-5562-gcf6c9cc/2014-02-25T19:03:49Z/coreboot_console.txt coreboot_console.txt]
channel
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/a8n_e/4.0-5562-gcf6c9cc/2014-02-25T19:03:49Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/a8n_e/4.0-5562-gcf6c9cc/2014-02-25T19:03:49Z/kernel_log.txt kernel_log.txt]
)


= 2014W04 =
||
<span id="samsung/stumpy"></span>
|- bgcolor="#eeeeee"
[[Board:samsung/stumpy|samsung/stumpy]] at Tue Jan 21 04:39:46 UTC 2014
| DIMM_SPD_SIZE || toplevel || int ||  ||
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=74230c32ced71c1c56691f95c82860096b63366d upstream tree] (
Total SPD size that will be used for DIMM.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/samsung/stumpy/4.0-5307-g74230c3-dirty/2014-01-21T04:39:46Z/config.txt config.txt]
Ex: DDR3 256, DDR4 512.
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/samsung/stumpy/4.0-5307-g74230c3-dirty/2014-01-21T04:39:46Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/samsung/stumpy/4.0-5307-g74230c3-dirty/2014-01-21T04:39:46Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/samsung/stumpy/4.0-5307-g74230c3-dirty/2014-01-21T04:39:46Z/kernel_log.txt kernel_log.txt]
)


= 2014W01 =
||
<span id="asus/a8v-e_se"></span>
|}
[[Board:asus/a8v-e_se|asus/a8v-e_se]] at Fri Jan  3 17:47:48 UTC 2014
[https://review.coreboot.org/gitweb/cgit/coreboot.git/commit/?id=812d624fd0384a5603c03a5055e9d0f7dd446dd4 upstream tree] (
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/a8v-e_se/4.0-5192-g812d624/2014-01-03T17:47:48Z/config.txt config.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/a8v-e_se/4.0-5192-g812d624/2014-01-03T17:47:48Z/coreboot_console.txt coreboot_console.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/a8v-e_se/4.0-5192-g812d624/2014-01-03T17:47:48Z/coreboot_timestamps.txt coreboot_timestamps.txt]
[https://review.coreboot.org/gitweb/cgit/board-status.git/tree/asus/a8v-e_se/4.0-5192-g812d624/2014-01-03T17:47:48Z/kernel_log.txt kernel_log.txt]
)

Revision as of 05:57, 19 May 2018

This is an automatically generated list of coreboot compile-time options.

Last update: 4.8-38-g8a25caee05

Option Source Format Short Description Description
Menu: General setup
LOCALVERSION toplevel string Local version string

Append an extra string to the end of the coreboot version.

This can be useful if, for instance, you want to append the respective board's hostname or some other identifying string to the coreboot version number, so that you can easily distinguish boot logs of different boards from each other.

CBFS_PREFIX toplevel string CBFS prefix to use

Select the prefix to all files put into the image. It's "fallback" by default, "normal" is a common alternative.

CBFS_PREFIX toplevel string Compiler to use

This option allows you to select the compiler used for building coreboot. You must build the coreboot crosscompiler for the board that you have selected.

To build all the GCC crosscompilers (takes a LONG time), run: make crossgcc

For help on individual architectures, run the command: make help_toolchain

COMPILER_GCC toplevel bool GCC

Use the GNU Compiler Collection (GCC) to build coreboot.

For details see http://gcc.gnu.org.

COMPILER_LLVM_CLANG toplevel bool LLVM/clang (TESTING ONLY - Not currently working)

Use LLVM/clang to build coreboot. To use this, you must build the coreboot version of the clang compiler. Run the command make clang Note that this option is not currently working correctly and should really only be selected if you're trying to work on getting clang operational.

For details see http://clang.llvm.org.

ANY_TOOLCHAIN toplevel bool Allow building with any toolchain

Many toolchains break when building coreboot since it uses quite unusual linker features. Unless developers explicitely request it, we'll have to assume that they use their distro compiler by mistake. Make sure that using patched compilers is a conscious decision.

CCACHE toplevel bool Use ccache to speed up (re)compilation

Enables the use of ccache for faster builds.

Requires the ccache utility in your system $PATH.

For details see https://ccache.samba.org.

FMD_GENPARSER toplevel bool Generate flashmap descriptor parser using flex and bison

Enable this option if you are working on the flashmap descriptor parser and made changes to fmd_scanner.l or fmd_parser.y.

Otherwise, say N to use the provided pregenerated scanner/parser.

UTIL_GENPARSER toplevel bool Generate SCONFIG & BINCFG parser using flex and bison

Enable this option if you are working on the sconfig device tree parser or bincfg and made changes to the .l or .y files.

Otherwise, say N to use the provided pregenerated scanner/parser.

USE_OPTION_TABLE toplevel bool Use CMOS for configuration values

Enable this option if coreboot shall read options from the "CMOS" NVRAM instead of using hard-coded values.

STATIC_OPTION_TABLE toplevel bool Load default configuration values into CMOS on each boot

Enable this option to reset "CMOS" NVRAM values to default on every boot. Use this if you want the NVRAM configuration to never be modified from its default values.

COMPRESS_RAMSTAGE toplevel bool Compress ramstage with LZMA

Compress ramstage to save memory in the flash image. Note that decompression might slow down booting if the boot flash is connected through a slow link (i.e. SPI).

COMPRESS_PRERAM_STAGES toplevel bool Compress romstage and verstage with LZ4

Compress romstage and (if it exists) verstage with LZ4 to save flash space and speed up boot, since the time for reading the image from SPI (and in the vboot case verifying it) is usually much greater than the time spent decompressing. Doesn't work for XIP stages (assume all ARCH_X86 for now) for obvious reasons.

INCLUDE_CONFIG_FILE toplevel bool Include the coreboot .config file into the ROM image

Include the .config file that was used to compile coreboot in the (CBFS) ROM image. This is useful if you want to know which options were used to build a specific coreboot.rom image.

Saying Y here will increase the image size by 2-3KB.

You can use the following command to easily list the options:

grep -a CONFIG_ coreboot.rom

Alternatively, you can also use cbfstool to print the image contents (including the raw 'config' item we're looking for).

Example:

$ cbfstool coreboot.rom print coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304, offset 0x0 Alignment: 64 bytes

Name Offset Type Size cmos_layout.bin 0x0 cmos layout 1159 fallback/romstage 0x4c0 stage 339756 fallback/ramstage 0x53440 stage 186664 fallback/payload 0x80dc0 payload 51526 config 0x8d740 raw 3324 (empty) 0x8e480 null 3610440

COLLECT_TIMESTAMPS toplevel bool Create a table of timestamps collected during boot

Make coreboot create a table of timer-ID/timer-value pairs to allow measuring time spent at different phases of the boot process.

TIMESTAMPS_ON_CONSOLE toplevel bool Print the timestamp values on the console

Print the timestamps to the debug console if enabled at level spew.

USE_BLOBS toplevel bool Allow use of binary-only repository

This draws in the blobs repository, which contains binary files that might be required for some chipsets or boards. This flag ensures that a "Free" option remains available for users.

COVERAGE toplevel bool Code coverage support

Add code coverage support for coreboot. This will store code coverage information in CBMEM for extraction from user space. If unsure, say N.

UBSAN toplevel bool Undefined behavior sanitizer support

Instrument the code with checks for undefined behavior. If unsure, say N because it adds a small performance penalty and may abort on code that happens to work in spite of the UB.

RELOCATABLE_RAMSTAGE toplevel bool Build the ramstage to be relocatable in 32-bit address space.

The reloctable ramstage support allows for the ramstage to be built as a relocatable module. The stage loader can identify a place out of the OS way so that copying memory is unnecessary during an S3 wake. When selecting this option the romstage is responsible for determing a stack location to use for loading the ramstage.

CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM toplevel bool

The relocated ramstage is saved in an area specified by the by the board and/or chipset.

UPDATE_IMAGE toplevel bool Update existing coreboot.rom image

If this option is enabled, no new coreboot.rom file is created. Instead it is expected that there already is a suitable file for further processing. The bootblock will not be modified.

If unsure, select 'N'

BOOTSPLASH_IMAGE toplevel bool Add a bootsplash image

Select this option if you have a bootsplash image that you would like to add to your ROM.

This will only add the image to the ROM. To actually run it check options under 'Display' section.

BOOTSPLASH_FILE toplevel string Bootsplash path and filename

The path and filename of the file to use as graphical bootsplash screen. The file format has to be jpg.

Menu: Mainboard
(comment) Important: Run 'make distclean' before switching boards
VENDOR_WINNET mainboard/winnet.name bool WinNET

WinNET boards. Used in various thin client appliances.

UART_FOR_CONSOLE mainboard/intel/mohonpeak int

The Mohon Peak board uses COM2 (2f8) for the serial console.

PAYLOAD_CONFIGFILE mainboard/intel/mohonpeak string

The Avoton/Rangeley chip does not allow devices to write into the 0xe000 segment. This means that USB/SATA devices will not work in SeaBIOS unless we put the SeaBIOS buffer area down in the 0x9000 segment.

ENABLE_FSP_MEMORY_DOWN mainboard/intel/harcuvar bool Enable Memory Down

Select this option to enable Memory Down function.

SPD_LOC mainboard/intel/harcuvar hex SPD binary location in cbfs

Location of SPD binary for memory down function.

VBOOT mainboard/intel/kblrvp None TPM to USE

This option allows you to select the TPM to use. Select whether the board does not have TPM, TPM 1.1 or TPM 2.0

UART_FOR_CONSOLE mainboard/intel/littleplains int

The Little Plains board uses COM2 (2f8) for the serial console.

PAYLOAD_CONFIGFILE mainboard/intel/littleplains string

The Avoton/Rangeley chip does not allow devices to write into the 0xe000 segment. This means that USB/SATA devices will not work in SeaBIOS unless we put the SeaBIOS buffer area down in the 0x9000 segment.

GALILEO_GEN2 mainboard/intel/galileo bool Board generation: GEN1 (n) or GEN2 (y)

The coreboot binary will configure only one generation of the Galileo board since coreboot can not determine the board generation at runtime. Select which generation of the Galileo that coreboot should initialize.

FSP_VERSION_1_1 mainboard/intel/galileo bool FSP 1.1

Use FSP 1_1 binary

FSP_VERSION_2_0 mainboard/intel/galileo bool FSP 2.0

Use FSP 2.0 binary

FSP_BUILD_TYPE_DEBUG mainboard/intel/galileo bool Debug

Use the debug version of FSP

FSP_BUILD_TYPE_RELEASE mainboard/intel/galileo bool Release

Use the release version of FSP

FSP_TYPE_1_1 mainboard/intel/galileo bool MemInit subroutine

FSP 1.1 implemented as subroutines, no EDK-II cores

FSP_TYPE_1_1_PEI mainboard/intel/galileo bool SEC + PEI Core + MemInit PEIM

FSP 1.1 implemented using SEC and PEI core

FSP_TYPE_2_0 mainboard/intel/galileo bool MemInit subroutine

FSP 2.0 implemented as subroutines, no EDK-II cores

FSP_TYPE_2_0_PEI mainboard/intel/galileo bool SEC + PEI Core + MemInit PEIM

FSP 2.0 implemented using SEC and PEI core

FSP_DEBUG_ALL mainboard/intel/galileo bool Enable all FSP debug support

Turn on debug support to display HOBS, MTRRS, SMM_MEMORY_MAP, UPD_DATA also turn on FSP 2.0 debug support for ESRAM_LAYOUT, FSP_CALLS_AND_STATUS, FSP_HEADER, POSTCAR_CONSOLE and VERIFY_HOBS or FSP 1.1 DISPLAY_FSP_ENTRY_POINTS

VBOOT_WITH_CRYPTO_SHIELD mainboard/intel/galileo bool Verified boot using the Crypto Shield board

Perform a verified boot using the TPM on the Crypto Shield board.

DRIVER_TPM_I2C_ADDR mainboard/intel/galileo hex Address of the I2C TPM chip

I2C address of the TPM chip on the Crypto Shield board.

FMDFILE mainboard/intel/galileo string FMAP description file in fmd format

The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE, but in some cases more complex setups are required.

When an FMD descriptionn file is specified, the build system uses it instead of creating a default FMAP file.

BASEBOARD_GLKRVP_LAPTOP mainboard/intel/glkrvp None ON BOARD EC

This option allows you to select the on board EC to use. Select whether the board has Intel EC or Chrome EC

Menu: Debugging
DISABLE_UART_ON_TESTPADS mainboard/intel/dcp847ske bool Disable UART on testpads

Serial output requires soldering to the testpad next to NCT5577D pin 18 (txd) and gnd.

VGA_BIOS_FILE mainboard/intel/strago string

The C0 version of the video bios gets computed from this name so that they can both be added. Only the correct one for the system will be run.

VGA_BIOS_ID mainboard/intel/strago string

The VGA_BIOS_ID for the C0 version of the video bios is hardcoded in soc/intel/braswell/Makefile.inc as 8086,22b1

BOARD_EMULATION_SPIKE_UCB_RISCV mainboard/emulation/spike-riscv.name bool SPIKE ucb riscv

To run coreboot in spike:

  • run "make" as usual
  • util/riscv/make-spike-elf.sh build/coreboot.{rom,elf}
  • spike -m1024 build/coreboot.elf
HUDSON_LEGACY_FREE mainboard/bap/ode_e21XX bool Select DDR3 clock

Select your preferenced DDR3 clock setting.

Note: This option changes the total power consumption.

If unsure, use DDR3-1333.

HUDSON_LEGACY_FREE mainboard/bap/ode_e20XX bool Select DDR3 clock

Select your preferred DDR3 clock setting.

Note: This option changes the total power consumption.

If unsure, use DDR3-1066.

ENABLE_DP3_DAUGHTER_CARD_IN_J120 mainboard/amd/lamar bool Use J120 as an additional graphics port

The PCI Express slot at J120 can be configured as an additional DisplayPort connector using an adapter card from AMD or as a normal PCI Express (x4) slot.

By default, the connector is configured as a PCI Express (x4) slot.

Select this option to enable the slot for use with one of AMD's passive graphics port expander cards (only available from AMD).

(comment) Slippy
(comment) Octopus
(comment) Auron
(comment) Gru
(comment) Cyan
(comment) Reef
(comment) Jecht
(comment) Beltino
(comment) Rambi
(comment) Kahlee
(comment) Poppy
(comment) Zoombini
(comment) Veyron
(comment) Oak
MAINBOARD_PART_NUMBER mainboard/google/nyan_blaze string BCT boot media

Which boot media to configure the BCT for.

NYAN_BLAZE_BCT_CFG_SPI mainboard/google/nyan_blaze bool SPI

Configure the BCT for booting from SPI.

NYAN_BLAZE_BCT_CFG_EMMC mainboard/google/nyan_blaze bool eMMC

Configure the BCT for booting from eMMC.

BOOT_DEVICE_SPI_FLASH_BUS mainboard/google/nyan_blaze int SPI bus with boot media ROM

Which SPI bus the boot media is connected to.

DISPLAY_SPD_DATA mainboard/google/cyan bool Display Memory Serial Presence Detect Data

When enabled displays the memory configuration data.

VGA_BIOS_FILE mainboard/google/cyan string

The C0 version of the video bios gets computed from this name so that they can both be added. Only the correct one for the system will be run.

VGA_BIOS_ID mainboard/google/cyan string

The VGA_BIOS_ID for the C0 version of the video bios is hardcoded in soc/intel/braswell/Makefile.inc as 8086,22b1

FMDFILE mainboard/google/kahlee string

The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE, but in some cases more complex setups are required. When an fmd is specified, it overrides the default format.

DRAM_SIZE_MB mainboard/google/smaug int BCT boot media

Which boot media to configure the BCT for.

SMAUG_BCT_CFG_SPI mainboard/google/smaug bool SPI

Configure the BCT for booting from SPI.

SMAUG_BCT_CFG_EMMC mainboard/google/smaug bool eMMC

Configure the BCT for booting from eMMC.

BOOT_DEVICE_SPI_FLASH_BUS mainboard/google/smaug int SPI bus with boot media ROM

Which SPI bus the boot media is connected to.

MAINBOARD_PART_NUMBER mainboard/google/nyan_big string BCT boot media

Which boot media to configure the BCT for.

NYAN_BIG_BCT_CFG_SPI mainboard/google/nyan_big bool SPI

Configure the BCT for booting from SPI.

NYAN_BIG_BCT_CFG_EMMC mainboard/google/nyan_big bool eMMC

Configure the BCT for booting from eMMC.

BOOT_DEVICE_SPI_FLASH_BUS mainboard/google/nyan_big int SPI bus with boot media ROM

Which SPI bus the boot media is connected to.

DRAM_SIZE_MB mainboard/google/foster int BCT boot media

Which boot media to configure the BCT for.

FOSTER_BCT_CFG_SPI mainboard/google/foster bool SPI

Configure the BCT for booting from SPI.

FOSTER_BCT_CFG_EMMC mainboard/google/foster bool eMMC

Configure the BCT for booting from eMMC.

BOOT_DEVICE_SPI_FLASH_BUS mainboard/google/foster int SPI bus with boot media ROM

Which SPI bus the boot media is connected to.

MAINBOARD_PART_NUMBER mainboard/google/nyan string BCT boot media

Which boot media to configure the BCT for.

NYAN_BCT_CFG_SPI mainboard/google/nyan bool SPI

Configure the BCT for booting from SPI.

NYAN_BCT_CFG_EMMC mainboard/google/nyan bool eMMC

Configure the BCT for booting from eMMC.

BOOT_DEVICE_SPI_FLASH_BUS mainboard/google/nyan int SPI bus with boot media ROM

Which SPI bus the boot media is connected to.

UART_FOR_CONSOLE mainboard/adi/rcc-dff int

The Mohon Peak board uses COM2 (2f8) for the serial console.

PAYLOAD_CONFIGFILE mainboard/adi/rcc-dff string

The Avoton/Rangeley chip does not allow devices to write into the 0xe000 segment. This means that USB/SATA devices will not work in SeaBIOS unless we put the SeaBIOS buffer area down in the 0x9000 segment.

BOARD_ASUS_F2A85_M_DDR3_VOLT_135 mainboard/asus/f2a85-m bool 1.35V

Set DRR3 memory voltage to 1.35V

BOARD_ASUS_F2A85_M_DDR3_VOLT_150 mainboard/asus/f2a85-m bool 1.50V

Set DRR3 memory voltage to 1.50V

BOARD_ASUS_F2A85_M_DDR3_VOLT_165 mainboard/asus/f2a85-m bool 1.65V

Set DRR3 memory voltage to 1.65V

BOARD_WINNET_G170 mainboard/winnet/g170.name bool WinNET G170 (Neoware CA19, IGEL 2110)

G170 is a board manufactured by WinNET, used in thin clients including HP Neoware CA19 and IGEL 2110.

BMC_INFO_LOC mainboard/scaleway/tagada hex BMC information location in flash

Location of BMC SERIAL information.

NO_POST mainboard/purism/librem_skl int

This platform does not have any way to see POST codes so disable them by default.

DRIVERS_PS2_KEYBOARD mainboard/purism/librem_bdw string

Default PS/2 Keyboard to enabled on this board.

DRIVERS_UART_8250IO mainboard/purism/librem_bdw string

This platform does not have any way to get standard serial output so disable it by default.

NO_POST mainboard/purism/librem_bdw int

This platform does not have any way to see POST codes so disable them by default.

(comment) was acquired by ADLINK
ONBOARD_UARTS_RS485 mainboard/lippert/spacerunner-lx bool Switch on-board serial ports to RS485

If selected, both on-board serial ports will operate in RS485 mode instead of RS232.

ONBOARD_IDE_SLAVE mainboard/lippert/spacerunner-lx bool Make on-board SSD act as Slave

If selected, the on-board SSD will act as IDE Slave instead of Master.

BOARD_OLD_REVISION mainboard/lippert/hurricane-lx bool Board is old pre-3.0 revision

Look on the bottom side for a number like 406-0001-30. The last 2 digits state the PCB revision (3.0 in this example). For 2.0 or older boards choose Y, for 3.0 and newer say N.

Old revision boards need a jumper shorting the power button to power on automatically. You may enable the button only after this jumper has been removed. New revision boards are not restricted in this way, and always have the power button enabled.

ONBOARD_UARTS_RS485 mainboard/lippert/hurricane-lx bool Switch on-board serial ports to RS485

If selected, both on-board serial ports will operate in RS485 mode instead of RS232.

ONBOARD_UARTS_RS485 mainboard/lippert/literunner-lx bool Switch on-board serial ports 1 & 2 to RS485

If selected, the first two on-board serial ports will operate in RS485 mode instead of RS232.

ONBOARD_IDE_SLAVE mainboard/lippert/literunner-lx bool Make on-board CF socket act as Slave

If selected, the on-board Compact Flash card socket will act as IDE Slave instead of Master.

ONBOARD_UARTS_RS485 mainboard/lippert/roadrunner-lx bool Switch on-board serial ports to RS485

If selected, both on-board serial ports will operate in RS485 mode instead of RS232.

(comment) see under vendor LiPPERT
(comment) WARNING: This mainboard uses LATE_CBMEM_INIT, which is deprecated
BOARD_ROMSIZE_KB_65536 mainboard bool ROM chip size

Select the size of the ROM chip you intend to flash coreboot on.

The build system will take care of creating a coreboot.rom file of the matching size.

COREBOOT_ROMSIZE_KB_64 mainboard bool 64 KB

Choose this option if you have a 64 KB ROM chip.

COREBOOT_ROMSIZE_KB_128 mainboard bool 128 KB

Choose this option if you have a 128 KB ROM chip.

COREBOOT_ROMSIZE_KB_256 mainboard bool 256 KB

Choose this option if you have a 256 KB ROM chip.

COREBOOT_ROMSIZE_KB_512 mainboard bool 512 KB

Choose this option if you have a 512 KB ROM chip.

COREBOOT_ROMSIZE_KB_1024 mainboard bool 1024 KB (1 MB)

Choose this option if you have a 1024 KB (1 MB) ROM chip.

COREBOOT_ROMSIZE_KB_2048 mainboard bool 2048 KB (2 MB)

Choose this option if you have a 2048 KB (2 MB) ROM chip.

COREBOOT_ROMSIZE_KB_4096 mainboard bool 4096 KB (4 MB)

Choose this option if you have a 4096 KB (4 MB) ROM chip.

COREBOOT_ROMSIZE_KB_8192 mainboard bool 8192 KB (8 MB)

Choose this option if you have a 8192 KB (8 MB) ROM chip.

COREBOOT_ROMSIZE_KB_10240 mainboard bool 10240 KB (10 MB)

Choose this option if you have a 10240 KB (10 MB) ROM chip.

COREBOOT_ROMSIZE_KB_12288 mainboard bool 12288 KB (12 MB)

Choose this option if you have a 12288 KB (12 MB) ROM chip.

COREBOOT_ROMSIZE_KB_16384 mainboard bool 16384 KB (16 MB)

Choose this option if you have a 16384 KB (16 MB) ROM chip.

COREBOOT_ROMSIZE_KB_32768 mainboard bool 32768 KB (32 MB)

Choose this option if you have a 32768 KB (32 MB) ROM chip.

COREBOOT_ROMSIZE_KB_65536 mainboard bool 65536 KB (64 MB)

Choose this option if you have a 65536 KB (64 MB) ROM chip.

ENABLE_POWER_BUTTON mainboard bool Enable the power button

The selected mainboard can optionally have the power button tied to ground with a jumper so that the button appears to be constantly depressed. If this option is enabled and the jumper is installed then the board will turn on, but turn off again after a short timeout, usually 4 seconds.

Select Y here if you have removed the jumper and want to use an actual power button. Select N if you have the jumper installed.

DEVICETREE toplevel string

This symbol allows mainboards to select a different file under their mainboard directory for the devicetree.cb file. This allows the board variants that need different devicetrees to be in the same directory.

Examples: "devicetree.variant.cb" "variant/devicetree.cb"

CBFS_SIZE toplevel hex Size of CBFS filesystem in ROM

This is the part of the ROM actually managed by CBFS, located at the end of the ROM (passed through cbfstool -o) on x86 and at at the start of the ROM (passed through cbfstool -s) everywhere else. It defaults to span the whole ROM on all but Intel systems that use an Intel Firmware Descriptor. It can be overridden to make coreboot live alongside other components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE binaries.

FMDFILE toplevel string fmap description file in fmd format

The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE, but in some cases more complex setups are required. When an fmd is specified, it overrides the default format.

CBFS_AUTOGEN_ATTRIBUTES toplevel bool

If this option is selected, every file in cbfs which has a constraint regarding position or alignment will get an additional file attribute which describes this constraint.

Menu: Chipset
(comment) SoC
MAINBOARD_DO_DSI_INIT soc/nvidia/tegra210 bool Use dsi graphics interface

Initialize dsi display

MAINBOARD_DO_SOR_INIT soc/nvidia/tegra210 bool Use dp graphics interface

Initialize dp display

CONSOLE_SERIAL_TEGRA210_UARTA soc/nvidia/tegra210 bool UARTA

Serial console on UART A.

CONSOLE_SERIAL_TEGRA210_UARTB soc/nvidia/tegra210 bool UARTB

Serial console on UART B.

CONSOLE_SERIAL_TEGRA210_UARTC soc/nvidia/tegra210 bool UARTC

Serial console on UART C.

CONSOLE_SERIAL_TEGRA210_UARTD soc/nvidia/tegra210 bool UARTD

Serial console on UART D.

CONSOLE_SERIAL_TEGRA210_UARTE soc/nvidia/tegra210 bool UARTE

Serial console on UART E.

CONSOLE_SERIAL_TEGRA210_UART_ADDRESS soc/nvidia/tegra210 hex

Map the UART names to the respective MMIO addres.

BOOTROM_SDRAM_INIT soc/nvidia/tegra210 bool SoC BootROM does SDRAM init with full BCT

Use during Foster LPDDR4 bringup.

TRUSTZONE_CARVEOUT_SIZE_MB soc/nvidia/tegra210 hex Size of Trust Zone region

Size of Trust Zone area in MiB to reserve in memory map.

TTB_SIZE_MB soc/nvidia/tegra210 hex Size of TTB

Maximum size of Translation Table Buffer in MiB.

SEC_COMPONENT_SIZE_MB soc/nvidia/tegra210 hex Size of resident EL3 components

Maximum size of resident EL3 components in MiB including BL31 and Secure OS.

HAVE_MTC soc/nvidia/tegra210 bool Add external Memory controller Training Code binary

Select this option to add emc training firmware

MTC_FILE soc/nvidia/tegra210 string tegra mtc firmware filename

The filename of the mtc firmware

MTC_DIRECTORY soc/nvidia/tegra210 string Directory where MTC firmware file is located

Path to directory where MTC firmware file is located.

MTC_ADDRESS soc/nvidia/tegra210 hex

The DRAM location where MTC firmware to be loaded in. This location needs to be consistent with the location defined in tegra_mtc.ld

SOC_INTEL_APOLLOLAKE soc/intel/apollolake bool

Intel Apollolake support

SOC_INTEL_GLK soc/intel/apollolake bool

Intel GLK support

TPM_ON_FAST_SPI soc/intel/apollolake bool

TPM part is conntected on Fast SPI interface, but the LPC MMIO TPM transactions are decoded and serialized over the SPI interface.

PCR_BASE_ADDRESS soc/intel/apollolake hex

This option allows you to select MMIO Base Address of sideband bus.

DCACHE_RAM_SIZE soc/intel/apollolake hex

The size of the cache-as-ram region required during bootblock and/or romstage.

DCACHE_BSP_STACK_SIZE soc/intel/apollolake hex

The amount of anticipated stack usage in CAR by bootblock and other stages.

ROMSTAGE_ADDR soc/intel/apollolake hex

The base address (in CAR) where romstage should be linked

VERSTAGE_ADDR soc/intel/apollolake hex

The base address (in CAR) where verstage should be linked

FSP_M_ADDR soc/intel/apollolake hex

The address FSP-M will be relocated to during build time

NEED_LBP2 soc/intel/apollolake bool Write contents for logical boot partition 2.

Write the contents from a file into the logical boot partition 2 region defined by LBP2_FMAP_NAME.

LBP2_FMAP_NAME soc/intel/apollolake string Name of FMAP region to put logical boot partition 2

Name of FMAP region to write logical boot partition 2 data.

LBP2_FILE_NAME soc/intel/apollolake string Path of file to write to logical boot partition 2 region

Name of file to store in the logical boot partition 2 region.

NEED_IFWI soc/intel/apollolake bool Write content into IFWI region

Write the content from a file into IFWI region defined by IFWI_FMAP_NAME.

IFWI_FMAP_NAME soc/intel/apollolake string Name of FMAP region to pull IFWI into

Name of FMAP region to write IFWI.

IFWI_FILE_NAME soc/intel/apollolake string Path of file to write to IFWI region

Name of file to store in the IFWI region.

NHLT_DMIC_1CH_16B soc/intel/apollolake bool

Include DSP firmware settings for 1 channel 16B DMIC array.

NHLT_DMIC_2CH_16B soc/intel/apollolake bool

Include DSP firmware settings for 2 channel 16B DMIC array.

NHLT_DMIC_4CH_16B soc/intel/apollolake bool

Include DSP firmware settings for 4 channel 16B DMIC array.

NHLT_MAX98357 soc/intel/apollolake bool

Include DSP firmware settings for headset codec.

NHLT_DA7219 soc/intel/apollolake bool

Include DSP firmware settings for headset codec.

NHLT_RT5682 soc/intel/apollolake bool

Include DSP firmware settings for headset codec.

NHLT_RT5682 soc/intel/apollolake bool Cache-as-ram implementation

This option allows you to select how cache-as-ram (CAR) is set up.

CAR_NEM soc/intel/apollolake bool Non-evict mode

Traditionally, CAR is set up by using Non-Evict mode. This method does not allow CAR and cache to co-exist, because cache fills are block in NEM mode.

CAR_CQOS soc/intel/apollolake bool Cache Quality of Service

Cache Quality of Service allows more fine-grained control of cache usage. As result, it is possible to set up portion of L2 cache for CAR and use remainder for actual caching.

USE_APOLLOLAKE_FSP_CAR soc/intel/apollolake bool Use FSP CAR

Use FSP APIs to initialize & tear down the Cache-As-Ram.

APL_SKIP_SET_POWER_LIMITS soc/intel/apollolake bool

Some Apollo Lake mainboards do not need the Running Average Power Limits (RAPL) algorithm for a constant power management. Set this config option to skip the RAPL configuration.

SOC_ESPI soc/intel/apollolake bool

Use eSPI bus instead of LPC

SOC_INTEL_BAYTRAIL soc/intel/baytrail bool

Bay Trail M/D part support.

HAVE_MRC soc/intel/baytrail bool Add a Memory Reference Code binary

Select this option to add a blob containing memory reference code. Note: Without this binary coreboot will not work

MRC_FILE soc/intel/baytrail string Intel memory refeference code path and filename

The path and filename of the file to use as System Agent binary. Note that this points to the sandybridge binary file which is will not work, but it serves its purpose to do builds.

DCACHE_RAM_SIZE soc/intel/baytrail hex

The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2.

DCACHE_RAM_MRC_VAR_SIZE soc/intel/baytrail hex

The amount of cache-as-ram region required by the reference code.

RESET_ON_INVALID_RAMSTAGE_CACHE soc/intel/baytrail bool Reset the system on S3 wake when ramstage cache invalid.

The baytrail romstage code caches the loaded ramstage program in SMM space. On S3 wake the romstage will copy over a fresh ramstage that was cached in the SMM space. This option determines the action to take when the ramstage cache is invalid. If selected the system will reset otherwise the ramstage will be reloaded from cbfs.

ENABLE_BUILTIN_COM1 soc/intel/baytrail bool Enable builtin COM1 Serial Port

The PMC has a legacy COM1 serial port. Choose this option to configure the pads and enable it. This serial port can be used for the debug console.

HAVE_REFCODE_BLOB soc/intel/baytrail bool An external reference code blob should be put into cbfs.

The reference code blob will be placed into cbfs.

REFCODE_BLOB_FILE soc/intel/baytrail string Path and filename to reference code blob.

The path and filename to the file to be added to cbfs.

SOC_INTEL_BRASWELL soc/intel/braswell bool

Braswell M/D part support.

DCACHE_RAM_SIZE soc/intel/braswell hex

The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2.

RESET_ON_INVALID_RAMSTAGE_CACHE soc/intel/braswell bool Reset the system on S3 wake when ramstage cache invalid.

The haswell romstage code caches the loaded ramstage program in SMM space. On S3 wake the romstage will copy over a fresh ramstage that was cached in the SMM space. This option determines the action to take when the ramstage cache is invalid. If selected the system will reset otherwise the ramstage will be reloaded from cbfs.

ENABLE_BUILTIN_COM1 soc/intel/braswell bool Enable builtin COM1 Serial Port

The PMC has a legacy COM1 serial port. Choose this option to configure the pads and enable it. This serial port can be used for the debug console.

SOC_INTEL_BROADWELL soc/intel/broadwell bool

Intel Broadwell and Haswell ULT support.

DCACHE_RAM_SIZE soc/intel/broadwell hex

The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2.

DCACHE_RAM_MRC_VAR_SIZE soc/intel/broadwell hex

The amount of cache-as-ram region required by the reference code.

HAVE_MRC soc/intel/broadwell bool Add a Memory Reference Code binary

Select this option to add a Memory Reference Code binary to the resulting coreboot image.

Note: Without this binary coreboot will not work

MRC_FILE soc/intel/broadwell string Intel Memory Reference Code path and filename

The filename of the file to use as Memory Reference Code binary.

PRE_GRAPHICS_DELAY soc/intel/broadwell int Graphics initialization delay in ms

On some systems, coreboot boots so fast that connected monitors (mostly TVs) won't be able to wake up fast enough to talk to the VBIOS. On those systems we need to wait for a bit before executing the VBIOS.

RESET_ON_INVALID_RAMSTAGE_CACHE soc/intel/broadwell bool Reset the system on S3 wake when ramstage cache invalid.

The romstage code caches the loaded ramstage program in SMM space. On S3 wake the romstage will copy over a fresh ramstage that was cached in the SMM space. This option determines the action to take when the ramstage cache is invalid. If selected the system will reset otherwise the ramstage will be reloaded from cbfs.

SERIRQ_CONTINUOUS_MODE soc/intel/broadwell bool

If you set this option to y, the serial IRQ machine will be operated in continuous mode.

HAVE_REFCODE_BLOB soc/intel/broadwell bool An external reference code blob should be put into cbfs.

The reference code blob will be placed into cbfs.

REFCODE_BLOB_FILE soc/intel/broadwell string Path and filename to reference code blob.

The path and filename to the file to be added to cbfs.

SOC_INTEL_CANNONLAKE soc/intel/cannonlake bool

Intel Cannonlake support

UART_FOR_CONSOLE soc/intel/cannonlake int Index for LPSS UART port to use for console

Index for LPSS UART port to use for console: 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2

DCACHE_RAM_SIZE soc/intel/cannonlake int

The size of the cache-as-ram region required during bootblock and/or romstage.

DCACHE_BSP_STACK_SIZE soc/intel/cannonlake hex

The amount of anticipated stack usage in CAR by bootblock and other stages.

NHLT_DMIC_1CH_16B soc/intel/cannonlake bool

Include DSP firmware settings for 1 channel 16B DMIC array.

NHLT_DMIC_2CH_16B soc/intel/cannonlake bool

Include DSP firmware settings for 2 channel 16B DMIC array.

NHLT_DMIC_4CH_16B soc/intel/cannonlake bool

Include DSP firmware settings for 4 channel 16B DMIC array.

NHLT_MAX98357 soc/intel/cannonlake bool

Include DSP firmware settings for headset codec.

NHLT_MAX98373 soc/intel/cannonlake bool

Include DSP firmware settings for headset codec.

NHLT_DA7219 soc/intel/cannonlake bool

Include DSP firmware settings for headset codec.

PCR_BASE_ADDRESS soc/intel/cannonlake hex

This option allows you to select MMIO Base Address of sideband bus.

STACK_SIZE soc/intel/cannonlake hex Cache-as-ram implementation

This option allows you to select how cache-as-ram (CAR) is set up.

USE_CANNONLAKE_CAR_NEM_ENHANCED soc/intel/cannonlake bool Enhanced Non-evict mode

A current limitation of NEM (Non-Evict mode) is that code and data sizes are derived from the requirement to not write out any modified cache line. With NEM, if there is no physical memory behind the cached area, the modified data will be lost and NEM results will be inconsistent. ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced.

USE_CANNONLAKE_FSP_CAR soc/intel/cannonlake bool Use FSP CAR

Use FSP APIs to initialize and tear down the Cache-As-Ram.

SOC_INTEL_DENVERTON_NS soc/intel/denverton_ns bool

Intel Denverton-NS SoC support

FSP_T_ADDR soc/intel/denverton_ns hex Intel FSP-T (temp ram init) binary location

The memory location of the Intel FSP-T binary for this platform.

FSP_M_ADDR soc/intel/denverton_ns hex Intel FSP-M (memory init) binary location

The memory location of the Intel FSP-M binary for this platform.

FSP_S_ADDR soc/intel/denverton_ns hex Intel FSP-S (silicon init) binary location

The memory location of the Intel FSP-S binary for this platform.

PCR_BASE_ADDRESS soc/intel/denverton_ns hex

This option allows you to select MMIO Base Address of sideband bus.

IQAT_MEMORY_REGION_SIZE soc/intel/denverton_ns hex

Do not change this value

NON_LEGACY_UART_MODE soc/intel/denverton_ns bool Non Legacy Mode

Disable legacy UART mode

LEGACY_UART_MODE soc/intel/denverton_ns bool Legacy Mode

Enable legacy UART mode

DENVERTON_NS_CAR_NEM_ENHANCED soc/intel/denverton_ns bool Enhanced Non-evict mode

A current limitation of NEM (Non-Evict mode) is that code and data sizes are derived from the requirement to not write out any modified cache line. With NEM, if there is no physical memory behind the cached area, the modified data will be lost and NEM results will be inconsistent. ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced.

SOC_INTEL_FSP_BAYTRAIL soc/intel/fsp_baytrail bool

Bay Trail I part support using the Intel FSP.

SMM_TSEG_SIZE soc/intel/fsp_baytrail hex

This is set by the FSP

VGA_BIOS_ID soc/intel/fsp_baytrail string

This is the default PCI ID for the Bay Trail graphics devices. This string names the vbios ROM in cbfs.

ENABLE_BUILTIN_COM1 soc/intel/fsp_baytrail bool Enable built-in legacy Serial Port

The Baytrail SOC has one legacy serial port. Choose this option to configure the pads and enable it. This serial port can be used for the debug console.

FSP_FILE soc/intel/fsp_baytrail/fsp string

The path and filename of the Intel FSP binary for this platform.

FSP_LOC soc/intel/fsp_baytrail/fsp hex

The location in CBFS that the FSP is located. This must match the value that is set in the FSP binary. If the FSP needs to be moved, rebase the FSP with Intel's BCT (tool).

The Bay Trail FSP is built with a preferred base address of 0xFFFC0000.

SOC_INTEL_FSP_BROADWELL_DE soc/intel/fsp_broadwell_de bool

Broadwell-DE support using the Intel FSP.

INTEGRATED_UART soc/intel/fsp_broadwell_de bool Integrated UART ports

Use Broadwell-DE Integrated UART ports @3F8h and 2F8h.

SERIRQ_CONTINUOUS_MODE soc/intel/fsp_broadwell_de bool

If you set this option to y, the serial IRQ machine will be operated in continuous mode.

FSP_FILE soc/intel/fsp_broadwell_de/fsp string

The path and filename of the Intel FSP binary for this platform.

FSP_LOC soc/intel/fsp_broadwell_de/fsp hex

The location in CBFS that the FSP is located. This must match the value that is set in the FSP binary. If the FSP needs to be moved, rebase the FSP with Intel's BCT (tool).

The Broadwell-DE FSP is built with a preferred base address of 0xffeb0000.

DCACHE_RAM_BASE soc/intel/fsp_broadwell_de/fsp hex

This address needs to match the setup performed inside FSP. On Broadwell-DE the FSP allocates temporary RAM starting at 0xfe100000.

DCACHE_RAM_SIZE soc/intel/fsp_broadwell_de/fsp hex

The DCACHE is shared between FSP itself and the rest of the coreboot stages. A size of 0x8000 works fine while providing enough space for features like VBOOT in verstage. Further increase to a power of two aligned value leads to errors in FSP.

FSP_MEMORY_DOWN soc/intel/fsp_broadwell_de/fsp bool Enable Memory Down

Load SPD data from ROM instead of trying to read from SMBus.

If the platform has DIMM sockets, say N. If memory is down, say Y and supply the appropriate SPD data for each Channel/DIMM.

FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT soc/intel/fsp_broadwell_de/fsp bool Channel 0, DIMM 0 Present

Select Y if Channel 0, DIMM 0 is present.

FSP_MEMORY_DOWN_CH0DIMM0_SPD_FILE soc/intel/fsp_broadwell_de/fsp string Channel 0, DIMM 0 SPD File

Path to the file which contains the SPD data for Channel 0, DIMM 0.

FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT soc/intel/fsp_broadwell_de/fsp bool Channel 0, DIMM 1 Present

Select Y if Channel 0, DIMM 1 is present.

FSP_MEMORY_DOWN_CH0DIMM1_SPD_FILE soc/intel/fsp_broadwell_de/fsp string Channel 0, DIMM 1 SPD File

Path to the file which contains the SPD data for Channel 0, DIMM 1.

FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT soc/intel/fsp_broadwell_de/fsp bool Channel 1, DIMM 0 Present

Select Y if Channel 1, DIMM 0 is present.

FSP_MEMORY_DOWN_CH1DIMM0_SPD_FILE soc/intel/fsp_broadwell_de/fsp string Channel 1, DIMM 0 SPD File

Path to the file which contains the SPD data for Channel 1, DIMM 0.

FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT soc/intel/fsp_broadwell_de/fsp bool Channel 1, DIMM 1 Present

Select Y if Channel 1, DIMM 1 is present.

FSP_MEMORY_DOWN_CH1DIMM1_SPD_FILE soc/intel/fsp_broadwell_de/fsp string Channel 1, DIMM 1 SPD File

Path to the file which contains the SPD data for Channel 1, DIMM 1.

FSP_HYPERTHREADING soc/intel/fsp_broadwell_de/fsp bool Enable Hyper-Threading

Enable Intel(r) Hyper-Threading Technology for the Broadwell-DE SoC.

FSP_EHCI1_ENABLE soc/intel/fsp_broadwell_de/fsp bool EHCI1 Enable

Enable EHCI controller 1

FSP_EHCI2_ENABLE soc/intel/fsp_broadwell_de/fsp bool EHCI2 Enable

Enable EHCI controller 2

SOC_INTEL_QUARK soc/intel/quark bool

Intel Quark support

ENABLE_BUILTIN_HSUART0 soc/intel/quark bool Enable built-in HSUART0

The Quark SoC has two HSUART. Choose this option to configure the pads and enable HSUART0, which can be used for the debug console.

ENABLE_BUILTIN_HSUART1 soc/intel/quark bool Enable built-in HSUART1

The Quark SoC has two HSUART. Choose this option to configure the pads and enable HSUART1, which can be used for the debug console.

TTYS0_BASE soc/intel/quark hex HSUART Base Address

Memory mapped MMIO of HSUART.

ENABLE_DEBUG_LED soc/intel/quark bool

Enable the use of the SD LED for early debugging before serial output is available. Setting this LED indicates that control has reached the desired check point.

ENABLE_DEBUG_LED_ESRAM soc/intel/quark bool SD LED indicates ESRAM initialized

Indicate that ESRAM has been successfully initialized. If the SD LED does not light then the ESRAM initialization needs to be debugged.

ENABLE_DEBUG_LED_FINDFSP soc/intel/quark bool SD LED indicates fsp.bin file was found

Indicate that fsp.bin was found. If the SD LED does not light then the code between ESRAM initialization through find_fsp needs to debugged. Start by verifying that the correct fsp.bin is in the image.

ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY soc/intel/quark bool SD LED indicates bootblock.c successfully entered

Indicate that bootblock_c_entry was entered. If the SD LED does not light then debug the code between ESRAM and bootblock_c_entry. For FSP 1.1, use ENABLE_DEBUG_LED_FINDFSP to split this code.

ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY soc/intel/quark bool SD LED indicates bootblock_soc_early_init successfully entered

Indicate that bootblock_soc_early_init was entered. If the SD LED does not light then debug the code in bootblock_main_with_timestamp.

ENABLE_DEBUG_LED_SOC_EARLY_INIT_EXIT soc/intel/quark bool SD LED indicates bootblock_soc_early_init successfully exited

Indicate that bootblock_soc_early_init exited. If the SD LED does not light then debug the scripts in bootblock_soc_early_init.

ENABLE_DEBUG_LED_SOC_INIT_ENTRY soc/intel/quark bool SD LED indicates bootblock_soc_init successfully entered

Indicate that bootblock_soc_init was entered. If the SD LED does not light then debug the code in bootblock_mainboard_early_init and console_init. If the SD LED does light but there is no serial then debug the serial port configuration and initialization.

DISPLAY_ESRAM_LAYOUT soc/intel/quark bool Display ESRAM layout

Select this option to display coreboot's use of ESRAM.

CBFS_SIZE soc/intel/quark hex

Specify the size of the coreboot file system in the read-only (recovery) portion of the flash part. On Quark systems the firmware image stores more than just coreboot, including: - The chipset microcode (RMU) binary file located at 0xFFF00000 - Intel Trusted Execution Engine firmware

ADD_FSP_RAW_BIN soc/intel/quark bool Add the Intel FSP binary to the flash image without relocation

Select this option to add an Intel FSP binary to the resulting coreboot image.

Note: Without this binary, coreboot builds relying on the FSP will not boot

FSP_FILE soc/intel/quark string Intel FSP binary path and filename

The path and filename of the Intel FSP binary for this platform.

FSP_LOC soc/intel/quark hex

The location in CBFS that the FSP is located. This must match the value that is set in the FSP binary. If the FSP needs to be moved, rebase the FSP with Intel's BCT (tool).

FSP_ESRAM_LOC soc/intel/quark hex

The location in ESRAM where a copy of the FSP binary is placed.

RELOCATE_FSP_INTO_DRAM soc/intel/quark bool Relocate FSP into DRAM

Relocate the FSP binary into DRAM before the call to SiliconInit.

ADD_RMU_FILE soc/intel/quark bool Should the RMU binary be added to the flash image?

The RMU file is required to get the chip out of reset.

RMU_FILE soc/intel/quark string

The path and filename of the Intel Quark RMU binary.

RMU_LOC soc/intel/quark hex

The location in CBFS that the RMU is located. It must match the strap-determined base address.

STORAGE_TEST soc/intel/quark bool Test SD/MMC/eMMC card or device access

Read block 0 from each parition of the storage device. User must also enable one or both of COMMONLIB_STORAGE_SD or COMMONLIB_STORAGE_MMC.

I2C_DEBUG soc/intel/quark bool Enable I2C debugging

Display the I2C segments and controller errors

SOC_INTEL_SKYLAKE soc/intel/skylake bool

Intel Skylake support

SOC_INTEL_KABYLAKE soc/intel/skylake bool

Intel Kabylake support

DCACHE_RAM_SIZE soc/intel/skylake hex

The size of the cache-as-ram region required during bootblock and/or romstage.

DCACHE_BSP_STACK_SIZE soc/intel/skylake hex

The amount of anticipated stack usage in CAR by bootblock and other stages.

EXCLUDE_NATIVE_SD_INTERFACE soc/intel/skylake bool

If you set this option to n, will not use native SD controller.

PCR_BASE_ADDRESS soc/intel/skylake hex

This option allows you to select MMIO Base Address of sideband bus.

SERIRQ_CONTINUOUS_MODE soc/intel/skylake bool

If you set this option to y, the serial IRQ machine will be operated in continuous mode.

UART_FOR_CONSOLE soc/intel/skylake int Index for LPSS UART port to use for console

Index for LPSS UART port to use for console: 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2

SKYLAKE_SOC_PCH_H soc/intel/skylake bool

Choose this option if you have a PCH-H chipset.

NHLT_DMIC_2CH soc/intel/skylake bool

Include DSP firmware settings for 2 channel DMIC array.

NHLT_DMIC_4CH soc/intel/skylake bool

Include DSP firmware settings for 4 channel DMIC array.

NHLT_NAU88L25 soc/intel/skylake bool

Include DSP firmware settings for nau88l25 headset codec.

NHLT_MAX98357 soc/intel/skylake bool

Include DSP firmware settings for max98357 amplifier.

NHLT_MAX98373 soc/intel/skylake bool

Include DSP firmware settings for max98373 amplifier.

NHLT_SSM4567 soc/intel/skylake bool

Include DSP firmware settings for ssm4567 smart amplifier.

NHLT_RT5514 soc/intel/skylake bool

Include DSP firmware settings for rt5514 DSP.

NHLT_RT5663 soc/intel/skylake bool

Include DSP firmware settings for rt5663 headset codec.

NHLT_MAX98927 soc/intel/skylake bool

Include DSP firmware settings for max98927 amplifier.

NHLT_DA7219 soc/intel/skylake bool

Include DSP firmware settings for DA7219 headset codec.

NHLT_DA7219 soc/intel/skylake bool Cache-as-ram implementation

This option allows you to select how cache-as-ram (CAR) is set up.

USE_SKYLAKE_CAR_NEM_ENHANCED soc/intel/skylake bool Enhanced Non-evict mode

A current limitation of NEM (Non-Evict mode) is that code and data sizes are derived from the requirement to not write out any modified cache line. With NEM, if there is no physical memory behind the cached area, the modified data will be lost and NEM results will be inconsistent. ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced.

USE_SKYLAKE_FSP_CAR soc/intel/skylake bool Use FSP CAR

Use FSP APIs to initialize and tear down the Cache-As-Ram.

SKIP_FSP_CAR soc/intel/skylake bool Skip cache as RAM setup in FSP

Skip Cache as RAM setup in FSP.

NO_FADT_8042 soc/intel/skylake bool

Choose this option if you want to disable 8042 Keyboard

SOC_INTEL_COMMON soc/intel/common bool

common code for Intel SOCs

(comment) Intel SoC Common Code
SOC_INTEL_COMMON_BLOCK soc/intel/common/block bool

SoC driver for intel common IP code

(comment) Intel SoC Common IP Code
SOC_INTEL_COMMON_BLOCK_TIMER soc/intel/common/block/timer bool

Intel Processor common TIMER support

SOC_INTEL_COMMON_BLOCK_XDCI soc/intel/common/block/xdci bool

Intel Processor common XDCI support

SOC_INTEL_COMMON_BLOCK_SCS soc/intel/common/block/scs bool

Intel Processor common storage and communication subsystem support

SOC_INTEL_COMMON_BLOCK_SATA soc/intel/common/block/sata bool

Intel Processor common SATA support

SOC_AHCI_PORT_IMPLEMENTED_INVERT soc/intel/common/block/sata bool

SATA PCI configuration space offset 0x92 Port implement register bit 0-2 represents respective SATA port enable status as in 0 = Disable; 1 = Enable. If this option is selected then port enable status will be inverted as in 0 = Enable; 1 = Disable.

SOC_INTEL_COMMON_BLOCK_LPC soc/intel/common/block/lpc bool

Use common LPC code for platform. Only soc specific code needs to be implemented as per requirement.

SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE soc/intel/common/block/lpc bool

By default COMA range to LPC is enable. COMB range to LPC is optional and should select based on platform dedicated selection.

SOC_INTEL_COMMON_BLOCK_SPI soc/intel/common/block/spi bool

Intel Processor common SPI support

SOC_INTEL_COMMON_BLOCK_P2SB soc/intel/common/block/p2sb bool

Intel Processor common P2SB driver

SOC_INTEL_COMMON_BLOCK_SMM soc/intel/common/block/smm bool

Intel Processor common SMM support

SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP soc/intel/common/block/smm bool

Intel Processor trap flag if it is supported

SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS soc/intel/common/block/smm int

Time in milliseconds that SLP_SMI for S5 waits for before enabling sleep. This is required to avoid any race between SLP_SMI and PWRBTN SMI.

SOC_INTEL_COMMON_BLOCK_SA soc/intel/common/block/systemagent bool

Intel Processor common System Agent support

SA_PCIEX_LENGTH soc/intel/common/block/systemagent hex

This option allows you to select length of PCIEX region.

SA_ENABLE_IMR soc/intel/common/block/systemagent bool

This option allows you to add the isolated memory ranges (IMRs).

SA_ENABLE_DPR soc/intel/common/block/systemagent bool

This option allows you to add the DMA Protected Range (DPR).

SOC_INTEL_COMMON_BLOCK_HDA soc/intel/common/block/hda bool

Intel Processor common High Definition Audio driver support

SOC_INTEL_COMMON_BLOCK_LPSS soc/intel/common/block/lpss bool

Intel Processor common LPSS support

SOC_INTEL_COMMON_BLOCK_FAST_SPI soc/intel/common/block/fast_spi bool

Intel Processor common FAST_SPI support

FAST_SPI_DISABLE_WRITE_STATUS soc/intel/common/block/fast_spi bool Disable write status SPI opcode

Disable the write status SPI opcode in Intel Fast SPI block.

SOC_INTEL_COMMON_BLOCK_UART soc/intel/common/block/uart bool

Intel Processor common UART support

SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_M_VAL soc/intel/common/block/uart hex

Clock m-divisor value for m/n divider

SOC_INTEL_COMMON_BLOCK_UART_LPSS_CLK_N_VAL soc/intel/common/block/uart hex

Clock m-divisor value for m/n divider

SOC_INTEL_COMMON_BLOCK_GSPI soc/intel/common/block/gspi bool

Intel Processor Common GSPI support

SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ soc/intel/common/block/gspi int

The input clock speed into the SPI controller IP block, in MHz. No default is set here as this is an SOC-specific value and must be provided by the SOC.

SOC_INTEL_COMMON_BLOCK_GSPI_MAX soc/intel/common/block/gspi int

Maximum number of GSPI controllers supported by the PCH. SoC must define this config if SOC_INTEL_COMMON_BLOCK_GSPI is selected.

SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 soc/intel/common/block/gspi bool

Intel Processor Common GSPI support with quirks to handle SPI_CS_CONTROL changes introduced in CNL.

SOC_INTEL_COMMON_BLOCK_XHCI soc/intel/common/block/xhci bool

Intel Processor common XHCI support

SOC_INTEL_COMMON_BLOCK_PCIE soc/intel/common/block/pcie bool

Intel Processor common PCIE support

PCIE_DEBUG_INFO soc/intel/common/block/pcie bool

Enable debug logs in PCIe module. Allows debug information on memory base and limit, prefetchable memory base and limit, prefetchable memory base upper 32 bits and prefetchable memory limit upper 32 bits.

SOC_INTEL_COMMON_BLOCK_PCR soc/intel/common/block/pcr bool

Intel Processor common Private configuration registers (PCR)

PCR_COMMON_IOSF_1_0 soc/intel/common/block/pcr bool

The mapping of addresses via the SBREG_BAR assumes the IOSF-SB agents are using 32-bit aligned accesses for their configuration registers. For IOSF versions greater than 1_0, IOSF-SB agents can use any access (8/16/32 bit aligned) for their configuration registers

SOC_INTEL_COMMON_BLOCK_ACPI soc/intel/common/block/acpi bool

Intel Processor common code for ACPI

SOC_INTEL_COMMON_BLOCK_RTC soc/intel/common/block/rtc bool

Intel Processor common RTC support

SOC_INTEL_COMMON_BLOCK_CPU soc/intel/common/block/cpu bool

This option selects Intel Common CPU Model support code which provides various CPU related APIs which are common between all Intel Processor families. Common CPU code is supported for SOCs starting from SKL,KBL,APL, and future.

SOC_INTEL_COMMON_BLOCK_CPU_MPINIT soc/intel/common/block/cpu bool

This option selects Intel Common CPU MP Init code. In this common MP Init mechanism, the MP Init is occurring before calling FSP Silicon Init. Hence, MP Init will be pulled to BS_DEV_INIT_CHIPS Entry. And on Exit of BS_DEV_INIT, it is ensured that all MTRRs are re-programmed based on the DRAM resource settings.

SOC_INTEL_COMMON_BLOCK_CAR soc/intel/common/block/cpu bool

This option allows you to select how cache-as-ram (CAR) is set up.

INTEL_CAR_NEM soc/intel/common/block/cpu bool

Traditionally, CAR is set up by using Non-Evict mode. This method does not allow CAR and cache to co-exist, because cache fills are blocked in NEM.

INTEL_CAR_CQOS soc/intel/common/block/cpu bool

Cache Quality of Service allows more fine-grained control of cache usage. As result, it is possible to set up a portion of L2 cache for CAR and use the remainder for actual caching.

INTEL_CAR_NEM_ENHANCED soc/intel/common/block/cpu bool

A current limitation of NEM (Non-Evict mode) is that code and data sizes are derived from the requirement to not write out any modified cache line. With NEM, if there is no physical memory behind the cached area, the modified data will be lost and NEM results will be inconsistent. ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced.

SOC_INTEL_COMMON_BLOCK_CSE soc/intel/common/block/cse bool

Driver for communication with Converged Security Engine (CSE) over Host Embedded Controller Interface (HECI)

SOC_INTEL_COMMON_BLOCK_EBDA soc/intel/common/block/ebda bool

Intel Processor common EBDA library support

SOC_INTEL_COMMON_BLOCK_PMC soc/intel/common/block/pmc bool

Intel Processor common code for Power Management controller(PMC) subsystem

POWER_STATE_OFF_AFTER_FAILURE soc/intel/common/block/pmc bool S5 Soft Off

Choose this option if you want to keep system into S5 after reapplying power after failure

POWER_STATE_ON_AFTER_FAILURE soc/intel/common/block/pmc bool S0 Full On

Choose this option if you want to keep system into S0 after reapplying power after failure

POWER_STATE_PREVIOUS_AFTER_FAILURE soc/intel/common/block/pmc bool Keep Previous State

Choose this option if you want to keep system into same power state as before failure even after reapplying power

PMC_INVALID_READ_AFTER_WRITE soc/intel/common/block/pmc bool

Enable this for PMC devices where a read back of ACPI BAR and IO access bit does not return the previously written value.

SOC_INTEL_COMMON_BLOCK_SMBUS soc/intel/common/block/smbus bool

Intel Processor common SMBus support

SOC_INTEL_COMMON_BLOCK_GPIO soc/intel/common/block/gpio bool

Intel Processor common GPIO support

DEBUG_SOC_COMMON_BLOCK_GPIO soc/intel/common/block/gpio bool Output verbose GPIO debug messages

This option enables GPIO debug messages

SOC_INTEL_COMMON_BLOCK_SGX soc/intel/common/block/sgx bool

Software Guard eXtension(SGX) Feature. Intel SGX is a set of new CPU instructions that can be used by applications to set aside private regions of code and data.

SOC_INTEL_COMMON_BLOCK_DSP soc/intel/common/block/dsp bool

Intel Processor common DSP support

SOC_INTEL_COMMON_BLOCK_I2C soc/intel/common/block/i2c bool

Intel Processor Common I2C support

SOC_INTEL_COMMON_BLOCK_I2C_DEBUG soc/intel/common/block/i2c bool Enable debug output for LPSS I2C transactions

Enable debug output for I2C transactions. This can be useful when debugging I2C drivers.

SOC_INTEL_COMMON_BLOCK_SRAM soc/intel/common/block/sram bool

Intel Processor common SRAM support

SOC_INTEL_COMMON_BLOCK_ITSS soc/intel/common/block/itss bool

Intel Processor common interrupt timer subsystem support

SOC_INTEL_COMMON_BLOCK_GRAPHICS soc/intel/common/block/graphics bool

Intel Processor common Graphics support

ACPI_CONSOLE soc/intel/common bool

Provide a mechanism for serial console based ACPI debug.

MMA soc/intel/common bool Enable MMA (Memory Margin Analysis) support for Intel Core

Set this option to y to enable MMA (Memory Margin Analysis) support

TPM_TIS_ACPI_INTERRUPT soc/intel/common int

acpi_get_gpe() is used to provide interrupt status to TPM layer. This option specifies the GPE number.

SOC_AMD_STONEYRIDGE_FP4 soc/amd/stoneyridge bool

AMD Stoney Ridge FP4 support

SOC_AMD_STONEYRIDGE_FT4 soc/amd/stoneyridge bool

AMD Stoney Ridge FT4 support

DCACHE_BSP_STACK_SIZE soc/amd/stoneyridge hex

The amount of anticipated stack usage in CAR by bootblock and other stages.

PRERAM_CBMEM_CONSOLE_SIZE soc/amd/stoneyridge hex

Increase this value if preram cbmem console is getting truncated

BOTTOMIO_POSITION soc/amd/stoneyridge hex Bottom of 32-bit IO space

If PCI peripherals with big BARs are connected to the system the bottom of the IO must be decreased to allocate such devices.

Declare the beginning of the 128MB-aligned MMIO region. This option is useful when PCI peripherals requesting large address ranges are present.

VGA_BIOS_ID soc/amd/stoneyridge string

The default VGA BIOS PCI vendor/device ID should be set to the result of the map_oprom_vendev() function in northbridge.c.

STONEYRIDGE_XHCI_ENABLE soc/amd/stoneyridge bool Enable Stoney Ridge XHCI Controller

The XHCI controller must be enabled and the XHCI firmware must be added in order to have USB 3.0 support configured by coreboot. The OS will be responsible for enabling the XHCI controller if the the XHCI firmware is available but the XHCI controller is not enabled by coreboot.

STONEYRIDGE_XHCI_FWM soc/amd/stoneyridge bool Add xhci firmware

Add Stoney Ridge XHCI Firmware to support the onboard USB 3.0

STONEYRIDGE_IMC_FWM soc/amd/stoneyridge bool Add IMC firmware

Add Stoney Ridge IMC Firmware to support the onboard fan control

STONEYRIDGE_GEC_FWM soc/amd/stoneyridge bool

Add Stoney Ridge GEC Firmware to support the onboard gigabit Ethernet MAC. Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.

STONEYRIDGE_SATA_MODE soc/amd/stoneyridge int SATA Mode

Select the mode in which SATA should be driven. The default is NATIVE. 0: NATIVE mode does not require a ROM. 2: AHCI may work with or without AHCI ROM. It depends on the payload support. For example, seabios does not require the AHCI ROM. 3: LEGACY IDE 4: IDE to AHCI 5: AHCI7804: ROM Required, and AMD driver required in the OS. 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.

(comment) NATIVE
(comment) AHCI
(comment) LEGACY IDE
(comment) IDE to AHCI
(comment) AHCI7804
(comment) IDE to AHCI7804
STONEYRIDGE_LEGACY_FREE soc/amd/stoneyridge bool System is legacy free

Select y if there is no keyboard controller in the system. This sets variables in AGESA and ACPI.

SERIRQ_CONTINUOUS_MODE soc/amd/stoneyridge bool

Set this option to y for serial IRQ in continuous mode. Otherwise it is in quiet mode.

STONEYRIDGE_ACPI_IO_BASE soc/amd/stoneyridge hex

Base address for the ACPI registers. This value must match the hardcoded value of AGESA.

STONEYRIDGE_UART soc/amd/stoneyridge bool UART controller on Stoney Ridge

There are two UART controllers in Stoney Ridge. The UART registers are memory-mapped. UART controller 0 registers range from FEDC_6000h to FEDC_6FFFh. UART controller 1 registers range from FEDC_8000h to FEDC_8FFFh.

USE_PSPSCUREOS soc/amd/stoneyridge bool Include PSP SecureOS blobs in AMD firmware

Include the PspSecureOs, PspTrustlet and TrustletKey binaries in the amdfw section.

If unsure, answer 'y'

AMDFW_OUTSIDE_CBFS soc/amd/stoneyridge bool The AMD firmware is outside CBFS

The AMDFW (PSP) is typically locatable in cbfs. Select this option to manually attach the generated amdfw.rom outside of cbfs. The location is selected by the FWM position.

AMD_FWM_POSITION_INDEX soc/amd/stoneyridge int Firmware Directory Table location (0 to 5)

Typically this is calculated by the ROM size, but there may be situations where you want to put the firmware directory table in a different location. 0: 512 KB - 0xFFFA0000 1: 1 MB - 0xFFF20000 2: 2 MB - 0xFFE20000 3: 4 MB - 0xFFC20000 4: 8 MB - 0xFF820000 5: 16 MB - 0xFF020000

(comment) AMD Firmware Directory Table set to location for 512KB ROM
(comment) AMD Firmware Directory Table set to location for 1MB ROM
(comment) AMD Firmware Directory Table set to location for 2MB ROM
(comment) AMD Firmware Directory Table set to location for 4MB ROM
(comment) AMD Firmware Directory Table set to location for 8MB ROM
(comment) AMD Firmware Directory Table set to location for 16MB ROM
MAINBOARD_POWER_RESTORE soc/amd/stoneyridge int

This option determines what state to go to once power is restored after having been lost in S0. Select this option to automatically return to S0. Otherwise the system will remain in S5 once power is restored.

VENDORCODE_FULL_SUPPORT soc/amd/stoneyridge int

This option determines if all files under vendorcode/amd/pi/00670F00/ will be compiled or only selected procedures of source files (minimum required).

SOC_AMD_COMMON soc/amd/common bool

common code for AMD SOCs

SOC_AMD_COMMON_BLOCK soc/amd/common/block bool

SoC driver for AMD common IP code

(comment) AMD SoC Common IP Code
SOC_AMD_COMMON_BLOCK_S3 soc/amd/common/block/s3 bool

Select this option to add S3 related functions to the build.

SOC_AMD_COMMON_BLOCK_PI soc/amd/common/block/pi bool

This option builds functions that interface AMD's AGESA.

SOC_AMD_COMMON_BLOCK_PCI soc/amd/common/block/pci bool

This option builds functions used to program PCI interrupt routing, both PIC and APIC modes.

SOC_AMD_COMMON_BLOCK_CAR soc/amd/common/block/cpu bool

This option allows the SOC to use a standard AMD cache-as-ram (CAR) implementation. CAR setup is built into bootblock and teardown is in postcar. The teardown procedure does not preserve the stack so it may not be appropriate for a romstage implementation without additional consideration. If this option is not used, the SOC must implement these functions separately.

SOC_AMD_COMMON_BLOCK_PSP soc/amd/common/block/psp bool

This option builds in the Platform Security Processor initialization functions.

SOC_AMD_PSP_SELECTABLE_SMU_FW soc/amd/common/block/psp bool

Some PSP implementations allow storing SMU firmware into cbfs and calling the PSP to load the blobs at the proper time.

The soc/<codename> should select this if its PSP supports the feature and each mainboard can choose to select an appropriate fanless or fanned set of blobs. Ask your AMD representative whether your APU is considered fanless.

CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE soc/broadcom/cygnus bool Enable DDR auto self-refresh

Warning: M0 expects that auto self-refresh is enabled. Modify with caution.


DEBUG_DRAM soc/mediatek/mt8173 bool Output verbose DRAM related debug messages

This option enables additional DRAM related debug messages.

DEBUG_I2C soc/mediatek/mt8173 bool Output verbose I2C related debug messages

This option enables I2C related debug messages.

DEBUG_PMIC soc/mediatek/mt8173 bool Output verbose PMIC related debug messages

This option enables PMIC related debug messages.

DEBUG_PMIC_WRAP soc/mediatek/mt8173 bool Output verbose PMIC WRAP related debug messages

This option enables PMIC WRAP related debug messages.

CONSOLE_SERIAL_MVMAP2315_UART_ADDRESS soc/marvell/mvmap2315 hex

Map the UART to the respective MMIO address

TTYS0_BAUD soc/marvell/mvmap2315 int

Baud rate for the UART

IPQ_QFN_PART soc/qualcomm/ipq40xx bool

Is the SoC a QFN part (as opposed to a BGA part)

SBL_ELF soc/qualcomm/ipq40xx string file name of the QCA SBL ELF

The path and filename of the binary blob containing ipq40xx early initialization code, as supplied by the vendor.

SBL_UTIL_PATH soc/qualcomm/ipq40xx string Path for utils to combine SBL_ELF and bootblock

Path for utils to combine SBL_ELF and bootblock

SBL_BLOB soc/qualcomm/ipq806x string file name of the Qualcomm SBL blob

The path and filename of the binary blob containing ipq806x early initialization code, as supplied by the vendor.

RK3399_SPREAD_SPECTRUM_DDR soc/rockchip/rk3399 bool Spread-spectrum DDR clock

Select Spread Spectrum Modulator (SSMOD) is a fully-digital circuit used to modulate the frequency of the Silicon Creations’ Fractional PLL in order to reduce EMI.

(comment) CPU
RESET_ON_INVALID_RAMSTAGE_CACHE cpu/intel/haswell bool Reset the system on S3 wake when ramstage cache invalid.

The haswell romstage code caches the loaded ramstage program in SMM space. On S3 wake the romstage will copy over a fresh ramstage that was cached in the SMM space. This option determines the action to take when the ramstage cache is invalid. If selected the system will reset otherwise the ramstage will be reloaded from cbfs.

CPU_INTEL_FIRMWARE_INTERFACE_TABLE cpu/intel/fit None

This option selects building a Firmware Interface Table (FIT).

CPU_INTEL_NUM_FIT_ENTRIES cpu/intel/fit int

This option selects the number of empty entries in the FIT table.

CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED cpu/intel/turbo None

This option indicates that the turbo mode setting is not package scoped. i.e. enable_turbo() needs to be called on not just the bsp

SET_VMX_LOCK_BIT cpu/intel/common bool Set lock bit after configuring VMX

Although the Intel manual says you must set the lock bit in addition to the VMX bit in order for VMX to work, this isn't strictly true, so we have the option to leave it unlocked and allow the OS (e.g. Linux) to manage things itself. This is beneficial for testing purposes as there is no need to reflash the firmware just to toggle the lock bit. However, leaving the lock bit unset will break Windows' detection of VMX support and built-in virtualization features like Hyper-V.

GEODE_VSA_FILE cpu/amd/geode_lx bool Add a VSA image

Select this option if you have an AMD Geode LX vsa that you would like to add to your ROM.

You will be able to specify the location and file name of the image later.

VSA_FILENAME cpu/amd/geode_lx string AMD Geode LX VSA path and filename

The path and filename of the file to use as VSA.

XIP_ROM_SIZE cpu/amd/agesa hex

Overwride the default write through caching size as 1M Bytes. On some AMD platforms, one socket supports 2 or more kinds of processor family, compiling several CPU families agesa code will increase the romstage size. In order to execute romstage in place on the flash ROM, more space is required to be set as write through caching.

ENABLE_MRC_CACHE cpu/amd/agesa bool Use cached memory configuration

Try to restore memory training results from non-volatile memory.

FORCE_AM1_SOCKET_SUPPORT cpu/amd/agesa/family16kb bool

Force AGESA to ignore package type mismatch between CPU and northbridge in memory code. This enables Socket AM1 support with current AGESA version for Kabini platform. Enable this option only if you have Socket AM1 board. Note that the AGESA release shipped with coreboot does not officially support the AM1 socket. Selecting this option might damage your hardware.

XIP_ROM_SIZE cpu/amd/pi hex

Overwride the default write through caching size as 1M Bytes. On some AMD platforms, one socket supports 2 or more kinds of processor family, compiling several CPU families agesa code will increase the romstage size. In order to execute romstage in place on the flash ROM, more space is required to be set as write through caching.

PARALLEL_MP cpu/x86 bool

This option uses common MP infrastructure for bringing up APs in parallel. It additionally provides a more flexible mechanism for sequencing the steps of bringing up the APs.

PARALLEL_MP_AP_WORK cpu/x86 bool

Allow APs to do other work after initialization instead of going to sleep.

LAPIC_MONOTONIC_TIMER cpu/x86 bool

Expose monotonic time using the local APIC.

TSC_CONSTANT_RATE cpu/x86 bool

This option asserts that the TSC ticks at a known constant rate. Therefore, no TSC calibration is required.

TSC_MONOTONIC_TIMER cpu/x86 bool

Expose monotonic time using the TSC.

TSC_SYNC_LFENCE cpu/x86 bool

The CPU driver should select this if the CPU needs to execute an lfence instruction in order to synchronize rdtsc. This is true for all modern AMD CPUs.

TSC_SYNC_MFENCE cpu/x86 bool

The CPU driver should select this if the CPU needs to execute an mfence instruction in order to synchronize rdtsc. This is true for all modern Intel CPUs.

NO_FIXED_XIP_ROM_SIZE cpu/x86 bool

The XIP_ROM_SIZE Kconfig variable is used globally on x86 with the assumption that all chipsets utilize this value. For the chipsets which do not use the variable it can lead to unnecessary alignment constraints in cbfs for romstage. Therefore, allow those chipsets a path to not be burdened.

SMM_MODULE_HEAP_SIZE cpu/x86 hex

This option determines the size of the heap within the SMM handler modules.

SERIALIZED_SMM_INITIALIZATION cpu/x86 bool

On some CPUs, there is a race condition in SMM. This can occur when both hyperthreads change SMM state variables in parallel without coordination. Setting this option serializes the SMM initialization to avoid an ugly hang in the boot process at the cost of a slightly longer boot time.

X86_AMD_FIXED_MTRRS cpu/x86 bool

This option informs the MTRR code to use the RdMem and WrMem fields in the fixed MTRR MSRs.

PLATFORM_USES_FSP1_0 cpu/x86 bool

Selected for Intel processors/platform combinations that use the Intel Firmware Support Package (FSP) 1.0 for initialization.

MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING cpu/x86 bool

On certain platforms a boot speed gain can be realized if mirroring the payload data stored in non-volatile storage. On x86 systems the payload would typically live in a memory-mapped SPI part. Copying the SPI contents to RAM before performing the load can speed up the boot process.

SOC_SETS_MSRS cpu/x86 bool

The SoC requires different access methods for reading and writing the MSRs. Use SoC specific routines to handle the MSR access.

NO_CAR_GLOBAL_MIGRATION cpu bool

This option is selected if there is no need to migrate CAR globals. All stages which use CAR globals can directly access the variables from their linked addresses.

SMP cpu bool

This option is used to enable certain functions to make coreboot work correctly on symmetric multi processor (SMP) systems.

AP_SIPI_VECTOR cpu hex

This must equal address of ap_sipi_vector from bootblock build.

MMX cpu bool

Select MMX in your socket or model Kconfig if your CPU has MMX streaming SIMD instructions. ROMCC can build more efficient code if it can spill to MMX registers.

SSE cpu bool

Select SSE in your socket or model Kconfig if your CPU has SSE streaming SIMD instructions. ROMCC can build more efficient code if it can spill to SSE (aka XMM) registers.

SSE2 cpu bool

Select SSE2 in your socket or model Kconfig if your CPU has SSE2 streaming SIMD instructions. Some parts of coreboot can be built with more efficient code if SSE2 instructions are available.

USES_MICROCODE_HEADER_FILES cpu bool

This is selected by a board or chipset to set the default for the microcode source choice to a list of external microcode headers

CPU_MICROCODE_CBFS_GENERATE cpu bool Generate from tree

Select this option if you want microcode updates to be assembled when building coreboot and included in the final image as a separate CBFS file. Microcode will not be hard-coded into ramstage.

The microcode file may be removed from the ROM image at a later time with cbfstool, if desired.

If unsure, select this option.

CPU_MICROCODE_CBFS_EXTERNAL_HEADER cpu bool Include external microcode header files

Select this option if you want to include external c header files containing the CPU microcode. This will be included as a separate file in CBFS.

A word of caution: only select this option if you are sure the microcode that you have is newer than the microcode shipping with coreboot.

The microcode file may be removed from the ROM image at a later time with cbfstool, if desired.

If unsure, select "Generate from tree"

CPU_MICROCODE_CBFS_NONE cpu bool Do not include microcode updates

Select this option if you do not want CPU microcode included in CBFS. Note that for some CPUs, the microcode is hard-coded into the source tree and is not loaded from CBFS. In this case, microcode will still be updated. There is a push to move all microcode to CBFS, but this change is not implemented for all CPUs.

This option currently applies to: - Intel SandyBridge/IvyBridge - VIA Nano

Microcode may be added to the ROM image at a later time with cbfstool, if desired.

If unsure, select "Generate from tree"

The GOOD: Microcode updates intend to solve issues that have been discovered after CPU production. The expected effect is that systems work as intended with the updated microcode, but we have also seen cases where issues were solved by not applying microcode updates.

The BAD: Note that some operating system include these same microcode patches, so you may need to also disable microcode updates in your operating system for this option to have an effect.

The UGLY: A word of CAUTION: some CPUs depend on microcode updates to function correctly. Not updating the microcode may leave the CPU operating at less than optimal performance, or may cause outright hangups. There are CPUs where coreboot cannot properly initialize the CPU without microcode updates For example, if running with the factory microcode, some Intel SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs will hang when changing the frequency.

Make sure you have a way of flashing the ROM externally before selecting this option.

CPU_MICROCODE_MULTIPLE_FILES cpu bool

Select this option to install separate microcode container files into CBFS instead of using the traditional monolithic microcode file format.

CPU_MICROCODE_HEADER_FILES cpu string List of space separated microcode header files with the path

A list of one or more microcode header files with path from the coreboot directory. These should be separated by spaces.

CPU_UCODE_BINARIES cpu string Microcode binary path and filename

Some platforms have microcode in the blobs directory, and these can be hardcoded in the makefiles. For platforms with microcode binaries that aren't in the makefile, set this option to pull in the microcode.

This should contain the full path of the file for one or more microcode binary files to include, separated by spaces.

If unsure, leave this blank.

(comment) Northbridge
I945_LVDS northbridge/intel/i945 string

Selected by mainboards that use native graphics initialization for the LVDS port. A linear framebuffer is only supported for LVDS.

OVERRIDE_CLOCK_DISABLE northbridge/intel/i945 bool

Usually system firmware turns off system memory clock signals to unused SO-DIMM slots to reduce EMI and power consumption. However, some boards do not like unused clock signals to be disabled.

MAXIMUM_SUPPORTED_FREQUENCY northbridge/intel/i945 int

If non-zero, this designates the maximum DDR frequency the board supports, despite what the chipset should be capable of.

CHECK_SLFRCS_ON_RESUME northbridge/intel/i945 int

On some boards it may be neccessary to hard reset early during resume from S3 if the SLFRCS register indicates that a memory channel is not guaranteed to be in self-refresh. On other boards the check always creates a false positive, effectively making it impossible to resume.

USE_NATIVE_RAMINIT northbridge/intel/sandybridge bool Use native raminit

Select if you want to use coreboot implementation of raminit rather than System Agent/MRC.bin. You should answer Y.

NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES northbridge/intel/sandybridge bool Ignore vendor programmed fuses that limit max. DRAM frequency

Ignore the mainboard's vendor programmed fuses that might limit the maximum DRAM frequency. By selecting this option the fuses will be ignored and the only limits on DRAM frequency are set by RAM's SPD and hard fuses in southbridge's clockgen. Disabled by default as it might causes system instability. Handle with care!

NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS northbridge/intel/sandybridge bool Ignore XMP profile max DIMMs per channel

Ignore the max DIMMs per channel restriciton defined in XMP profiles. Disabled by default as it might cause system instability. Handle with care!

MMCONF_BASE_ADDRESS northbridge/intel/sandybridge hex

The MRC blob requires it to be at 0xf0000000.

MRC_FILE northbridge/intel/sandybridge string Intel System Agent path and filename

The path and filename of the file to use as System Agent binary.

DCACHE_RAM_SIZE northbridge/intel/haswell hex

The size of the cache-as-ram region required during bootblock and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2.

DCACHE_RAM_MRC_VAR_SIZE northbridge/intel/haswell hex

The amount of cache-as-ram region required by the reference code.

DCACHE_RAM_ROMSTAGE_STACK_SIZE northbridge/intel/haswell hex

The amount of anticipated stack usage from the data cache during pre-ram ROM stage execution.

HAVE_MRC northbridge/intel/haswell bool Add a System Agent binary

Select this option to add a System Agent binary to the resulting coreboot image.

Note: Without this binary coreboot will not work

MRC_FILE northbridge/intel/haswell string Intel System Agent path and filename

The path and filename of the file to use as System Agent binary.

PRE_GRAPHICS_DELAY northbridge/intel/haswell int Graphics initialization delay in ms

On some systems, coreboot boots so fast that connected monitors (mostly TVs) won't be able to wake up fast enough to talk to the VBIOS. On those systems we need to wait for a bit before executing the VBIOS.

VGA_BIOS_ID northbridge/intel/fsp_sandybridge string

This is the default PCI ID for the sandybridge/ivybridge graphics devices. This string names the vbios ROM in cbfs. The following PCI IDs will be remapped to load this ROM: 0x80860102, 0x8086010a, 0x80860112, 0x80860116 0x80860122, 0x80860126, 0x80860166

FSP_FILE northbridge/intel/fsp_sandybridge/fsp string

The path and filename of the Intel FSP binary for this platform.

FSP_LOC northbridge/intel/fsp_sandybridge/fsp hex Intel FSP Binary location in CBFS

The location in CBFS that the FSP is located. This must match the value that is set in the FSP binary. If the FSP needs to be moved, rebase the FSP with the Intel's BCT (tool).

The Ivy Bridge Processor/Panther Point FSP is built with a preferred base address of 0xFFF80000

SDRAMPWR_4DIMM northbridge/intel/i440bx bool

This option affects how the SDRAMC register is programmed. Memory clock signals will not be routed properly if this option is set wrong.

If your board has 4 DIMM slots, you must use select this option, in your Kconfig file of the board. On boards with 3 DIMM slots, do _not_ select this option.

SET_TSEG_1MB northbridge/intel/fsp_rangeley bool 1 MB

Set the TSEG area to 1 MB.

SET_TSEG_2MB northbridge/intel/fsp_rangeley bool 2 MB

Set the TSEG area to 2 MB.

SET_TSEG_4MB northbridge/intel/fsp_rangeley bool 4 MB

Set the TSEG area to 4 MB.

SET_TSEG_8MB northbridge/intel/fsp_rangeley bool 8 MB

Set the TSEG area to 8 MB.

FSP_FILE northbridge/intel/fsp_rangeley/fsp string

The path and filename of the Intel FSP binary for this platform.

FSP_LOC northbridge/intel/fsp_rangeley/fsp hex

The location in CBFS that the FSP is located. This must match the value that is set in the FSP binary. If the FSP needs to be moved, rebase the FSP with Intel's BCT (tool).

The Rangeley FSP is built with a preferred base address of 0xFFF80000

BOTTOMIO_POSITION northbridge/amd/pi hex Bottom of 32-bit IO space

If PCI peripherals with big BARs are connected to the system the bottom of the IO must be decreased to allocate such devices.

Declare the beginning of the 128MB-aligned MMIO region. This option is useful when PCI peripherals requesting large address ranges are present.

VGA_BIOS_ID northbridge/amd/pi/00630F01 string

The default VGA BIOS PCI vendor/device ID should be set to the result of the map_oprom_vendev() function in northbridge.c.

VGA_BIOS_ID northbridge/amd/pi/00730F01 string

The default VGA BIOS PCI vendor/device ID should be set to the result of the map_oprom_vendev() function in northbridge.c.

VGA_BIOS_ID northbridge/amd/pi/00660F01 string

The default VGA BIOS PCI vendor/device ID should be set to the result of the map_oprom_vendev() function in northbridge.c.

REDIRECT_NBCIMX_TRACE_TO_SERIAL northbridge/amd/cimx/rd890 bool Redirect AMD Northbridge CIMX Trace to serial console

This Option allows you to redirect the AMD Northbridge CIMX Trace debug information to the serial console.

Warning: Only enable this option when debuging or tracing AMD CIMX code.

NO_MMCONF_SUPPORT northbridge/amd/amdk8 bool

If you want to remove this, you need to make sure any access to CPU nodes 0:18.0, 0:19.0, ... continue to use PCI IO config access.

VGA_BIOS_ID northbridge/amd/agesa/family16kb string

The default VGA BIOS PCI vendor/device ID should be set to the result of the map_oprom_vendev() function in northbridge.c.

SVI_HIGH_FREQ northbridge/amd/amdfam10 bool

Select this for boards with a Voltage Regulator able to operate at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.

Menu: HyperTransport setup
SVI_HIGH_FREQ northbridge/amd/amdfam10 bool HyperTransport downlink width

This option sets the maximum permissible HyperTransport downlink width.

Use of this option will only limit the autodetected HT width. It will not (and cannot) increase the width beyond the autodetected limits.

This is primarily used to work around poorly designed or laid out HT traces on certain motherboards.

LIMIT_HT_DOWN_WIDTH_16 northbridge/amd/amdfam10 bool HyperTransport uplink width

This option sets the maximum permissible HyperTransport uplink width.

Use of this option will only limit the autodetected HT width. It will not (and cannot) increase the width beyond the autodetected limits.

This is primarily used to work around poorly designed or laid out HT traces on certain motherboards.

(comment) Southbridge
SERIRQ_CONTINUOUS_MODE southbridge/intel/ibexpeak bool

If you set this option to y, the serial IRQ machine will be operated in continuous mode.

INTEL_LYNXPOINT_LP southbridge/intel/lynxpoint bool

Set this option to y for Lynxpont LP (Haswell ULT).

SERIRQ_CONTINUOUS_MODE southbridge/intel/lynxpoint bool

If you set this option to y, the serial IRQ machine will be operated in continuous mode.

ME_MBP_CLEAR_LATE southbridge/intel/lynxpoint bool Defer wait for ME MBP Cleared

If you set this option to y, the Management Engine driver will defer waiting for the MBP Cleared indicator until the finalize step. This can speed up boot time if the ME takes a long time to indicate this status.

FINALIZE_USB_ROUTE_XHCI southbridge/intel/lynxpoint bool Route all ports to XHCI controller in finalize step

If you set this option to y, the USB ports will be routed to the XHCI controller during the finalize SMM callback.

SERIRQ_CONTINUOUS_MODE southbridge/intel/bd82x6x bool

If you set this option to y, the serial IRQ machine will be operated in continuous mode.

LOCK_SPI_FLASH_RO southbridge/intel/bd82x6x bool Write-protect all flash sections

Select this if you want to write-protect the whole firmware flash chip. The locking will take place during the chipset lockdown, which is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set) or has to be triggered later (e.g. by the payload or the OS).

NOTE: If you trigger the chipset lockdown unconditionally, you won't be able to write to the flash chip using the internal programmer any more.

LOCK_SPI_FLASH_NO_ACCESS southbridge/intel/bd82x6x bool Write-protect all flash sections and read-protect non-BIOS sections

Select this if you want to protect the firmware flash against all further accesses (with the exception of the memory mapped BIOS re- gion which is always readable). The locking will take place during the chipset lockdown, which is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set) or has to be triggered later (e.g. by the payload or the OS).

NOTE: If you trigger the chipset lockdown unconditionally, you won't be able to write to the flash chip using the internal programmer any more.

SERIRQ_CONTINUOUS_MODE southbridge/intel/fsp_bd82x6x bool

If you set this option to y, the serial IRQ machine will be operated in continuous mode.

INTEL_CHIPSET_LOCKDOWN southbridge/intel/common bool Lock down chipset in coreboot

Some registers within host bridge on particular chipsets should be locked down on each normal boot path (done by either coreboot or payload) and S3 resume (always done by coreboot). Select this to let coreboot to do this on normal boot path.

SERIRQ_CONTINUOUS_MODE southbridge/intel/fsp_rangeley bool

If you set this option to y, the serial IRQ machine will be operated in continuous mode.

IFD_BIN_PATH southbridge/intel/fsp_rangeley string

The path and filename to the descriptor.bin file.

SERIRQ_CONTINUOUS_MODE southbridge/intel/fsp_i89xx bool

If you set this option to y, the serial IRQ machine will be operated in continuous mode.

HUDSON_XHCI_ENABLE southbridge/amd/pi/hudson bool Enable Hudson XHCI Controller

The XHCI controller must be enabled and the XHCI firmware must be added in order to have USB 3.0 support configured by coreboot. The OS will be responsible for enabling the XHCI controller if the the XHCI firmware is available but the XHCI controller is not enabled by coreboot.

HUDSON_XHCI_FWM southbridge/amd/pi/hudson bool Add xhci firmware

Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0

HUDSON_IMC_FWM southbridge/amd/pi/hudson bool Add IMC firmware

Add Hudson 2/3/4 IMC Firmware to support the onboard fan control

HUDSON_GEC_FWM southbridge/amd/pi/hudson bool

Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC. Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.

HUDSON_SATA_MODE southbridge/amd/pi/hudson int SATA Mode

Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. The default is NATIVE. 0: NATIVE mode does not require a ROM. 1: RAID mode must have the two ROM files. 2: AHCI may work with or without AHCI ROM. It depends on the payload support. For example, seabios does not require the AHCI ROM. 3: LEGACY IDE 4: IDE to AHCI 5: AHCI7804: ROM Required, and AMD driver required in the OS. 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.

(comment) NATIVE
(comment) RAID
(comment) AHCI
(comment) LEGACY IDE
(comment) IDE to AHCI
(comment) AHCI7804
(comment) IDE to AHCI7804
RAID_ROM_ID southbridge/amd/pi/hudson string RAID device PCI IDs

1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode

RAID_MISC_ROM_POSITION southbridge/amd/pi/hudson hex RAID Misc ROM Position

The RAID ROM requires that the MISC ROM is located between the range 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned. The CONFIG_ROM_SIZE must be larger than 0x100000.

HUDSON_LEGACY_FREE southbridge/amd/pi/hudson bool System is legacy free

Select y if there is no keyboard controller in the system. This sets variables in AGESA and ACPI.

AZ_PIN southbridge/amd/pi/hudson hex

bit 1,0 - pin 0 bit 3,2 - pin 1 bit 5,4 - pin 2 bit 7,6 - pin 3

AMDFW_OUTSIDE_CBFS southbridge/amd/pi/hudson hex

The AMDFW (PSP) is typically locatable in cbfs. Select this option to manually attach the generated amdfw.rom at an offset of 0x20000 from the bottom of the coreboot ROM image.

SERIRQ_CONTINUOUS_MODE southbridge/amd/pi/hudson bool

Set this option to y for serial IRQ in continuous mode. Otherwise it is in quiet mode.

HUDSON_ACPI_IO_BASE southbridge/amd/pi/hudson hex

Base address for the ACPI registers. This value must match the hardcoded value of AGESA.

HUDSON_UART southbridge/amd/pi/hudson bool UART controller on Kern

There are two UART controllers in Kern. The UART registers are memory-mapped. UART controller 0 registers range from FEDC_6000h to FEDC_6FFFh. UART controller 1 registers range from FEDC_8000h to FEDC_8FFFh.

ENABLE_IDE_COMBINED_MODE southbridge/amd/cimx/sb800 bool Enable SATA IDE combined mode

If Combined Mode is enabled. IDE controller is exposed and SATA controller has control over Port0 through Port3, IDE controller has control over Port4 and Port5.

If Combined Mode is disabled, IDE controller is hidden and SATA controller has full control of all 6 Ports when operating in non-IDE mode.

IDE_COMBINED_MODE southbridge/amd/cimx/sb800 hex SATA Mode

Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. The default is AHCI.

SB800_SATA_IDE southbridge/amd/cimx/sb800 bool NATIVE

NATIVE does not require a ROM.

SB800_SATA_AHCI southbridge/amd/cimx/sb800 bool AHCI

AHCI is the default and may work with or without AHCI ROM. It depends on the payload support. For example, seabios does not require the AHCI ROM.

SB800_SATA_RAID southbridge/amd/cimx/sb800 bool RAID

sb800 RAID mode must have the two required ROM files.

RAID_ROM_ID southbridge/amd/cimx/sb800 string RAID device PCI IDs

1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode

RAID_MISC_ROM_POSITION southbridge/amd/cimx/sb800 hex RAID Misc ROM Position

The RAID ROM requires that the MISC ROM is located between the range 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned. The CONFIG_ROM_SIZE must larger than 0x100000.

SB800_IMC_FWM southbridge/amd/cimx/sb800 bool Add IMC firmware

Add SB800 / Hudson 1 IMC Firmware to support the onboard fan control.

SB800_FWM_AT_FFFA0000 southbridge/amd/cimx/sb800 bool 0xFFFA0000

The IMC and GEC ROMs requires a 'signature' located at one of several fixed locations in memory. The location used shouldn't matter, just select an area that doesn't conflict with anything else.

SB800_FWM_AT_FFF20000 southbridge/amd/cimx/sb800 bool 0xFFF20000

The IMC and GEC ROMs requires a 'signature' located at one of several fixed locations in memory. The location used shouldn't matter, just select an area that doesn't conflict with anything else.

SB800_FWM_AT_FFE20000 southbridge/amd/cimx/sb800 bool 0xFFE20000

The IMC and GEC ROMs requires a 'signature' located at one of several fixed locations in memory. The location used shouldn't matter, just select an area that doesn't conflict with anything else.

SB800_FWM_AT_FFC20000 southbridge/amd/cimx/sb800 bool 0xFFC20000

The IMC and GEC ROMs requires a 'signature' located at one of several fixed locations in memory. The location used shouldn't matter, just select an area that doesn't conflict with anything else.

SB800_FWM_AT_FF820000 southbridge/amd/cimx/sb800 bool 0xFF820000

The IMC and GEC ROMs requires a 'signature' located at one of several fixed locations in memory. The location used shouldn't matter, just select an area that doesn't conflict with anything else.

EHCI_BAR southbridge/amd/cimx/sb800 hex Fan Control

Select the method of SB800 fan control to be used. None would be for either fixed maximum speed fans connected to the SB800 or for an external chip controlling the fan speeds. Manual control sets up the SB800 fan control registers. IMC fan control uses the SB800 IMC to actively control the fan speeds.

SB800_NO_FAN_CONTROL southbridge/amd/cimx/sb800 bool None

No SB800 Fan control - Do not set up the SB800 fan control registers.

SB800_MANUAL_FAN_CONTROL southbridge/amd/cimx/sb800 bool Manual

Configure the SB800 fan control registers in devicetree.cb.

SB800_IMC_FAN_CONTROL southbridge/amd/cimx/sb800 bool IMC Based

Set up the SB800 to use the IMC based Fan controller. This requires the IMC ROM from AMD. Configure the registers in devicetree.cb.

SATA_CONTROLLER_MODE southbridge/amd/cimx/sb900 hex

0x0 = Native IDE mode. 0x1 = RAID mode. 0x2 = AHCI mode. 0x3 = Legacy IDE mode. 0x4 = IDE->AHCI mode. 0x5 = AHCI mode as 7804 ID (AMD driver). 0x6 = IDE->AHCI mode as 7804 ID (AMD driver).

PCIB_ENABLE southbridge/amd/cimx/sb900 bool

n = Disable PCI Bridge Device 14 Function 4. y = Enable PCI Bridge Device 14 Function 4.

ACPI_SCI_IRQ southbridge/amd/cimx/sb900 hex

Set SCI IRQ to 9.

EXT_CONF_SUPPORT southbridge/amd/sr5650 bool Enable PCI-E MMCONFIG support

Select to enable PCI-E MMCONFIG support on the SR5650.

EXT_CONF_SUPPORT southbridge/amd/rs690 bool

Select if RS690 should be setup to support MMCONF.

HUDSON_XHCI_ENABLE southbridge/amd/agesa/hudson bool Enable Hudson XHCI Controller

The XHCI controller must be enabled and the XHCI firmware must be added in order to have USB 3.0 support configured by coreboot. The OS will be responsible for enabling the XHCI controller if the the XHCI firmware is available but the XHCI controller is not enabled by coreboot.

HUDSON_XHCI_FWM southbridge/amd/agesa/hudson bool Add xhci firmware

Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0

HUDSON_IMC_FWM southbridge/amd/agesa/hudson bool Add imc firmware

Add Hudson 2/3/4 IMC Firmware to support the onboard fan control

HUDSON_GEC_FWM southbridge/amd/agesa/hudson bool

Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC. Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.

HUDSON_SATA_MODE southbridge/amd/agesa/hudson int SATA Mode

Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. The default is NATIVE. 0: NATIVE mode does not require a ROM. 1: RAID mode must have the two ROM files. 2: AHCI may work with or without AHCI ROM. It depends on the payload support. For example, seabios does not require the AHCI ROM. 3: LEGACY IDE 4: IDE to AHCI 5: AHCI7804: ROM Required, and AMD driver required in the OS. 6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.

(comment) NATIVE
(comment) RAID
(comment) AHCI
(comment) LEGACY IDE
(comment) IDE to AHCI
(comment) AHCI7804
(comment) IDE to AHCI7804
RAID_ROM_ID southbridge/amd/agesa/hudson string RAID device PCI IDs

1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode

RAID_MISC_ROM_POSITION southbridge/amd/agesa/hudson hex RAID Misc ROM Position

The RAID ROM requires that the MISC ROM is located between the range 0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned. The CONFIG_ROM_SIZE must be larger than 0x100000.

HUDSON_LEGACY_FREE southbridge/amd/agesa/hudson bool System is legacy free

Select y if there is no keyboard controller in the system. This sets variables in AGESA and ACPI.

AZ_PIN southbridge/amd/agesa/hudson hex

bit 1,0 - pin 0 bit 3,2 - pin 1 bit 5,4 - pin 2 bit 7,6 - pin 3

SOUTHBRIDGE_AMD_SB700_33MHZ_SPI southbridge/amd/sb700 bool Enable high speed SPI clock

When set, the SPI clock will run at 33MHz instead of the compatibility mode 16.5MHz. Note that not all ROMs are capable of 33MHz operation, so you will need to verify this option is appropriate for the ROM you are using.

NO_EARLY_SMBUS southbridge/amd/cs5536 bool

Skip the CS5536 early SMBUS initialization.

EHCI_BAR southbridge/amd/sb600 hex SATA Mode

Select the mode in which SATA should be driven. IDE or AHCI. The default is IDE.

config SATA_MODE_IDE bool "IDE"

config SATA_MODE_AHCI bool "AHCI"

(comment) Super I/O
SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG superio/ite/common bool

Enable extended, 16-bit wide tacho counters.

SUPERIO_ITE_ENV_CTRL_8BIT_PWM superio/ite/common bool

PWM duty cycles are set in 8-bit registers (instead of 7 bit).

SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 superio/ite/common bool

The second FAN controller has a separate frequency setting.

(comment) Embedded Controllers
EC_ACPI ec/acpi bool

ACPI Embedded Controller interface. Mostly found in laptops.

EC_GOOGLE_CHROMEEC ec/google/chromeec bool

Google's Chrome EC

EC_GOOGLE_CHROMEEC_ACPI_MEMMAP ec/google/chromeec bool

When defined, ACPI accesses EC memmap data on ports 66h/62h. When not defined, the memmap data is instead accessed on 900h-9ffh via the LPC bus.

EC_GOOGLE_CHROMEEC_BOARDID ec/google/chromeec bool

Provides common routine for reading boardid from Chrome EC.

EC_GOOGLE_CHROMEEC_I2C ec/google/chromeec bool

Google's Chrome EC via I2C bus.

EC_GOOGLE_CHROMEEC_I2C_PROTO3 ec/google/chromeec bool

Use only proto3 for i2c EC communication.

EC_GOOGLE_CHROMEEC_LPC ec/google/chromeec bool

Google Chrome EC via LPC bus.

EC_GOOGLE_CHROMEEC_MEC ec/google/chromeec bool

Microchip EC variant for LPC register access.

EC_GOOGLE_CHROMEEC_PD ec/google/chromeec bool

Indicates that Google's Chrome USB PD chip is present.

EC_GOOGLE_CHROMEEC_SPI ec/google/chromeec bool

Google's Chrome EC via SPI bus.

EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US ec/google/chromeec int

Force delay after asserting /CS to allow EC to wakeup.

EC_GOOGLE_CHROMEEC_BOARDNAME ec/google/chromeec string Chrome EC board name for EC

The board name used in the Chrome EC code base to build the EC firmware. If set, the coreboot build with also build the EC firmware and add it to the image.

EC_GOOGLE_CHROMEEC_PD_BOARDNAME ec/google/chromeec string Chrome EC board name for PD

The board name used in the Chrome EC code base to build the PD firmware. If set, the coreboot build with also build the EC firmware and add it to the image.

EC_GOOGLE_CHROMEEC_RTC ec/google/chromeec bool Enable Chrome OS EC RTC

Enable support for the real-time clock on the Chrome OS EC. This uses the EC_CMD_RTC_GET_VALUE command to read the current time.

EC_GOOGLE_CHROMEEC_FIRMWARE_NONE ec/google/chromeec bool No EC firmware is included

Disable building and including any EC firmware in the image.

config EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL bool "External EC firmware is included" help Include EC firmware binary in the image from an external source. It is expected to be built externally.

config EC_GOOGLE_CHROMEEC_FIRMWARE_BUILTIN bool "Builtin EC firmware is included" help Build and include EC firmware binary in the image.

EC_GOOGLE_CHROMEEC_FIRMWARE_FILE ec/google/chromeec string Chrome EC firmware path and filename

The path and filename of the EC firmware file to use.

EC_GOOGLE_CHROMEEC_PD_FIRMWARE_NONE ec/google/chromeec bool No PD firmware is included

Disable building and including any PD firmware in the image.

config EC_GOOGLE_CHROMEEC_PD_FIRMWARE_EXTERNAL bool "External PD firmware is included" help Include PD firmware binary in the image from an external source. It is expected to be built externally.

config EC_GOOGLE_CHROMEEC_PD_FIRMWARE_BUILTIN bool "Builtin PD firmware is included" help Build and include PD firmware binary in the image.

EC_GOOGLE_CHROMEEC_PD_FIRMWARE_FILE ec/google/chromeec string Chrome EC firmware path and filename for PD

The path and filename of the PD firmware file to use.

EC_GOOGLE_CHROMEEC_SWITCHES ec/google/chromeec bool

Enable support for Chrome OS mode switches provided by the Chrome OS EC.

EC_QUANTA_IT8518 ec/quanta/it8518 bool

Interface to QUANTA IT8518 Embedded Controller.

EC_QUANTA_ENE_KB3940Q ec/quanta/ene_kb3940q bool

Interface to QUANTA ENE KB3940Q Embedded Controller.

EC_HP_KBC1126 ec/hp/kbc1126 bool

Interface to SMSC KBC1126 embedded controller in HP laptops.

(comment) Please select the following otherwise your laptop cannot be powered on.
KBC1126_FIRMWARE ec/hp/kbc1126 bool Add firmware images for KBC1126 EC

Select this option to add the two firmware blobs for KBC1126. You need these two blobs to power on your machine.

KBC1126_FW1 ec/hp/kbc1126 string KBC1126 firmware #1 path and filename

The path and filename of the file to use as KBC1126 firmware #1. You can use util/kbc1126/kbc1126_ec_dump to dump it from the vendor firmware.

KBC1126_FW2 ec/hp/kbc1126 string KBC1126 filename #2 path and filename

The path and filename of the file to use as KBC1126 firmware #2. You can use util/kbc1126/kbc1126_ec_dump to dump it from the vendor firmware.

H8_BEEP_ON_DEATH ec/lenovo/h8 bool Beep on fatal error

Beep when encountered a fatal error.

H8_FLASH_LEDS_ON_DEATH ec/lenovo/h8 bool Flash LEDs on fatal error

Flash all LEDs when encountered a fatal error.

H8_SUPPORT_BT_ON_WIFI ec/lenovo/h8 bool Support bluetooth on wifi cards

Disable BDC detection and assume bluetooth is installed. Required for bluetooth on wifi cards, as it's not possible to detect it in coreboot.

EC_RODA_IT8518 ec/roda/it8518 bool

Interface to IT8518 embedded controller in Roda notebooks.

EC_SMSC_MEC1308 ec/smsc/mec1308 bool

Shared memory mailbox interface to SMSC MEC1308 Embedded Controller.

EC_PURISM_LIBREM ec/purism/librem bool

Purism Librem EC

EC_COMPAL_ENE932 ec/compal/ene932 bool

Interface to COMPAL ENE932 Embedded Controller.

EC_KONTRON_IT8516E ec/kontron/it8516e bool

Kontron uses an ITE IT8516E on the KTQM77. Its firmware might come from Fintek (mentioned as Finte*c* somewhere in their Linux driver). The KTQM77 is an embedded board and the IT8516E seems to be only used for fan control and GPIO.

(comment) Intel FSP
HAVE_FSP_BIN drivers/intel/fsp1_0 bool Use Intel Firmware Support Package

Select this option to add an Intel FSP binary to the resulting coreboot image.

Note: Without this binary, coreboot builds relying on the FSP will not boot

FSP_FILE drivers/intel/fsp1_0 string Intel FSP binary path and filename

The path and filename of the Intel FSP binary for this platform.

FSP_LOC drivers/intel/fsp1_0 hex Intel FSP Binary location in CBFS

The location in CBFS that the FSP is located. This must match the value that is set in the FSP binary. If the FSP needs to be moved, rebase the FSP with Intel's BCT (tool).

ENABLE_FSP_FAST_BOOT drivers/intel/fsp1_0 bool Enable Fast Boot

Enabling this feature will force the MRC data to be cached in NV storage to be used for speeding up boot time on future reboots and/or power cycles.

ENABLE_MRC_CACHE drivers/intel/fsp1_0 bool

Enabling this feature will cause MRC data to be cached in NV storage. This can either be used for fast boot, or just because the FSP wants it to be saved.

MRC_CACHE_FMAP drivers/intel/fsp1_0 bool Use MRC Cache in FMAP

Use the region "RW_MRC_CACHE" in FMAP instead of "mrc.cache" in CBFS. You must define a region in your FMAP named "RW_MRC_CACHE".

MRC_CACHE_SIZE drivers/intel/fsp1_0 hex Fast Boot Data Cache Size

This is the amount of space in NV storage that is reserved for the fast boot data cache storage.

WARNING: Because this area will be erased and re-written, the size should be a full sector of the flash ROM chip and nothing else should be included in CBFS in any sector that the fast boot cache data is in.

VIRTUAL_ROM_SIZE drivers/intel/fsp1_0 hex Virtual ROM Size

This is used to calculate the offset of the MRC data cache in NV Storage for fast boot. If in doubt, leave this set to the default which sets the virtual size equal to the ROM size.

Example: Cougar Canyon 2 has two 8 MB SPI ROMs. When the SPI ROMs are loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB. When the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM size is 16 MB.

CACHE_ROM_SIZE_OVERRIDE drivers/intel/fsp1_0 hex Cache ROM Size

This is the size of the cachable area that is passed into the FSP in the early initialization. Typically this should be the size of the CBFS area, but the size must be a power of 2 whereas the CBFS size does not have this limitation.

USE_GENERIC_FSP_CAR_INC drivers/intel/fsp1_0 bool

The chipset can select this to use a generic cache_as_ram.inc file that should be good for all FSP based platforms.

FSP_USES_UPD drivers/intel/fsp1_0 bool

If this FSP uses UPD/VPD data regions, select this in the chipset Kconfig.

HAVE_INTEL_FIRMWARE southbridge/intel/common/firmware bool

Chipset uses the Intel Firmware Descriptor to describe the layout of the SPI ROM chip.

(comment) Intel Firmware
HAVE_IFD_BIN southbridge/intel/common/firmware bool Add Intel descriptor.bin file

The descriptor binary

EM100 southbridge/intel/common/firmware bool Configure IFD for EM100 usage

Set SPI frequency to 20MHz and disable Dual Output Fast Read Support

HAVE_ME_BIN southbridge/intel/common/firmware bool Add Intel ME/TXE firmware

The Intel processor in the selected system requires a special firmware for an integrated controller. This might be called the Management Engine (ME), the Trusted Execution Engine (TXE) or something else depending on the chip. This firmware might or might not be available in coreboot's 3rdparty/blobs repository. If it is not and if you don't have access to the firmware from elsewhere, you can still build coreboot without it. In this case however, you'll have to make sure that you don't overwrite your ME/TXE firmware on your flash ROM.

CHECK_ME southbridge/intel/common/firmware bool Verify the integrity of the supplied ME/TXE firmware

Verify the integrity of the supplied Intel ME/TXE firmware before proceeding with the build, in order to prevent an accidental loading of a corrupted ME/TXE image.

USE_ME_CLEANER southbridge/intel/common/firmware bool Strip down the Intel ME/TXE firmware

Use me_cleaner to remove all the non-fundamental code from the Intel ME/TXE firmware. The resulting Intel ME/TXE firmware will have only the code responsible for the very basic hardware initialization, leaving the ME/TXE subsystem essentially in a disabled state.

Don't flash a modified ME/TXE firmware and a new coreboot image at the same time, test them in two different steps.

WARNING: this tool isn't based on any official Intel documentation but only on reverse engineering and trial & error.

See the project's page https://github.com/corna/me_cleaner or the wiki https://github.com/corna/me_cleaner/wiki/How-to-apply-me_cleaner https://github.com/corna/me_cleaner/wiki/How-does-it-work%3F https://github.com/corna/me_cleaner/wiki/me_cleaner-status for more info about this tool

If unsure, say N.

(comment) Please test the modified ME/TXE firmware and coreboot in two steps
HAVE_GBE_BIN southbridge/intel/common/firmware bool Add gigabit ethernet firmware

The integrated gigabit ethernet controller needs a firmware file. Select this if you are going to use the PCH integrated controller and have the firmware.

HAVE_EC_BIN southbridge/intel/common/firmware bool Add EC firmware

The embedded controller needs a firmware file.

Select this if you are going to use the PCH integrated controller and have the EC firmware. EC firmware will be added to final image through ifdtool.

BUILD_WITH_FAKE_IFD southbridge/intel/common/firmware bool Build with a fake IFD

If you don't have an Intel Firmware Descriptor (descriptor.bin) for your board, you can select this option and coreboot will build without it. The resulting coreboot.rom will not contain all parts required to get coreboot running on your board. You can however write only the BIOS section to your board's flash ROM and keep the other sections untouched. Unfortunately the current version of flashrom doesn't support this yet. But there is a patch pending [1].

WARNING: Never write a complete coreboot.rom to your flash ROM if it was built with a fake IFD. It just won't work.

[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html

IFD_BIOS_SECTION southbridge/intel/common/firmware string BIOS Region Starting:Ending addresses within the ROM

The BIOS region is typically the size of the CBFS area, and is located at the end of the ROM space.

For an 8MB ROM with a 3MB CBFS area, this would look like: 0x00500000:0x007fffff

IFD_ME_SECTION southbridge/intel/common/firmware string ME/TXE Region Starting:Ending addresses within the ROM

The ME/TXE region typically starts at around 0x1000 and often fills the ROM space not used by CBFS.

For an 8MB ROM with a 3MB CBFS area, this might look like: 0x00001000:0x004fffff

IFD_GBE_SECTION southbridge/intel/common/firmware string GBE Region Starting:Ending addresses within the ROM

The Gigabit Ethernet ROM region is used when an Intel NIC is built into the Southbridge/SOC and the platform uses this device instead of an external PCIe NIC. It will be located between the ME/TXE and the BIOS region.

Leave this empty if you're unsure.

IFD_PLATFORM_SECTION southbridge/intel/common/firmware string Platform Region Starting:Ending addresses within the Rom

The Platform region is used for platform specific data. It will be located between the ME/TXE and the BIOS region.

Leave this empty if you're unsure.

LOCK_MANAGEMENT_ENGINE southbridge/intel/common/firmware bool Lock ME/TXE section

The Intel Firmware Descriptor supports preventing write accesses from the host to the ME or TXE section in the firmware descriptor. If the section is locked, it can only be overwritten with an external SPI flash programmer. You will want this if you want to increase security of your ROM image once you are sure that the ME/TXE firmware is no longer going to change.

If unsure, say N.

CBFS_SIZE southbridge/intel/common/firmware hex

Reduce CBFS size to give room to the IFD blobs.

UDK_VERSION vendorcode/intel int

UEFI Development Kit version for Platform

Menu: AMD Platform Initialization
None vendorcode/amd None AGESA source

Select the method for including the AMD Platform Initialization code into coreboot. Platform Initialization code is required for all AMD processors.

CPU_AMD_AGESA_BINARY_PI vendorcode/amd bool binary PI

Use a binary PI package. Generally, these will be stored in the "3rdparty/blobs" directory. For some processors, these must be obtained directly from AMD Embedded Processors Group (http://www.amdcom/embedded).

CPU_AMD_AGESA_OPENSOURCE vendorcode/amd bool open-source AGESA

Build the PI package ("AGESA") from source code in the "vendorcode" directory.

AGESA_BINARY_PI_VENDORCODE_PATH vendorcode/amd/pi string AGESA PI directory path

Specify where to find the AGESA header files for AMD platform initialization.

AGESA_BINARY_PI_FILE vendorcode/amd/pi string AGESA PI binary file name

Specify the binary file to use for AMD platform initialization.

AGESA_BINARY_PI_AS_STAGE vendorcode/amd/pi bool AGESA Binary PI is added as stage to CBFS.

AGESA will be added as a stage utilizing --xip cbfstool options as needed relocating the image to the proper location in memory-mapped cpu address space. It's required that the file be in ELF format containing the relocations necessary for relocating at runtime.

AGESA_SPLIT_MEMORY_FILES vendorcode/amd/pi bool Split AGESA Binary PI into pre- and post-memory files.

Specifies that AGESA is split into two binaries for pre- and post-memory.

AGESA_PRE_MEMORY_BINARY_PI_FILE vendorcode/amd/pi string

Specify the binary file to use for pre-memory AMD platform initialization.

AGESA_POST_MEMORY_BINARY_PI_FILE vendorcode/amd/pi string

Specify the binary file to use for post-memory AMD platform initialization.

AGESA_BINARY_PI_LOCATION vendorcode/amd/pi hex AGESA PI binary address in ROM

Specify the ROM address at which to store the binary Platform Initialization code.

Menu: ChromeOS
CHROMEOS vendorcode/google/chromeos bool Build for ChromeOS

Enable ChromeOS specific features like the GPIO sub table in the coreboot table. NOTE: Enabling this option on an unsupported board will most likely break your build.

NO_TPM_RESUME vendorcode/google/chromeos bool

On some boards the TPM stays powered up in S3. On those boards, booting Windows will break if the TPM resume command is sent during an S3 resume.

HAVE_REGULATORY_DOMAIN vendorcode/google/chromeos bool Add regulatory domain methods

This option is needed to add ACPI regulatory domain methods

CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME vendorcode/google/chromeos bool

Disable the platform heirarchy on resume path if the firmware is involved in resume. The hierarchy is disabled prior to jumping to the OS. Note that this option is sepcific to TPM2 boards. This option is auto selected if CHROMEOS because it matches with vboot_reference model which disables the platform hierarchy in the boot loader. However, those operations need to be symmetric on normal boot as well as resume and coreboot is only involved in the resume piece w.r.t. the platform hierarchy.

GOOGLE_SMBIOS_MAINBOARD_VERSION vendorcode/google bool

Provide a common implementation for mainboard version, which returns a formatted 'rev%d' board_id() string.

ARCH_RISCV_COMPRESSED arch/riscv bool

Enable this option if your RISC-V processor supports compressed instructions (RVC). Currently, this enables RVC for all stages.

ARCH_ARMV8_EXTENSION arch/arm64/armv8 int

Specify ARMv8 extension, for example '1' for ARMv8.1, to control the '-march' option passed into the compiler. Defaults to 0 for vanilla ARMv8 but may be overridden in the SoC's Kconfig.

All ARMv8 implementations are downwards-compatible, so this does not need to be changed unless specific features (e.g. new instructions) are used by the SoC's coreboot code.

ARM64_SECURE_OS_FILE arch/arm64 string Secure OS binary file

Secure OS binary file.

ARM64_A53_ERRATUM_843419 arch/arm64 bool

Some early Cortex-A53 revisions had a hardware bug that results in incorrect address calculations in rare cases. This option enables a linker workaround to avoid those cases if your toolchain supports it. Should be selected automatically by SoCs that are affected.

USE_MARCH_586 arch/x86 bool

Allow a platform or processor to select to be compiled using the '-march=i586' option instead of the typical '-march=i686'

CBMEM_TOP_BACKUP arch/x86 bool

Platform implements non-volatile storage to cache cbmem_top() over stage transitions and optionally also over S3 suspend.

LATE_CBMEM_INIT arch/x86 bool

Enable this in chipset's Kconfig if northbridge does not implement early cbmem_top() call for romstage. CBMEM tables will be allocated late in ramstage, after PCI devices resources are known.

WARNING: Late CBMEM initialization is deprecated. Platforms that don't support early CBMEM initialization will be removed after the release of coreboot 4.7.

PRERAM_CBMEM_CONSOLE_SIZE arch/x86 hex

Increase this value if preram cbmem console is getting truncated

EARLY_EBDA_INIT arch/x86 bool

Initialize BIOS EBDA area early in romstage to allow bootloader to use this region for storing data which can be available across various stages. If user is selecting this option then its users responsibility to perform EBDA initialization call during romstage.

BOOTBLOCK_DEBUG_SPINLOOP arch/x86 bool

Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait for a JTAG debugger to break into the execution sequence.

BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP arch/x86 bool

Select this value to provide a routine to save the BIST and timestamp values. The default code places the BIST value in MM0 and the timestamp value in MM2:MM1. Another file is necessary when the CPU does not support the MMx register set.

VERSTAGE_DEBUG_SPINLOOP arch/x86 bool

Add a spin (JMP .) in assembly_entry.S during early verstage to wait for a JTAG debugger to break into the execution sequence.

ROMSTAGE_DEBUG_SPINLOOP arch/x86 bool

Add a spin (JMP .) in assembly_entry.S during early romstage to wait for a JTAG debugger to break into the execution sequence.

SKIP_MAX_REBOOT_CNT_CLEAR arch/x86 bool Do not clear reboot count after successful boot

Do not clear the reboot count immediately after successful boot. Set to allow the payload to control normal/fallback image recovery. Note that it is the responsibility of the payload to reset the normal boot bit to 1 after each successsful boot.

ACPI_CPU_STRING arch/x86 string

Sets the ACPI name string in the processor scope as written by the acpigen function. Default is \_PR.CPxx. Note that you need the \ escape character in the string.

COLLECT_TIMESTAMPS_NO_TSC arch/x86 bool

Use a non-TSC platform-dependent source for timestamps.

COLLECT_TIMESTAMPS_TSC arch/x86 bool

Use the TSC as the timestamp source.

PAGING_IN_CACHE_AS_RAM arch/x86 bool

Chipsets scan select this option to preallocate area in cache-as-ram for storing paging data structures. PAE paging is currently the only thing being supported.

NUM_CAR_PAGE_TABLE_PAGES arch/x86 int

The number of 4KiB pages that should be pre-allocated for page tables.

Menu: Devices
HAVE_VGA_TEXT_FRAMEBUFFER device bool

Selected by graphics drivers that support legacy VGA text mode.

HAVE_VBE_LINEAR_FRAMEBUFFER device bool

Selected by graphics drivers that can set up a VBE linear-framebuffer mode.

HAVE_LINEAR_FRAMEBUFFER device bool

Selected by graphics drivers that can set up a generic linear framebuffer.

HAVE_FSP_GOP device bool

Selected by drivers that support to run a blob that implements the Graphics Output Protocol (GOP).

MAINBOARD_HAS_NATIVE_VGA_INIT device bool

Selected by mainboards / drivers that provide native graphics init within coreboot.

MAINBOARD_FORCE_NATIVE_VGA_INIT device bool

Selected by mainboards / chipsets whose graphics driver can't or shouldn't be disabled.

MAINBOARD_HAS_LIBGFXINIT device bool

Selected by mainboards that implement support for `libgfxinit`. Usually this requires a list of ports to be probed for displays.

MAINBOARD_DO_NATIVE_VGA_INIT device bool Use native graphics init

Some mainboards, such as the Google Link, allow initializing the display without the need of a binary only VGA OPROM. Enabling this option may be faster, but also lacks flexibility in setting modes.

MAINBOARD_USE_LIBGFXINIT device bool Use libgfxinit

Use the SPARK library `libgfxinit` for the native graphics initialization. This requires an Ada toolchain.

VGA_ROM_RUN device bool Run VGA Option ROMs

Execute VGA Option ROMs in coreboot if found. This can be used to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS payload.

When using a SeaBIOS payload it runs all option ROMs with much more complete BIOS interrupt services available than coreboot, which some option ROMs require in order to function correctly.

RUN_FSP_GOP device bool Run a GOP driver

Some platforms (e.g. Intel Braswell and Skylake/Kaby Lake) support to run a GOP blob. This option enables graphics initialization with such a blob.

NO_GFX_INIT device bool None

Select this to not perform any graphics initialization in coreboot. This is useful if the payload (e.g. SeaBIOS) can initialize graphics or if pre-boot graphics are not required.

S3_VGA_ROM_RUN device bool Re-run VGA Option ROMs on S3 resume

Execute VGA Option ROMs in coreboot when resuming from S3 suspend.

When using a SeaBIOS payload it runs all option ROMs with much more complete BIOS interrupt services available than coreboot, which some option ROMs require in order to function correctly.

If unsure, say N when using SeaBIOS as payload, Y otherwise.

ALWAYS_LOAD_OPROM device bool

Always load option ROMs if any are found. The decision to run the ROM is still determined at runtime, but the distinction between loading and not running comes into play for CHROMEOS.

An example where this is required is that VBT (Video BIOS Tables) are needed for the kernel's display driver to know how a piece of hardware is configured to be used.

ALWAYS_RUN_OPROM device bool

Always uncondtionally run the option regardless of other policies.

ON_DEVICE_ROM_LOAD device bool Load Option ROMs on PCI devices

Load Option ROMs stored on PCI/PCIe/AGP VGA devices in coreboot.

If disabled, only Option ROMs stored in CBFS will be executed by coreboot. If you are concerned about security, you might want to disable this option, but it might leave your system in a state of degraded functionality.

When using a SeaBIOS payload it runs all option ROMs with much more complete BIOS interrupt services available than coreboot, which some option ROMs require in order to function correctly.

If unsure, say N when using SeaBIOS as payload, Y otherwise.

PCI_OPTION_ROM_RUN_REALMODE device bool Native mode

If you select this option, PCI Option ROMs will be executed natively on the CPU in real mode. No CPU emulation is involved, so this is the fastest, but also the least secure option. (only works on x86/x64 systems)

PCI_OPTION_ROM_RUN_YABEL device bool Secure mode

If you select this option, the x86emu CPU emulator will be used to execute PCI Option ROMs.

This option prevents Option ROMs from doing dirty tricks with the system (such as installing SMM modules or hypervisors), but it is also significantly slower than the native Option ROM initialization method.

This is the default choice for non-x86 systems.

YABEL_PCI_ACCESS_OTHER_DEVICES device bool Allow Option ROMs to access other devices

Per default, YABEL only allows Option ROMs to access the PCI device that they are associated with. However, this causes trouble for some onboard graphics chips whose Option ROM needs to reconfigure the north bridge.

YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG device bool Fake success on writing other device's config space

By default, YABEL aborts when the Option ROM tries to write to other devices' config spaces. With this option enabled, the write doesn't follow through, but the Option ROM is allowed to go on. This can create issues such as hanging Option ROMs (if it depends on that other register changing to the written value), so test for impact before using this option.

YABEL_VIRTMEM_LOCATION device hex Location of YABEL's virtual memory

YABEL requires 1MB memory for its CPU emulation. This memory is normally located at 16MB.

YABEL_DIRECTHW device bool Direct hardware access

YABEL consists of two parts: It uses x86emu for the CPU emulation and additionally provides a PC system emulation that filters bad device and memory access (such as PCI config space access to other devices than the initialized one).

When choosing this option, x86emu will pass through all hardware accesses to memory and I/O devices to the underlying memory and I/O addresses. While this option prevents Option ROMs from doing dirty tricks with the CPU (such as installing SMM modules or hypervisors), they can still access all devices in the system. Enable this option for a good compromise between security and speed.

Menu: Display
FRAMEBUFFER_SET_VESA_MODE device bool Set framebuffer graphics resolution

Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console)

FRAMEBUFFER_SET_VESA_MODE device bool framebuffer graphics resolution

This option sets the resolution used for the coreboot framebuffer (and bootsplash screen).

BOOTSPLASH device bool Show graphical bootsplash

This option shows a graphical bootsplash screen. The graphics are loaded from the CBFS file bootsplash.jpg.

You can either specify the location and file name of the image in the 'General' section or add it manually to CBFS, using, for example, cbfstool.

VGA_TEXT_FRAMEBUFFER device bool Legacy VGA text mode

If this option is enabled, coreboot will initialize graphics in legacy VGA text mode or, if a VGA BIOS is used and a VESA mode set, switch to text mode before handing control to a payload.

VBE_LINEAR_FRAMEBUFFER device bool VESA framebuffer

This option keeps the framebuffer mode set after coreboot finishes execution. If this option is enabled, coreboot will pass a framebuffer entry in its coreboot table and the payload will need a compatible driver.

GENERIC_LINEAR_FRAMEBUFFER device bool Linear \"high-resolution\" framebuffer

This option enables a high-resolution, linear framebuffer. If this option is enabled, coreboot will pass a framebuffer entry in its coreboot table and the payload will need a compatible driver.

PCIEXP_COMMON_CLOCK device bool Enable PCIe Common Clock

Detect and enable Common Clock on PCIe links.

PCIEXP_ASPM device bool Enable PCIe ASPM

Detect and enable ASPM (Active State Power Management) on PCIe links.

PCIEXP_CLK_PM device bool Enable PCIe Clock Power Management

Detect and enable Clock Power Management on PCIe.

PCIEXP_L1_SUB_STATE device bool Enable PCIe ASPM L1 SubState

Detect and enable ASPM on PCIe links.

EARLY_PCI_BRIDGE device bool Early PCI bridge

While coreboot is executing code from ROM, the coreboot resource allocator has not been running yet. Hence PCI devices living behind a bridge are not yet visible to the system.

This option enables static configuration for a single pre-defined PCI bridge function on bus 0.

SUBSYSTEM_VENDOR_ID device hex Override PCI Subsystem Vendor ID

This config option will override the devicetree settings for PCI Subsystem Vendor ID.

SUBSYSTEM_DEVICE_ID device hex Override PCI Subsystem Device ID

This config option will override the devicetree settings for PCI Subsystem Device ID.

VGA_BIOS device bool Add a VGA BIOS image

Select this option if you have a VGA BIOS image that you would like to add to your ROM.

You will be able to specify the location and file name of the image later.

VGA_BIOS_FILE device string VGA BIOS path and filename

The path and filename of the file to use as VGA BIOS.

VGA_BIOS_ID device string VGA device PCI IDs

The comma-separated PCI vendor and device ID that would associate your VGA BIOS to your video card.

Example: 1106,3230

In the above example 1106 is the PCI vendor ID (in hex, but without the "0x" prefix) and 3230 specifies the PCI device ID of the video card (also in hex, without "0x" prefix).

Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.

INTEL_GMA_ADD_VBT_DATA_FILE device bool Add a Video Bios Table (VBT) binary to CBFS

Add a VBT data file to CBFS. The VBT describes the integrated GPU and connections, and is needed by the GOP driver integrated into FSP and the OS driver in order to initialize the display.

INTEL_GMA_VBT_FILE device string VBT binary path and filename

The path and filename of the VBT binary.

SOFTWARE_I2C device bool Enable I2C controller emulation in software

This config option will enable code to override the i2c_transfer routine with a (simple) software emulation of the protocol. This may be useful for debugging or on platforms where a driver for the real I2C controller is not (yet) available. The platform code needs to provide bindings to manually toggle I2C lines.

Menu: Generic Drivers
ELOG drivers/elog bool Support for flash based event log

Enable support for flash based event logging.

ELOG_CBMEM drivers/elog bool Store a copy of ELOG in CBMEM

This option will have ELOG store a copy of the flash event log in a CBMEM region and export that address in SMBIOS to the OS. This is useful if the ELOG location is not in memory mapped flash, but it means that events added at runtime via the SMI handler will not be reflected in the CBMEM copy of the log.

ELOG_GSMI drivers/elog bool SMI interface to write and clear event log

This interface is compatible with the linux kernel driver available with CONFIG_GOOGLE_GSMI and can be used to write kernel reset/shutdown messages to the event log.

ELOG_BOOT_COUNT drivers/elog bool Maintain a monotonic boot number in CMOS

Store a monotonic boot number in CMOS and provide an interface to read the current value and increment the counter. This boot counter will be logged as part of the System Boot event.

ELOG_BOOT_COUNT_CMOS_OFFSET drivers/elog int Offset in CMOS to store the boot count

This value must be greater than 16 bytes so as not to interfere with the standard RTC region. Requires 8 bytes.

USBDEBUG drivers/usb bool USB 2.0 EHCI debug dongle support

This option allows you to use a so-called USB EHCI Debug device (such as the Ajays NET20DC, AMIDebug RX, or a system using the Linux "EHCI Debug Device gadget" driver found in recent kernel) to retrieve the coreboot debug messages (instead, or in addition to, a serial port).

This feature is NOT supported on all chipsets in coreboot!

It also requires a USB2 controller which supports the EHCI Debug Port capability.

See https://www.coreboot.org/EHCI_Debug_Port for an up-to-date list of supported controllers.

If unsure, say N.

USBDEBUG_IN_ROMSTAGE drivers/usb bool Enable early (pre-RAM) usbdebug

Configuring USB controllers in system-agent binary may cause problems to usbdebug. Disabling this option delays usbdebug to be setup on entry to ramstage.

If unsure, say Y.

USBDEBUG_HCD_INDEX drivers/usb int Index for EHCI controller to use with usbdebug

Some boards have multiple EHCI controllers with possibly only one having the Debug Port capability on an external USB port.

Mapping of this index to PCI device functions is southbridge specific and mainboard level Kconfig should already provide a working default value here.

USBDEBUG_DEFAULT_PORT drivers/usb int Default USB port to use as Debug Port

Selects which physical USB port usbdebug dongle is connected to. Setting of 0 means to scan possible ports starting from 1.

Intel platforms have hardwired the debug port location and this setting makes no difference there.

Hence, if you select the correct port here, you can speed up your boot time. Which USB port number refers to which actual port on your mainboard (potentially also USB pin headers on your mainboard) is highly board-specific, and you'll likely have to find out by trial-and-error.

USBDEBUG_DONGLE_STD drivers/usb bool USB gadget driver or Net20DC

Net20DC, BeagleBone Black, Raspberry Pi Zero W

USBDEBUG_DONGLE_BEAGLEBONE drivers/usb bool BeagleBone

Use this to configure the USB hub on BeagleBone board. Do NOT select this for the BeagleBone Black.

USBDEBUG_DONGLE_FTDI_FT232H drivers/usb bool FTDI FT232H UART

Use this with FT232H usb-to-uart. Configuration is hard-coded to use 8n1, no flow control.

USBDEBUG_DONGLE_FTDI_FT232H_BAUD drivers/usb int FTDI FT232H baud rate

Select baud rate for FT232H in the range 733..12,000,000. Make sure that your receiving side supports the same setting and your connection works with it. Multiples of 115,200 seem to be a good choice, and EHCI debug usually can't saturate more than 576,000.

COMMON_CBFS_SPI_WRAPPER drivers/spi bool

Use common wrapper to interface CBFS to SPI bootrom.

SPI_FLASH drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash.

BOOT_DEVICE_SPI_FLASH_BUS drivers/spi int

Which SPI bus the boot device is connected to.

BOOT_DEVICE_SPI_FLASH_RW_NOMMAP drivers/spi bool

Provide common implementation of the RW boot device that doesn't provide mmap() operations.

BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY drivers/spi bool

Include the common implementation in all stages, including the early ones.

SPI_FLASH_SMM drivers/spi bool SPI flash driver support in SMM

Select this option if you want SPI flash support in SMM.

SPI_FLASH_NO_FAST_READ drivers/spi bool Disable Fast Read command

Select this option if your setup requires to avoid "fast read"s from the SPI flash parts.

SPI_FLASH_ADESTO drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Adesto Technologies.

SPI_FLASH_AMIC drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by AMIC.

SPI_FLASH_ATMEL drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Atmel.

SPI_FLASH_EON drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by EON.

SPI_FLASH_GIGADEVICE drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Gigadevice.

SPI_FLASH_MACRONIX drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Macronix.

SPI_FLASH_SPANSION drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Spansion.

SPI_FLASH_SST drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by SST.

SPI_FLASH_STMICRO drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by ST MICRO.

SPI_FLASH_WINBOND drivers/spi bool

Select this option if your chipset driver needs to store certain data in the SPI flash and your SPI flash is made by Winbond.

SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B drivers/spi bool

Select this option if your SPI flash supports the fast read dual- output command (opcode 0x3b) where the opcode and address are sent to the chip on MOSI and data is received on both MOSI and MISO.

SPI_FLASH_HAS_VOLATILE_GROUP drivers/spi bool

Allows chipset to group write/erase operations under a single volatile group.

CACHE_MRC_SETTINGS drivers/mrc_cache bool

Save cached MRC settings

MRC_WRITE_NV_LATE drivers/mrc_cache bool

MRC settings are normally written to NVRAM at BS_DEV_ENUMERATE-EXIT. If a platform requires MRC settings written to NVRAM later than normal, select this item. This will cause the write to occur at BS_OS_RESUME_CHECK-ENTRY.

DIGITIZER_AUTODETECT drivers/lenovo bool Autodetect

The presence of digitizer is inferred from model number stored in AT24RF chip.

DIGITIZER_PRESENT drivers/lenovo bool Present

The digitizer is assumed to be present.

DIGITIZER_ABSENT drivers/lenovo bool Absent

The digitizer is assumed to be absent.

UART_OVERRIDE_INPUT_CLOCK_DIVIDER drivers/uart boolean

Set to "y" when the platform overrides the uart_input_clock_divider routine.

UART_OVERRIDE_REFCLK drivers/uart boolean

Set to "y" when the platform overrides the uart_platform_refclk routine.

DRIVERS_UART_OXPCIE drivers/uart bool Oxford OXPCIe952

Support for Oxford OXPCIe952 serial port PCIe cards. Currently only devices with the vendor ID 0x1415 and device ID 0xc158 or 0xc11b will work.

UART_USE_REFCLK_AS_INPUT_CLOCK drivers/uart bool

Use uart_platform_refclk to specify the input clock value.

UART_PCI_ADDR drivers/uart hex UART's PCI bus, device, function address

Specify zero if the UART is connected to another bus type. For PCI based UARTs, build the value as:

  • 1 << 31 - Valid bit, PCI UART in use
  • Bus << 20
  • Device << 15
  • Function << 12
GIC drivers/gic None

This option enables GIC support, the ARM generic interrupt controller.

REALTEK_8168_RESET drivers/net bool

This forces a realtek 10ec:8168 card to reset to ensure power state is correct at boot.

REALTEK_8168_MACADDRESS drivers/net string Realtek rt8168 mac address

This is a string to set the mac address on a Realtek rt8168 card. It must be in the form of "xx:xx:xx:xx:xx:xx", where x is a hexadecimal number for it to be valid. Failing to do so will result in the default macaddress being used.

RT8168_SET_LED_MODE drivers/net bool

This is to set a customized LED mode to distinguish 10/100/1000 link and speed status with limited LEDs avaiable on a board. Please refer to RTL811x datasheet section 7.2 Customizable LED Configuration for details. With this flag enabled, the customized_leds variable will be read from devicetree setting.

DRIVERS_PS2_KEYBOARD drivers/pc80/pc bool PS/2 keyboard init

Enable this option to initialize PS/2 keyboards found connected to the PS/2 port.

Some payloads (eg, filo) require this option. Other payloads (eg, GRUB 2, SeaBIOS, Linux) do not require it. Initializing a PS/2 keyboard can take several hundred milliseconds.

If you know you will only use a payload which does not require this option, then you can say N here to speed up boot time. Otherwise say Y.

VGA drivers/pc80/vga bool

Include legacy VGA support code.

LPC_TPM drivers/pc80/tpm bool Enable TPM support

Enable this option to enable LPC TPM support in coreboot.

If unsure, say N.

TPM_TIS_BASE_ADDRESS drivers/pc80/tpm hex

This can be used to adjust the TPM memory base address. The default is specified by the TCG PC Client Specific TPM Interface Specification 1.2 and should not be changed unless the TPM being used does not conform to TPM TIS 1.2.

TPM_PIRQ drivers/pc80/tpm hex

This can be used to specify a PIRQ to use instead of SERIRQ, which is needed for SPI TPM interrupt support on x86.

TPM_INIT_FAILURE_IS_FATAL drivers/pc80/tpm bool

What to do if TPM init failed. If true, force a hard reset, otherwise just log error message to console.

SKIP_TPM_STARTUP_ON_NORMAL_BOOT drivers/pc80/tpm bool

Skip TPM init on normal boot. Useful if payload does TPM init.

TPM_DEACTIVATE drivers/pc80/tpm bool Deactivate TPM

Deactivate TPM by issuing deactivate command.

TPM_RDRESP_NEED_DELAY drivers/pc80/tpm bool Enable Delay Workaround for TPM

Certain TPMs seem to need some delay when reading response to work around a race-condition-related issue, possibly caused by ill-programmed TPM firmware.

PLATFORM_USES_FSP1_1 drivers/intel/fsp1_1 bool

Does the code require the Intel Firmware Support Package?

(comment) Intel FSP 1.1
HAVE_FSP_BIN drivers/intel/fsp1_1 bool Should the Intel FSP binary be added to the flash image

Select this option to add an Intel FSP binary to the resulting coreboot image.

Note: Without this binary, coreboot builds relying on the FSP will not boot

CPU_MICROCODE_CBFS_LEN drivers/intel/fsp1_1 hex Microcode update region length in bytes

The length in bytes of the microcode update region.

CPU_MICROCODE_CBFS_LOC drivers/intel/fsp1_1 hex Microcode update base address in CBFS

The location (base address) in CBFS that contains the microcode update binary.

FSP_FILE drivers/intel/fsp1_1 string Intel FSP binary path and filename

The path and filename of the Intel FSP binary for this platform.

FSP_LOC drivers/intel/fsp1_1 hex Intel FSP Binary location in CBFS

The location in CBFS that the FSP is located. This must match the value that is set in the FSP binary. If the FSP needs to be moved, rebase the FSP with Intel's BCT (tool).

DISPLAY_UPD_DATA drivers/intel/fsp1_1 bool Display UPD data

Display the user specified product data prior to memory initialization.

FSP_USES_UPD drivers/intel/fsp1_1 bool

If this FSP uses UPD/VPD data regions, select this in the chipset Kconfig.

USE_GENERIC_FSP_CAR_INC drivers/intel/fsp1_1 bool

The chipset can select this to use a generic cache_as_ram.inc file that should be good for all FSP based platforms.

INTEL_DDI drivers/intel/gma bool

helper functions for intel DDI operations

INTEL_GMA_SSC_ALTERNATE_REF drivers/intel/gma bool

Set when the SSC reference clock for LVDS runs at a different fre- quency than the general display reference clock.

To be set by northbridge or mainboard Kconfig. For most platforms, there is no choice, i.e. for i945 and gm45 the SSC reference always differs from the display reference clock (i945: 66Mhz SSC vs. 48MHz DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Nehalem and newer, it's the same frequency for SSC/non-SSC (120MHz). The only, currently supported platform with a choice seems to be Pineview, where the alternative is 100MHz vs. the default 96MHz.

INTEL_GMA_SWSMISCI drivers/intel/gma bool

Select this option for Atom-based platforms which use the SWSMISCI register (0xe0) rather than the SWSCI register (0xe8).

GFX_GMA_ANALOG_I2C_PORT drivers/intel/gma string

Boards with a DVI-I connector share the I2C pins for both analog and digital displays. In that case, the EDID for a VGA display has to be read over the I2C interface of the coupled digital port.

DRIVERS_INTEL_MIPI_CAMERA drivers/intel/mipi_camera bool

MIPI CSI I2C camera SSDT generator. Generates SSDB and PWDB structures which are used by the Intel kernel drivers.

(comment) Intel FSP
HAVE_FSP_BIN drivers/intel/fsp1_0 bool Use Intel Firmware Support Package

Select this option to add an Intel FSP binary to the resulting coreboot image.

Note: Without this binary, coreboot builds relying on the FSP will not boot

FSP_FILE drivers/intel/fsp1_0 string Intel FSP binary path and filename

The path and filename of the Intel FSP binary for this platform.

FSP_LOC drivers/intel/fsp1_0 hex Intel FSP Binary location in CBFS

The location in CBFS that the FSP is located. This must match the value that is set in the FSP binary. If the FSP needs to be moved, rebase the FSP with Intel's BCT (tool).

ENABLE_FSP_FAST_BOOT drivers/intel/fsp1_0 bool Enable Fast Boot

Enabling this feature will force the MRC data to be cached in NV storage to be used for speeding up boot time on future reboots and/or power cycles.

ENABLE_MRC_CACHE drivers/intel/fsp1_0 bool

Enabling this feature will cause MRC data to be cached in NV storage. This can either be used for fast boot, or just because the FSP wants it to be saved.

MRC_CACHE_FMAP drivers/intel/fsp1_0 bool Use MRC Cache in FMAP

Use the region "RW_MRC_CACHE" in FMAP instead of "mrc.cache" in CBFS. You must define a region in your FMAP named "RW_MRC_CACHE".

MRC_CACHE_SIZE drivers/intel/fsp1_0 hex Fast Boot Data Cache Size

This is the amount of space in NV storage that is reserved for the fast boot data cache storage.

WARNING: Because this area will be erased and re-written, the size should be a full sector of the flash ROM chip and nothing else should be included in CBFS in any sector that the fast boot cache data is in.

VIRTUAL_ROM_SIZE drivers/intel/fsp1_0 hex Virtual ROM Size

This is used to calculate the offset of the MRC data cache in NV Storage for fast boot. If in doubt, leave this set to the default which sets the virtual size equal to the ROM size.

Example: Cougar Canyon 2 has two 8 MB SPI ROMs. When the SPI ROMs are loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB. When the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM size is 16 MB.

CACHE_ROM_SIZE_OVERRIDE drivers/intel/fsp1_0 hex Cache ROM Size

This is the size of the cachable area that is passed into the FSP in the early initialization. Typically this should be the size of the CBFS area, but the size must be a power of 2 whereas the CBFS size does not have this limitation.

USE_GENERIC_FSP_CAR_INC drivers/intel/fsp1_0 bool

The chipset can select this to use a generic cache_as_ram.inc file that should be good for all FSP based platforms.

FSP_USES_UPD drivers/intel/fsp1_0 bool

If this FSP uses UPD/VPD data regions, select this in the chipset Kconfig.

DRIVERS_INTEL_WIFI drivers/intel/wifi bool Support Intel PCI-e WiFi adapters

When enabled, add identifiers in ACPI and SMBIOS tables to make OS drivers work with certain Intel PCI-e WiFi chipsets.

USE_SAR drivers/intel/wifi bool

Enable it when wifi driver uses SAR configuration feature. VPD entry "wifi_sar" is required to support it.

DSAR_SET_NUM drivers/intel/wifi hex Number of SAR sets when D-SAR is enabled

There can be up to 3 optional SAR table sets.

PLATFORM_USES_FSP2_0 drivers/intel/fsp2_0 bool

Include FSP 2.0 wrappers and functionality

ADD_FSP_BINARIES drivers/intel/fsp2_0 bool Add Intel FSP 2.0 binaries to CBFS

Add the FSP-M and FSP-S binaries to CBFS. Currently coreboot does not use the FSP-T binary and it is not added.

DISPLAY_FSP_CALLS_AND_STATUS drivers/intel/fsp2_0 bool Display the FSP calls and status

Display the FSP call entry point and parameters prior to calling FSP and display the status upon return from FSP.

DISPLAY_FSP_HEADER drivers/intel/fsp2_0 bool Display the FSP header

Display the FSP header information when the FSP file is found.

DISPLAY_HOBS drivers/intel/fsp2_0 bool Display the hand-off-blocks

Display the FSP HOBs which are provided for coreboot.

DISPLAY_UPD_DATA drivers/intel/fsp2_0 bool Display UPD data

Display the user specified product data prior to memory initialization.

FSP_T_FILE drivers/intel/fsp2_0 string Intel FSP-T (temp ram init) binary path and filename

The path and filename of the Intel FSP-M binary for this platform.

FSP_M_FILE drivers/intel/fsp2_0 string Intel FSP-M (memory init) binary path and filename

The path and filename of the Intel FSP-M binary for this platform.

FSP_S_FILE drivers/intel/fsp2_0 string Intel FSP-S (silicon init) binary path and filename

The path and filename of the Intel FSP-S binary for this platform.

FSP_CAR drivers/intel/fsp2_0 bool Use FSP TempRamInit & TempRamExit APIs

Use FSP APIs to initialize & Tear Down the Cache-As-Ram

FSP_M_XIP drivers/intel/fsp2_0 bool Is FSP-M XIP

Select this value when FSP-M is execute-in-place.

VERIFY_HOBS drivers/intel/fsp2_0 bool Verify the FSP hand-off-blocks

Verify that the HOBs required by coreboot are returned by FSP and that the resource HOBs are in the correct order and position.

DISPLAY_FSP_VERSION_INFO drivers/intel/fsp2_0 bool Display Firmware Ingredient Version Information

Select this option to display Firmware version information.

FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS drivers/intel/fsp2_0 bool

This is selected by SoC or mainboard to supply their own concept of a version for the memory settings respectively. This allows deployed systems to bump their version number with the same FSP which will trigger a retrain of the memory.

DRIVERS_SIL_3114 drivers/sil/3114 bool Silicon Image SIL3114

It sets PCI class to IDE compatible native mode, allowing SeaBIOS, FILO etc... to boot from it.

DRIVER_TI_TPS65090 drivers/ti/tps65090 bool

TI TPS65090

DRIVERS_EMULATION_QEMU_BOCHS drivers/emulation/qemu bool bochs dispi interface vga driver

VGA driver for qemu emulated vga cards supporting the bochs dispi interface. This includes standard vga, vmware svga and qxl. The default vga (cirrus) is *not* supported, so you have to pick another one explicitly via 'qemu -vga $card'.

DRIVER_XPOWERS_AXP209 drivers/xpowers/axp209 bool

X-Powers AXP902 Power Management Unit

DRIVER_XPOWERS_AXP209_BOOTBLOCK drivers/xpowers/axp209 bool

Make AXP209 functionality available in he bootblock.

DRIVER_PARADE_PS8640 drivers/parade/ps8640 bool

Parade PS8640 MIPI DSI to eDP Converter

DRIVER_PARADE_PS8625 drivers/parade/ps8625 bool

Parade ps8625 display port to lvds bridge

DRIVER_MAXIM_MAX77686 drivers/maxim/max77686 bool

Maxim MAX77686 power regulator

DRIVERS_I2C_PCA9538 drivers/i2c/pca9538 bool

Enable support for I2C I/O expander PCA9538.

DRIVERS_I2C_RX6110SA drivers/i2c/rx6110sa bool

Enable support for external RTC chip RX6110 SA.

DRIVERS_I2C_DESIGNWARE drivers/i2c/designware bool

Designware I2C support

DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ drivers/i2c/designware int

The i2c ip block's clock.

DRIVERS_I2C_RTD2132 drivers/i2c/rtd2132 bool

Enable support for Realtek RTD2132 DisplayPort to LVDS bridge chip.

STORAGE_ERASE commonlib/storage bool Support SD/MMC erase operations

Select to enable SD/MMC erase oprations

STORAGE_WRITE commonlib/storage bool Support SD/MMC write operations

Select to enable SD/MMC write oprations

SD_MMC_DEBUG commonlib/storage bool Debug SD/MMC card/devices operations

Display overview of SD/MMC card/device operations

SD_MMC_TRACE commonlib/storage bool Trace SD/MMC card/device operations

Display details of SD/MMC card/device operations

SDHC_DEBUG commonlib/storage bool Debug SD/MMC controller settings

Display clock speed and bus width settings

SDHC_TRACE commonlib/storage bool Trace SD/MMC controller operations

Display the operations performed by the SD/MMC controller

SDHCI_ADMA_IN_BOOTBLOCK commonlib/storage bool

Determine if bootblock is able to use ADMA2 or ADMA64

SDHCI_ADMA_IN_ROMSTAGE commonlib/storage bool

Determine if romstage is able to use ADMA2 or ADMA64

SDHCI_ADMA_IN_VERSTAGE commonlib/storage bool

Determine if verstage is able to use ADMA2 or ADMA64

Menu: Security
Menu: Verified Boot (vboot)
VBOOT security/vboot bool Verify firmware with vboot.

Enabling VBOOT will use vboot to verify the components of the firmware (stages, payload, etc).

VBOOT_VBNV_CMOS security/vboot bool

VBNV is stored in CMOS

VBOOT_VBNV_OFFSET security/vboot hex

CMOS offset for VbNv data. This value must match cmos.layout in the mainboard directory, minus 14 bytes for the RTC.

VBOOT_VBNV_CMOS_BACKUP_TO_FLASH security/vboot bool

Vboot non-volatile storage data will be backed up from CMOS to flash and restored from flash if the CMOS is invalid due to power loss.

VBOOT_VBNV_EC security/vboot bool

VBNV is stored in EC

VBOOT_VBNV_FLASH security/vboot bool

VBNV is stored in flash storage

VBOOT_STARTS_IN_BOOTBLOCK security/vboot bool

Firmware verification happens during the end of or right after the bootblock. This implies that a static VBOOT2_WORK() buffer must be allocated in memlayout.

VBOOT_STARTS_IN_ROMSTAGE security/vboot bool

Firmware verification happens during the end of romstage (after memory initialization). This implies that vboot working data is allocated in CBMEM.

VBOOT_MOCK_SECDATA security/vboot bool Mock secdata for firmware verification

Enabling VBOOT_MOCK_SECDATA will mock secdata for the firmware verification to avoid access to a secdata storage (typically TPM). All operations for a secdata storage will be successful. This option can be used during development when a TPM is not present or broken. THIS SHOULD NOT BE LEFT ON FOR PRODUCTION DEVICES.

VBOOT_DISABLE_DEV_ON_RECOVERY security/vboot bool

When this option is enabled, the Chrome OS device leaves the developer mode as soon as recovery request is detected. This is handy on embedded devices with limited input capabilities.

VBOOT_SEPARATE_VERSTAGE security/vboot bool

If this option is set, vboot verification runs in a standalone stage that is loaded from the bootblock and exits into romstage. If it is not set, the verification code is linked directly into the bootblock or the romstage and runs as part of that stage (cf. related options VBOOT_STARTS_IN_BOOTBLOCK/_ROMSTAGE and VBOOT_RETURN_FROM_VERSTAGE).

VBOOT_RETURN_FROM_VERSTAGE security/vboot bool

If this is set, the verstage returns back to the calling stage instead of exiting to the succeeding stage so that the verstage space can be reused by the succeeding stage. This is useful if a RAM space is too small to fit both the verstage and the succeeding stage.

VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT security/vboot bool

This option ensures that the recovery request is not lost because of reboots caused after vboot verification is run. e.g. reboots caused by FSP components on Intel platforms.

VBOOT_OPROM_MATTERS security/vboot bool

Set this option to indicate to vboot that this platform will skip its display initialization on a normal (non-recovery, non-developer) boot. Vboot calls this "oprom matters" because on x86 devices this traditionally meant that the video option ROM will not be loaded, but it works functionally the same for other platforms that can skip their native display initialization code instead.

VBOOT_HAS_REC_HASH_SPACE security/vboot bool

Set this option to indicate to vboot that recovery data hash space is present in TPM.

VBOOT_EC_SOFTWARE_SYNC security/vboot bool Enable EC software sync

EC software sync is a mechanism where the AP helps the EC verify its firmware similar to how vboot verifies the main system firmware. This option selects whether vboot should support EC software sync.

VBOOT_EC_SLOW_UPDATE security/vboot bool

Whether the EC (or PD) is slow to update and needs to display a screen that informs the user the update is happening.

VBOOT_EC_EFS security/vboot bool

CrosEC can support EFS: Early Firmware Selection. If it's enabled, software sync need to also support it. This setting tells vboot to perform EFS software sync.

VBOOT_PHYSICAL_DEV_SWITCH security/vboot bool

Whether this platform has a physical developer switch. Note that this disables virtual dev switch functionality (through secdata). Operation where both a physical pin and the virtual switch get sampled is not supported by coreboot.

VBOOT_PHYSICAL_REC_SWITCH security/vboot bool

Whether this platform has a physical recovery switch.

VBOOT_LID_SWITCH security/vboot bool

Whether this platform has a lid switch. If it does, vboot will not decrement try counters for boot failures if the lid is closed.

VBOOT_WIPEOUT_SUPPORTED security/vboot bool

When this option is enabled, the firmware provides the ability to signal the application the need for factory reset (a.k.a. wipe out) of the device

VBOOT_FWID_MODEL security/vboot string Firmware ID model

This is the first part of the FWID written to various regions of a vboot firmware image to identify its version.

VBOOT_FWID_VERSION security/vboot string Firmware ID version

This is the second part of the FWID written to various regions of a vboot firmware image to identify its version.

VBOOT_NO_BOARD_SUPPORT security/vboot bool Allow the use of vboot without board support

Enable weak functions for get_write_protect_state and get_recovery_mode_switch in order to proceed with refactoring of the vboot2 code base. Later on this code is removed and replaced by interfaces.

RO_REGION_ONLY security/vboot string Additional files that should not be copied to RW

Add a space delimited list of filenames that should only be in the RO section.

Menu: GBB configuration
Menu: Vboot Keys


Menu: Trusted Platform Module
TPM security/tpm bool

Enable this option to enable TPM support in coreboot.

If unsure, say N.

TPM2 security/tpm bool

Enable this option to enable TPM2 support in coreboot.

If unsure, say N.

DEBUG_TPM security/tpm bool Output verbose TPM debug messages

This option enables additional TPM related debug messages.

POWER_OFF_ON_CR50_UPDATE security/tpm bool

Power off machine while waiting for CR50 update to take effect.

MAINBOARD_HAS_LPC_TPM security/tpm bool

Board has TPM support

MAINBOARD_HAS_TPM2 security/tpm bool

There is a TPM device installed on the mainboard, and it is compliant with version 2 TCG TPM specification. Could be connected over LPC, SPI or I2C.


ACPI_SATA_GENERATOR acpi bool

Use ACPI SATA port generator.

ACPI_INTEL_HARDWARE_SLEEP_VALUES acpi bool

Provide common definitions for Intel hardware PM1_CNT register sleep values.

ACPI_AMD_HARDWARE_SLEEP_VALUES acpi bool

Provide common definitions for AMD hardware PM1_CNT register sleep values.

BOOT_DEVICE_MEMORY_MAPPED toplevel bool

Inform system if SPI is memory-mapped or not.

BOOT_DEVICE_SUPPORTS_WRITES toplevel bool

Indicate that the platform has writable boot device support.

Menu: Console
BOOTBLOCK_CONSOLE console bool Enable early (bootblock) console output.

Use console during the bootblock if supported

POSTCAR_CONSOLE console bool Enable console output during postcar.

Use console during the postcar if supported

SQUELCH_EARLY_SMP console bool Squelch AP CPUs from early console.

When selected only the BSP CPU will output to early console.

Console drivers have unpredictable behaviour if multiple threads attempt to share the same resources without a spinlock.

If unsure, say Y.

CONSOLE_SERIAL console bool Serial port console output

Send coreboot debug output to a serial port.

The type of serial port driver selected based on your configuration is shown on the following menu line. Supporting multiple different types of UARTs in one build is not supported.

(comment) I/O mapped, 8250-compatible
(comment) memory mapped, 8250-compatible
(comment) device-specific UART
UART_FOR_CONSOLE console int Index for UART port to use for console

Select an I/O port to use for serial console: 0 = 0x3f8, 1 = 0x2f8, 2 = 0x3e8, 3 = 0x2e8

TTYS0_BASE console hex

Map the COM port number to the respective I/O port.

(comment) Serial port base address = 0x3f8
(comment) Serial port base address = 0x2f8
(comment) Serial port base address = 0x3e8
(comment) Serial port base address = 0x2e8
UART_OVERRIDE_BAUDRATE console boolean

Set to "y" when the platform overrides the baudrate by providing a get_uart_baudrate routine.

CONSOLE_SERIAL_921600 console bool 921600

Set serial port Baud rate to 921600.

CONSOLE_SERIAL_460800 console bool 460800

Set serial port Baud rate to 460800.

CONSOLE_SERIAL_230400 console bool 230400

Set serial port Baud rate to 230400.

CONSOLE_SERIAL_115200 console bool 115200

Set serial port Baud rate to 115200.

CONSOLE_SERIAL_57600 console bool 57600

Set serial port Baud rate to 57600.

CONSOLE_SERIAL_38400 console bool 38400

Set serial port Baud rate to 38400.

CONSOLE_SERIAL_19200 console bool 19200

Set serial port Baud rate to 19200.

CONSOLE_SERIAL_9600 console bool 9600

Set serial port Baud rate to 9600.

TTYS0_BAUD console int

Map the Baud rates to an integer.

SPKMODEM console bool spkmodem (console on speaker) console output

Send coreboot debug output through speaker

CONSOLE_USB console bool USB dongle console output

Send coreboot debug output to USB.

Configuration for USB hardware is under menu Generic Drivers.

ONBOARD_VGA_IS_PRIMARY console bool Use onboard VGA as primary video device

If not selected, the last adapter found will be used.

CONSOLE_NE2K console bool Network console over NE2000 compatible Ethernet adapter

Send coreboot debug output to a Ethernet console, it works same way as Linux netconsole, packets are received to UDP port 6666 on IP/MAC specified with options bellow. Use following netcat command: nc -u -l -p 6666

CONSOLE_NE2K_DST_MAC console string Destination MAC address of remote system

Type in either MAC address of logging system or MAC address of the router.

CONSOLE_NE2K_DST_IP console string Destination IP of logging system

This is IP address of the system running for example netcat command to dump the packets.

CONSOLE_NE2K_SRC_IP console string IP address of coreboot system

This is the IP of the coreboot system

CONSOLE_NE2K_IO_PORT console hex NE2000 adapter fixed IO port address

This is the IO port address for the IO port on the card, please select some non-conflicting region, 32 bytes of IO spaces will be used (and align on 32 bytes boundary, qemu needs broader align)

CONSOLE_CBMEM console bool Send console output to a CBMEM buffer

Enable this to save the console output in a CBMEM buffer. This would allow to see coreboot console output from Linux space.

CONSOLE_CBMEM_BUFFER_SIZE console hex Room allocated for console output in CBMEM

Space allocated for console output storage in CBMEM. The default value (128K or 0x20000 bytes) is large enough to accommodate even the BIOS_SPEW level.

CONSOLE_CBMEM_DUMP_TO_UART console bool Dump CBMEM console on resets

Enable this to have CBMEM console buffer contents dumped on the serial output in case serial console is disabled and the device resets itself while trying to boot the payload.

CONSOLE_SPI_FLASH console bool SPI Flash console output

Send coreboot debug output to the SPI Flash in the FMAP CONSOLE area

This option can cause premature wear on the SPI flash and should not be used as a normal means of debugging. It is only to be enabled and used when porting a new motherboard which has no other console available (no UART, no POST, no cbmem access(non bootable)). Since a non bootable machine will require the use of an external SPI Flash programmer, the developer can grab the console log at the same time.

The flash console will not be erased on reboot, so once it is full, the flashconsole driver will stop writing to it. This is to avoid wear on the flash, and to avoid erasing sectors (which may freeze the SPI controller on skylake).

The 'CONSOLE' area can be extracted from the FMAP with : cbfstool rom.bin read -r CONSOLE -f console.log

CONSOLE_SPI_FLASH_BUFFER_SIZE console hex Room allocated for console output in FMAP

Space allocated for console output storage in FMAP. The default value (128K or 0x20000 bytes) is large enough to accommodate even the BIOS_SPEW level.

CONSOLE_QEMU_DEBUGCON console bool QEMU debug console output

Send coreboot debug output to QEMU's isa-debugcon device:

qemu-system-x86_64 \ -chardev file,id=debugcon,path=/dir/file.log \ -device isa-debugcon,iobase=0x402,chardev=debugcon

SPI_CONSOLE console bool SPI debug console output

Enable support for the debug console on the Dediprog EM100Pro. This is currently working only in ramstage due to how the spi drivers are written.

CONSOLE_OVERRIDE_LOGLEVEL console boolean

Set to "y" when the platform overrides the loglevel by providing a get_console_loglevel routine.

DEFAULT_CONSOLE_LOGLEVEL_8 console bool 8: SPEW

Way too many details.

DEFAULT_CONSOLE_LOGLEVEL_7 console bool 7: DEBUG

Debug-level messages.

DEFAULT_CONSOLE_LOGLEVEL_6 console bool 6: INFO

Informational messages.

DEFAULT_CONSOLE_LOGLEVEL_5 console bool 5: NOTICE

Normal but significant conditions.

DEFAULT_CONSOLE_LOGLEVEL_4 console bool 4: WARNING

Warning conditions.

DEFAULT_CONSOLE_LOGLEVEL_3 console bool 3: ERR

Error conditions.

DEFAULT_CONSOLE_LOGLEVEL_2 console bool 2: CRIT

Critical conditions.

DEFAULT_CONSOLE_LOGLEVEL_1 console bool 1: ALERT

Action must be taken immediately.

DEFAULT_CONSOLE_LOGLEVEL_0 console bool 0: EMERG

System is unusable.

DEFAULT_CONSOLE_LOGLEVEL console int

Map the log level config names to an integer.

CMOS_POST console bool Store post codes in CMOS for debugging

If enabled, coreboot will store post codes in CMOS and switch between two offsets on each boot so the last post code in the previous boot can be retrieved. This uses 3 bytes of CMOS.

CMOS_POST_OFFSET console hex Offset into CMOS to store POST codes

If CMOS_POST is enabled then an offset into CMOS must be provided. If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value defined in the mainboard option table.

CMOS_POST_EXTRA console bool Store extra logging info into CMOS

This will enable extra logging of work that happens between post codes into CMOS for debug. This uses an additional 8 bytes of CMOS.

CONSOLE_POST console bool Show POST codes on the debug console

If enabled, coreboot will additionally print POST codes (which are usually displayed using a so-called "POST card" ISA/PCI/PCI-E device) on the debug console.

POST_IO console bool Send POST codes to an IO port

If enabled, POST codes will be written to an IO port.

POST_IO_PORT console hex IO port for POST codes

POST codes on x86 are typically written to the LPC bus on port 0x80. However, it may be desirable to change the port number depending on the presence of coprocessors/microcontrollers or if the platform does not support IO in the conventional x86 manner.

NO_EARLY_BOOTBLOCK_POSTCODES console hex

Some chipsets require that the routing for the port 80h POST code be configured before any POST codes are sent out. This can be done in the boot block, but there are a couple of POST codes that go out before the chipset's bootblock initialization can happen. This option suppresses those POST codes.

ACPI_HUGE_LOWMEM_BACKUP toplevel bool

On S3 resume path, backup low memory from RAMBASE..RAMTOP in CBMEM.

RESUME_PATH_SAME_AS_BOOT toplevel bool

This option indicates that when a system resumes it takes the same path as a regular boot. e.g. an x86 system runs from the reset vector at 0xfffffff0 on both resume and warm/cold boot.

HAVE_HARD_RESET toplevel bool

This variable specifies whether a given board has a hard_reset function, no matter if it's provided by board code or chipset code.

HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK toplevel bool

This should be enabled on certain plaforms, such as the AMD SR565x, that cannot handle concurrent CBFS accesses from multiple APs during early startup.

HAVE_MONOTONIC_TIMER toplevel bool

The board/chipset provides a monotonic timer.

GENERIC_UDELAY toplevel bool

The board/chipset uses a generic udelay function utilizing the monotonic timer.

TIMER_QUEUE toplevel bool

Provide a timer queue for performing time-based callbacks.

COOP_MULTITASKING toplevel bool

Cooperative multitasking allows callbacks to be multiplexed on the main thread of ramstage. With this enabled it allows for multiple execution paths to take place when they have udelay() calls within their code.

NUM_THREADS toplevel int

How many execution threads to cooperatively multitask with.

HAVE_OPTION_TABLE toplevel bool

This variable specifies whether a given board has a cmos.layout file containing NVRAM/CMOS bit definitions. It defaults to 'n' but can be selected in mainboard/*/Kconfig.

GFXUMA toplevel bool

Enable Unified Memory Architecture for graphics.

HAVE_ACPI_TABLES toplevel bool

This variable specifies whether a given board has ACPI table support. It is usually set in mainboard/*/Kconfig.

HAVE_MP_TABLE toplevel bool

This variable specifies whether a given board has MP table support. It is usually set in mainboard/*/Kconfig. Whether or not the MP table is actually generated by coreboot is configurable by the user via GENERATE_MP_TABLE.

HAVE_PIRQ_TABLE toplevel bool

This variable specifies whether a given board has PIRQ table support. It is usually set in mainboard/*/Kconfig. Whether or not the PIRQ table is actually generated by coreboot is configurable by the user via GENERATE_PIRQ_TABLE.

MAX_PIRQ_LINKS toplevel int

This variable specifies the number of PIRQ interrupt links which are routable. On most chipsets, this is 4, INTA through INTD. Some chipsets offer more than four links, commonly up to INTH. They may also have a separate link for ATA or IOAPIC interrupts. When the PIRQ table specifies links greater than 4, pirq_route_irqs will not function properly, unless this variable is correctly set.

ACPI_NHLT toplevel bool

Build support for NHLT (non HD Audio) ACPI table generation.

Menu: System tables
GENERATE_MP_TABLE toplevel bool Generate an MP table

Generate an MP table (conforming to the Intel MultiProcessor specification 1.4) for this board.

If unsure, say Y.

GENERATE_PIRQ_TABLE toplevel bool Generate a PIRQ table

Generate a PIRQ table for this board.

If unsure, say Y.

GENERATE_SMBIOS_TABLES toplevel bool Generate SMBIOS tables

Generate SMBIOS tables for this board.

If unsure, say Y.

MAINBOARD_SERIAL_NUMBER toplevel string SMBIOS Serial Number

The Serial Number to store in SMBIOS structures.

MAINBOARD_VERSION toplevel string SMBIOS Version Number

The Version Number to store in SMBIOS structures.

MAINBOARD_SMBIOS_MANUFACTURER toplevel string SMBIOS Manufacturer

Override the default Manufacturer stored in SMBIOS structures.

MAINBOARD_SMBIOS_PRODUCT_NAME toplevel string SMBIOS Product name

Override the default Product name stored in SMBIOS structures.

SMBIOS_ENCLOSURE_TYPE toplevel hex

System Enclosure or Chassis Types as defined in SMBIOS specification. The default value is SMBIOS_ENCLOSURE_DESKTOP (0x03) or SMBIOS_ENCLOSURE_LAPTOP (0x09) if SYSTEM_TYPE_LAPTOP is set.

Menu: Payload
PAYLOAD_NONE payloads bool None

Select this option if you want to create an "empty" coreboot ROM image for a certain mainboard, i.e. a coreboot ROM image which does not yet contain a payload.

For such an image to be useful, you have to use 'cbfstool' to add a payload to the ROM image later.

PAYLOAD_ELF payloads bool An ELF executable payload

Select this option if you have a payload image (an ELF file) which coreboot should run as soon as the basic hardware initialization is completed.

You will be able to specify the location and file name of the payload image later.

PAYLOAD_BAYOU payloads bool Bayou

Select this option if you want to set bayou as your primary payload.

PAYLOAD_UBOOT payloads/external/U-Boot.name bool U-Boot (Experimental)

Select this option if you want to build a coreboot image with a U-Boot payload.

See https://coreboot.org/Payloads and U-Boot's documentation at http://git.denx.de/?p=u-boot.git;a=blob;f=doc/README.x86 for more information.

PAYLOAD_SEABIOS payloads/external/SeaBIOS.name bool SeaBIOS

Select this option if you want to build a coreboot image with a SeaBIOS payload. If you don't know what this is about, just leave it enabled.

See https://coreboot.org/Payloads for more information.

PAYLOAD_FILO payloads/external/FILO.name bool FILO

Select this option if you want to build a coreboot image with a FILO payload. If you don't know what this is about, just leave it enabled.

See https://coreboot.org/Payloads for more information.

PAYLOAD_LINUX payloads/external/linux.name bool A Linux payload

Select this option if you have a Linux bzImage which coreboot should run as soon as the basic hardware initialization is completed.

You will be able to specify the location and file name of the payload image later.

PAYLOAD_TIANOCORE payloads/external/tianocore.name bool Tianocore coreboot payload package

Select this option if you want to build a coreboot image with a Tianocore payload. If you don't know what this is about, just leave it enabled.

See https://coreboot.org/Payloads for more information.

PAYLOAD_GRUB2 payloads/external/GRUB2.name bool GRUB2

Select this option if you want to build a coreboot image with a GRUB2 payload. If you don't know what this is about, just leave it enabled.

See https://coreboot.org/Payloads for more information.

PAYLOAD_DEPTHCHARGE payloads/external/depthcharge.name bool Depthcharge

Select this option if you want to build a coreboot image with a depthcharge payload.

See https://coreboot.org/Payloads for more information.

UBOOT_STABLE payloads/external/U-Boot bool v2016.1

Stable U-Boot version

UBOOT_MASTER payloads/external/U-Boot bool master

Newest U-Boot version

PAYLOAD_CONFIGFILE payloads/external/U-Boot string U-Boot config file

This option allows a platform to set Kconfig options for a basic U-Boot payload. In general, if the option is used, the default would be "$(top)/src/mainboard/$(MAINBOARDDIR)/config_uboot" for a config stored in the coreboot mainboard directory, or "$(project_dir)/configs/coreboot-x86_defconfig" to use a config from the U-Boot config directory

SEABIOS_STABLE payloads/external/SeaBIOS bool 1.11.1

Stable SeaBIOS version

SEABIOS_MASTER payloads/external/SeaBIOS bool master

Newest SeaBIOS version

SEABIOS_REVISION payloads/external/SeaBIOS bool git revision

Select this option if you have a specific commit or branch that you want to use as the revision from which to build SeaBIOS.

You will be able to specify the name of a branch or a commit id later.

SEABIOS_REVISION_ID payloads/external/SeaBIOS string Insert a commit's SHA-1 or a branch name

The commit's SHA-1 or branch name of the revision to use.

SEABIOS_PS2_TIMEOUT payloads/external/SeaBIOS int PS/2 keyboard controller initialization timeout (milliseconds)

Some PS/2 keyboard controllers don't respond to commands immediately after powering on. This specifies how long SeaBIOS will wait for the keyboard controller to become ready before giving up.

SEABIOS_THREAD_OPTIONROMS payloads/external/SeaBIOS bool Hardware init during option ROM execution

Allow hardware init to run in parallel with optionrom execution.

This can reduce boot time, but can cause some timing variations during option ROM code execution. It is not known if all option ROMs will behave properly with this option.

SEABIOS_VGA_COREBOOT payloads/external/SeaBIOS bool Include generated option rom that implements legacy VGA BIOS compatibility

coreboot can initialize the GPU of some mainboards.

After initializing the GPU, the information about it can be passed to the payload. Provide an option rom that implements this legacy VGA BIOS compatibility requirement.

PAYLOAD_CONFIGFILE payloads/external/SeaBIOS string SeaBIOS config file

This option allows a platform to set Kconfig options for a basic SeaBIOS payload. In general, if the option is used, the default would be "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios"

SEABIOS_BOOTORDER_FILE payloads/external/SeaBIOS string SeaBIOS bootorder file

Add a SeaBIOS bootorder file. From the wiki: "The bootorder file may be used to configure the boot up order. The file should be ASCII text and contain one line per boot method. The description of each boot method follows an Open Firmware device path format. SeaBIOS will attempt to boot from each item in the file - first line of the file first."

See: https://www.coreboot.org/SeaBIOS#Configuring_boot_order

If used, a typical value would be: $(top)/src/mainboard/$(MAINBOARDDIR)/bootorder

SEABIOS_DEBUG_LEVEL payloads/external/SeaBIOS int SeaBIOS debug level (verbosity)

The higher the number, the more verbose SeaBIOS will be. See the table below for the current values corresponding to various items as of SeaBIOS version 1.10.1. Set this value to -1 to use SeaBIOS' default.

Output at various SeaBIOS log levels: level 0 - Logging disabled level 1 - Basic output, interrupts 5, 18h, 19h, 40h, SMP, PNP, PMM level 2 - AHCI, Floppy, Basic ps2, interrupts 11h, 12h, 14h, 17h level 3 - bootsplash, initializations, SeaBIOS VGA BIOS interrupts level 4 - bios tables, more optionrom level 5 - Extra bootsplash, more XHCI level 6 - ATA commands, extra optionrom level 7 - extra ps2 commands, more OHCI & EHCI level 8 - extra malloc info, more AHCI level 9 - interrupts 15h, 16h, 1ah, APM, PCI, SMIs, PCIBIOS, USB-HID commands, SDcard commands, Floppy commands level 10 - interrupt 13h (Drives other than floppy) level 20 - interrupt 10h (Display)

(comment) Using default SeaBIOS log level
(comment) SeaBIOS logging disabled
Menu: PXE Options
PXE_ROM payloads/external/iPXE bool Add an existing PXE ROM image

Select this option if you have a PXE ROM image that you would like to add to your ROM.

BUILD_IPXE payloads/external/iPXE bool Build and add an iPXE ROM

Select this option to fetch and build a ROM from the iPXE project.

IPXE_STABLE payloads/external/iPXE bool 2017.3

iPXE uses a rolling release with no stable version, for reproducibility, use the last commit of a given month as the 'stable' version. This is iPXE from the end of March, 2017.

IPXE_MASTER payloads/external/iPXE bool master

Newest iPXE version.

PXE_ROM_FILE payloads/external/iPXE string PXE ROM filename

The path and filename of the file to use as PXE ROM.

PXE_ROM_ID payloads/external/iPXE string network card PCI IDs

The comma-separated PCI vendor and device ID that would associate your PXE ROM to your network card.

Example: 10ec,8168

In the above example 10ec is the PCI vendor ID (in hex, but without the "0x" prefix) and 8168 specifies the PCI device ID of the network card (also in hex, without "0x" prefix).

Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.

FILO_STABLE payloads/external/FILO bool 0.6.0

Stable FILO version

FILO_MASTER payloads/external/FILO bool HEAD

Newest FILO version

PAYLOAD_FILE payloads/external/linux string Linux path and filename

The path and filename of the bzImage kernel to use as payload.

LINUX_COMMAND_LINE payloads/external/linux string Linux command line

A command line to add to the Linux kernel.

LINUX_INITRD payloads/external/linux string Linux initrd

An initrd image to add to the Linux kernel.

PAYLOAD_FILE payloads/external/tianocore string Tianocore binary

The result of a corebootPkg build

PAYLOAD_FILE payloads/external/tianocore string Tianocore version

Select which version of Tianocore to build (default is to build stable) stable: a version of Tianocore that builds without any errors master: most recent version from upstream Tianocore repository revision: use specific commit or branch to build Tianocore (specified by user)

TIANOCORE_STABLE payloads/external/tianocore bool stable

Select this option to build the stable tianocore version i.e. a version of Tianocore that builds without any errors

TIANOCORE_MASTER payloads/external/tianocore bool master

Select this option to build the master tianocore version i.e. most recent version from upstream Tianocore repository

TIANOCORE_REVISION payloads/external/tianocore bool git revision

Select this option if you have a specific commit or branch that you want to use as the revision from which to build Tianocore.

You will be able to specify the name of a branch or a commit id later.

TIANOCORE_REVISION_ID payloads/external/tianocore string Insert a commit's SHA-1 or a branch name

The commit's SHA-1 or branch name of the revision to use.

TIANOCORE_REVISION_ID payloads/external/tianocore string Target architecture

The Tianocore coreboot Payload Package binary can be built for either only IA32 or both X64 and IA32 architectures. Select which architecture(s) to build for; default is to build for both X64 and IA32.

TIANOCORE_TARGET_IA32 payloads/external/tianocore bool IA32

By selecting this option, the target architecture will be built for only IA32.

TIANOCORE_TARGET_X64 payloads/external/tianocore bool X64

By selecting this option, the target architecture will be built for X64 and IA32.

TIANOCORE_TARGET_X64 payloads/external/tianocore bool Tianocore build

Select whether to generate a debug or release build for Tianocore; default is to generate a release build.

TIANOCORE_DEBUG payloads/external/tianocore bool Generate Tianocore debug build

Generate a debug build.

TIANOCORE_RELEASE payloads/external/tianocore bool Generate Tianocore release build

Generate a release build.

GRUB2_STABLE payloads/external/GRUB2 bool 2.02

Stable GRUB2 version

GRUB2_MASTER payloads/external/GRUB2 bool HEAD

Newest GRUB2 version

GRUB2_REVISION payloads/external/GRUB2 bool git revision

Select this option if you have a specific commit or branch that you want to use as the revision from which to build GRUB2.

You will be able to specify the name of a branch or a commit id later.

GRUB2_REVISION_ID payloads/external/GRUB2 string Insert a commit's SHA-1 or a branch name

The commit's SHA-1 or branch name of the revision to use.

GRUB2_EXTRA_MODULES payloads/external/GRUB2 string Extra modules to include in GRUB image

Space-separated list of additional modules to include. Few common ones:

  • bsd for *BSD
  • png/jpg for PNG/JPG images
  • gfxmenu for graphical menus (you'll need a theme as well)
  • gfxterm_background for setting background
GRUB2_INCLUDE_RUNTIME_CONFIG_FILE payloads/external/GRUB2 bool Include GRUB2 runtime config file into ROM image

The GRUB2 payload reads its runtime configuration file from etc/grub.cfg stored in the CBFS on the flash ROM chip. Without that, it’ll just drop into a rescue shell.

This configuration may need to be coreboot specific.

Select this option, if you want to include the GRUB2 runtime configuration file into CBFS as `etc/grub.cfg` automatically.

You will be able to specify the path of the configuration file later.

Without this option you would need to add this file manually with build/cbfstool build/coreboot.rom add -f grub.cfg -n etc/grub.cfg -t raw

GRUB2_RUNTIME_CONFIG_FILE payloads/external/GRUB2 string Path of grub.cfg

The path of the GRUB2 runtime configuration file to be added to CBFS.

DEPTHCHARGE_STABLE payloads/external/depthcharge bool stable

Latest stable version.

DEPTHCHARGE_MASTER payloads/external/depthcharge bool master

Newest Depthcharge version.

DEPTHCHARGE_REVISION payloads/external/depthcharge bool git revision

Select this option if you have a specific commit or branch that you want to use as the revision from which to build Depthcharge.

You will be able to specify the name of a branch or a commit SHA later.

DEPTHCHARGE_REVISION_ID payloads/external/depthcharge string Insert a commit's SHA-1 or a branch name

The commit's SHA-1 or branch name of the revision to use.

LP_DEFCONFIG_OVERRIDE payloads/external/depthcharge bool Use default libpayload config

The Depthcharge makefile looks for a file config.<boardname> in the libpayload/configs directory. Say Y here to use the file defconfig instead. This is can be a convenience for development purposes, or if the defaults in defconfig are sufficient for your system.

PAYLOAD_FILE payloads string Payload path and filename

The path and filename of the ELF executable file to use as payload.

PAYLOAD_FILE payloads string Payload compression algorithm

Choose the compression algorithm for the chosen payloads. You can choose between LZMA and LZ4.

COMPRESSED_PAYLOAD_LZMA payloads bool Use LZMA compression for payloads

In order to reduce the size payloads take up in the ROM chip coreboot can compress them using the LZMA algorithm.

COMPRESSED_PAYLOAD_LZ4 payloads bool Use LZ4 compression for payloads

In order to reduce the size payloads take up in the ROM chip coreboot can compress them using the LZ4 algorithm.

PAYLOAD_OPTIONS payloads string

Additional cbfstool options for the payload

PAYLOAD_IS_FLAT_BINARY payloads string

Add the payload to cbfs as a flat binary type instead of as an elf payload

COMPRESS_SECONDARY_PAYLOAD payloads bool Use LZMA compression for secondary payloads

In order to reduce the size secondary payloads take up in the ROM chip they can be compressed using the LZMA algorithm.

Menu: Secondary Payloads
COREINFO_SECONDARY_PAYLOAD payloads bool Load coreinfo as a secondary payload

coreinfo can be loaded as a secondary payload under SeaBIOS, GRUB, or any other payload that can load additional payloads.

MEMTEST_SECONDARY_PAYLOAD payloads bool Load Memtest86+ as a secondary payload

Memtest86+ can be loaded as a secondary payload under SeaBIOS, GRUB, or any other payload that can load additional payloads.

MEMTEST_STABLE payloads bool Stable

Stable Memtest86+ version.

For reproducible builds, this option must be selected.

MEMTEST_MASTER payloads bool Master

Newest Memtest86+ version.

This option will fetch the newest version of the Memtest86+ code, updating as new changes are committed. This makes the build non-reproducible, as it can fetch different code each time.

NVRAMCUI_SECONDARY_PAYLOAD payloads bool Load nvramcui as a secondary payload

nvramcui can be loaded as a secondary payload under SeaBIOS, GRUB, or any other payload that can load additional payloads.

TINT_SECONDARY_PAYLOAD payloads bool Load tint as a secondary payload

tint can be loaded as a secondary payload under SeaBIOS, GRUB, or any other payload that can load additional payloads.


Menu: Debugging
GDB_STUB toplevel bool GDB debugging support

If enabled, you will be able to set breakpoints for gdb debugging. See src/arch/x86/lib/c_start.S for details.

GDB_WAIT toplevel bool Wait for a GDB connection in the ramstage

If enabled, coreboot will wait for a GDB connection in the ramstage.


FATAL_ASSERTS toplevel bool Halt when hitting a BUG() or assertion error

If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().

DEBUG_CBFS toplevel bool Output verbose CBFS debug messages

This option enables additional CBFS related debug messages.

DEBUG_RAM_SETUP toplevel bool Output verbose RAM init debug messages

This option enables additional RAM init related debug messages. It is recommended to enable this when debugging issues on your board which might be RAM init related.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

DEBUG_CAR toplevel bool Output verbose Cache-as-RAM debug messages

This option enables additional CAR related debug messages.

DEBUG_PIRQ toplevel bool Check PIRQ table consistency

If unsure, say N.

DEBUG_SMBUS toplevel bool Output verbose SMBus debug messages

This option enables additional SMBus (and SPD) debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

DEBUG_SMI toplevel bool Output verbose SMI debug messages

This option enables additional SMI related debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

DEBUG_SMM_RELOCATION toplevel bool Debug SMM relocation code

This option enables additional SMM handler relocation related debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

DEBUG_MALLOC toplevel bool Output verbose malloc debug messages

This option enables additional malloc related debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

DEBUG_ACPI toplevel bool Output verbose ACPI debug messages

This option enables additional ACPI related debug messages.

Note: This option will slightly increase the size of the coreboot image.

If unsure, say N.

REALMODE_DEBUG toplevel bool Enable debug messages for option ROM execution

This option enables additional x86emu related debug messages.

Note: This option will increase the time to emulate a ROM.

If unsure, say N.

X86EMU_DEBUG toplevel bool Output verbose x86emu debug messages

This option enables additional x86emu related debug messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_JMP toplevel bool Trace JMP/RETF

Print information about JMP and RETF opcodes from x86emu.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_TRACE toplevel bool Trace all opcodes

Print _all_ opcodes that are executed by x86emu.

WARNING: This will produce a LOT of output and take a long time.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_PNP toplevel bool Log Plug&Play accesses

Print Plug And Play accesses made by option ROMs.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_DISK toplevel bool Log Disk I/O

Print Disk I/O related messages.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_PMM toplevel bool Log PMM

Print messages related to POST Memory Manager (PMM).

Note: This option will increase the size of the coreboot image.

If unsure, say N.


X86EMU_DEBUG_VBE toplevel bool Debug VESA BIOS Extensions

Print messages related to VESA BIOS Extension (VBE) functions.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_INT10 toplevel bool Redirect INT10 output to console

Let INT10 (i.e. character output) calls print messages to debug output.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_INTERRUPTS toplevel bool Log intXX calls

Print messages related to interrupt handling.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_CHECK_VMEM_ACCESS toplevel bool Log special memory accesses

Print messages related to accesses to certain areas of the virtual memory (e.g. BDA (BIOS Data Area) or interrupt vectors)

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_MEM toplevel bool Log all memory accesses

Print memory accesses made by option ROM. Note: This also includes accesses to fetch instructions.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_IO toplevel bool Log IO accesses

Print I/O accesses made by option ROM.

Note: This option will increase the size of the coreboot image.

If unsure, say N.

X86EMU_DEBUG_TIMINGS toplevel bool Output timing information

Print timing information needed by i915tool.

If unsure, say N.

DEBUG_SPI_FLASH toplevel bool Output verbose SPI flash debug messages

This option enables additional SPI flash related debug messages.

DEBUG_USBDEBUG toplevel bool Output verbose USB 2.0 EHCI debug dongle messages

This option enables additional USB 2.0 debug dongle related messages.

Select this to debug the connection of usbdebug dongle. Note that you need some other working console to receive the messages.

DEBUG_INTEL_ME toplevel bool Verbose logging for Intel Management Engine

Enable verbose logging for Intel Management Engine driver that is present on Intel 6-series chipsets.

TRACE toplevel bool Trace function calls

If enabled, every function will print information to console once the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd) the 0xaaaabbbb is the actual function and 0xccccdddd is EIP of calling function. Please note some printk related functions are omitted from trace to have good looking console dumps.

DEBUG_COVERAGE toplevel bool Debug code coverage

If enabled, the code coverage hooks in coreboot will output some information about the coverage data that is dumped.

DEBUG_BOOT_STATE toplevel bool Debug boot state machine

Control debugging of the boot state machine. When selected displays the state boundaries in ramstage.

DEBUG_ADA_CODE toplevel bool Compile debug code in Ada sources

Add the compiler switch `-gnata` to compile code guarded by `pragma Debug`.

NO_EDID_FILL_FB lib bool

Don't include default fill_lb_framebuffer() implementation. Select this if your drivers uses MAINBOARD_DO_NATIVE_VGA_INIT but provides its own fill_lb_framebuffer() implementation.

RAMSTAGE_ADA lib bool

Selected by features that use Ada code in ramstage.

RAMSTAGE_LIBHWBASE lib bool

Selected by features that require `libhwbase` in ramstage.

FLATTENED_DEVICE_TREE lib bool

Selected by features that require to parse and manipulate a flattened devicetree in ramstage.

POWER_BUTTON_DEFAULT_ENABLE toplevel bool

Select when the board has a power button which can optionally be disabled by the user.

POWER_BUTTON_DEFAULT_DISABLE toplevel bool

Select when the board has a power button which can optionally be enabled by the user, e.g. when the board ships with a jumper over the power switch contacts.

POWER_BUTTON_FORCE_ENABLE toplevel bool

Select when the board requires that the power button is always enabled.

POWER_BUTTON_FORCE_DISABLE toplevel bool

Select when the board requires that the power button is always disabled, e.g. when it has been hardwired to ground.

POWER_BUTTON_IS_OPTIONAL toplevel bool

Internal option that controls ENABLE_POWER_BUTTON visibility.

REG_SCRIPT toplevel bool

Internal option that controls whether we compile in register scripts.

MAX_REBOOT_CNT toplevel int

Internal option that sets the maximum number of bootblock executions allowed with the normal image enabled before assuming the normal image is defective and switching to the fallback image.

CREATE_BOARD_CHECKLIST toplevel bool

When selected, creates a webpage showing the implementation status for the board. Routines highlighted in green are complete, yellow are optional and red are required and must be implemented. A table is produced for each stage of the boot process except the bootblock. The red items may be used as an implementation checklist for the board.

MAKE_CHECKLIST_PUBLIC toplevel bool

When selected, build/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html is copied into the Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board directory.

CHECKLIST_DATA_FILE_LOCATION toplevel string

Location of the <stage>_complete.dat and <stage>_optional.dat files that are consumed during checklist processing. <stage>_complete.dat contains the symbols that are expected to be in the resulting image. <stage>_optional.dat is a subset of <stage>_complete.dat and contains a list of weak symbols which the resulting image may consume. Other symbols contained only in <stage>_complete.dat will be flagged as required and not implemented if a weak implementation is found in the resulting image.

NO_XIP_EARLY_STAGES toplevel bool

Identify if early stages are eXecute-In-Place(XIP).

EARLY_CBMEM_LIST toplevel bool

Enable display of CBMEM during romstage and postcar.

RELOCATABLE_MODULES toplevel bool

If RELOCATABLE_MODULES is selected then support is enabled for building relocatable modules in the RAM stage. Those modules can be loaded anywhere and all the relocations are handled automatically.

NO_STAGE_CACHE toplevel bool

Do not save any component in stage cache for resume path. On resume, all components would be read back from CBFS again.

GENERIC_GPIO_LIB toplevel bool

If enabled, compile the generic GPIO library. A "generic" GPIO implies configurability usually found on SoCs, particularly the ability to control internal pull resistors.

GENERIC_SPD_BIN toplevel bool

If enabled, add support for adding spd.hex files in cbfs as spd.bin and locating it runtime to load SPD. Additionally provide provision to fetch SPD over SMBus.

DIMM_MAX toplevel int

Total number of memory DIMM slots available on motherboard. It is multiplication of number of channel to number of DIMMs per channel

DIMM_SPD_SIZE toplevel int

Total SPD size that will be used for DIMM. Ex: DDR3 256, DDR4 512.

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