Difference between pages "Coreboot Options" and "Supported Motherboards"

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This is an automatically generated list of '''coreboot compile-time options'''.
+
__NOTOC__
 +
This page was automatically generated. Please do not edit, any edits will be overwritten by an
 +
automatic utility.
  
Last update: 4.8-38-g8a25caee05
+
= Mainboards supported by coreboot =
{| border="0" style="font-size: smaller"
 
|- bgcolor="#6699dd"
 
! align="left" | Option
 
! align="left" | Source
 
! align="left" | Format
 
! align="left" | Short Description
 
! align="left" | Description
 
|- bgcolor="#6699dd"
 
! align="left" | Menu: General setup || || || ||
 
|- bgcolor="#eeeeee"
 
| LOCALVERSION || toplevel || string || Local version string ||
 
Append an extra string to the end of the coreboot version.
 
  
This can be useful if, for instance, you want to append the
+
This page shows two representations of the same data:
respective board's hostname or some other identifying string to
 
the coreboot version number, so that you can easily distinguish
 
boot logs of different boards from each other.
 
  
||
+
First a list of all mainboards supported by coreboot (current within
|- bgcolor="#eeeeee"
+
one hour) ordered by category. For each mainboard the table shows the
| CBFS_PREFIX || toplevel || string || CBFS prefix to use ||
+
latest user-contributed report of a successful boot on the device.
Select the prefix to all files put into the image. It's "fallback"
 
by default, "normal" is a common alternative.
 
  
||
+
After that, the page provides a time-ordered list of these contributed
|- bgcolor="#eeeeee"
+
reports, with the newest report first.
| CBFS_PREFIX || toplevel || string || Compiler to use ||
 
This option allows you to select the compiler used for building
 
coreboot.
 
You must build the coreboot crosscompiler for the board that you
 
have selected.
 
  
To build all the GCC crosscompilers (takes a LONG time), run:
+
Boards without such reports may boot or there may be some maintenance
make crossgcc
+
required. The reports contain the coreboot configuration and precise commit
 +
id, so it is possible to reproduce the build.
  
For help on individual architectures, run the command:
+
We encourage developers and users to contribute reports so we know which
make help_toolchain
+
devices are well-tested.  We have
 +
[https://review.coreboot.org/gitweb/cgit/coreboot.git/tree/util/board_status a tool in the coreboot repository]
 +
to make contributing easy.  The data resides in the
 +
[https://review.coreboot.org/gitweb/cgit/board-status.git/ board status repository].
 +
Contributing requires an account on review.coreboot.org
  
||
+
Sometimes the same board is sold under different names, we've tried to
|- bgcolor="#eeeeee"
+
list all known names but some names might be missing.
| COMPILER_GCC || toplevel || bool || GCC ||
 
Use the GNU Compiler Collection (GCC) to build coreboot.
 
  
For details see http://gcc.gnu.org.
+
If the board is not found in the coreboot's source code, there might
 +
be some form of support that is not ready yet for inclusion in coreboot,
 +
usually people willing to send their patches to coreboot goes through
 +
[https://review.coreboot.org gerrit], so looking there could find some
 +
code for boards that are not yet merged.
  
||
+
= Vendor trees =
|- bgcolor="#eeeeee"
+
Some vendors have their own coreboot trees/fork, like for instance:
| COMPILER_LLVM_CLANG || toplevel || bool || LLVM/clang (TESTING ONLY - Not currently working) ||
+
* [http://git.chromium.org/gitweb/?p=chromiumos/third_party/coreboot.git;a=summary chrome/chromium's tree]
Use LLVM/clang to build coreboot. To use this, you must build the
+
== Motherboards supported in coreboot ==
coreboot version of the clang compiler. Run the command
 
make clang
 
Note that this option is not currently working correctly and should
 
really only be selected if you're trying to work on getting clang
 
operational.
 
  
For details see http://clang.llvm.org.
+
{| border="0" style="font-size: smaller"
 
+
|- bgcolor="#6699ff"
||
+
! align="left" | Vendor
|- bgcolor="#eeeeee"
+
! align="left" | Mainboard
| ANY_TOOLCHAIN || toplevel || bool || Allow building with any toolchain ||  
+
! align="left" | Latest known good
Many toolchains break when building coreboot since it uses quite
+
! align="left" | Northbridge
unusual linker features. Unless developers explicitely request it,
+
! align="left" | Southbridge
we'll have to assume that they use their distro compiler by mistake.
+
! align="left" | Super I/O
Make sure that using patched compilers is a conscious decision.
+
! align="left" | CPU
 
+
! align="left" | Socket
||
+
! align="left" | <span title="ROM chip package">ROM&nbsp;<sup>1</sup></span>
|- bgcolor="#eeeeee"
+
! align="left" | <span title="ROM chip protocol">P&nbsp;<sup>2</sup></span>
| CCACHE || toplevel || bool || Use ccache to speed up (re)compilation ||  
+
! align="left" | <span title="ROM chip socketed?">S&nbsp;<sup>3</sup></span>
Enables the use of ccache for faster builds.
+
! align="left" | <span title="Board supported by flashrom?">F&nbsp;<sup>4</sup></span>
 
+
! align="left" | <span title="Vendor Cooperation Score">VCS<sup>5</sup></span>
Requires the ccache utility in your system $PATH.
+
|- bgcolor="#6699ff"
 
+
| colspan="13" | <h4>Laptops</h4>
For details see https://ccache.samba.org.
 
 
 
||
 
|- bgcolor="#eeeeee"
 
| FMD_GENPARSER || toplevel || bool || Generate flashmap descriptor parser using flex and bison ||
 
Enable this option if you are working on the flashmap descriptor
 
parser and made changes to fmd_scanner.l or fmd_parser.y.
 
 
 
Otherwise, say N to use the provided pregenerated scanner/parser.
 
 
 
||
 
|- bgcolor="#eeeeee"
 
| UTIL_GENPARSER || toplevel || bool || Generate SCONFIG &amp; BINCFG parser using flex and bison ||
 
Enable this option if you are working on the sconfig device tree
 
parser or bincfg and made changes to the .l or .y files.
 
 
 
Otherwise, say N to use the provided pregenerated scanner/parser.
 
 
 
||
 
|- bgcolor="#eeeeee"
 
| USE_OPTION_TABLE || toplevel || bool || Use CMOS for configuration values ||
 
Enable this option if coreboot shall read options from the "CMOS"
 
NVRAM instead of using hard-coded values.
 
 
 
||
 
|- bgcolor="#eeeeee"
 
| STATIC_OPTION_TABLE || toplevel || bool || Load default configuration values into CMOS on each boot ||
 
Enable this option to reset "CMOS" NVRAM values to default on
 
every boot.  Use this if you want the NVRAM configuration to
 
never be modified from its default values.
 
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Apple
| COMPRESS_RAMSTAGE || toplevel || bool || Compress ramstage with LZMA ||  
+
| [[Board:apple/macbook21|Macbook2,1]]
Compress ramstage to save memory in the flash image. Note
+
| style="background:#FFff00" | [[#apple/macbook21|2014-08-17T22:05:53Z]]
that decompression might slow down booting if the boot flash
+
| Intel® I945
is connected through a slow link (i.e. SPI).
+
Intel® SUBTYPE I945GM
 +
| Intel® I82801GX
 +
|  
 +
| Intel® Core™ 2 Duo Mobile, Core™ Duo/Solo, Celeron® M
 +
| Socket mPGA478
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Apple
| COMPRESS_PRERAM_STAGES || toplevel || bool || Compress romstage and verstage with LZ4 ||  
+
| [[Board:apple/macbookair4_2|MacBookAir4,2]]
Compress romstage and (if it exists) verstage with LZ4 to save flash
+
| style="background:red" | Unknown
space and speed up boot, since the time for reading the image from SPI
+
| Intel® SANDYBRIDGE
(and in the vboot case verifying it) is usually much greater than the
+
| Intel® BD82X6X
time spent decompressing. Doesn't work for XIP stages (assume all
+
|  
ARCH_X86 for now) for obvious reasons.
+
| Intel® 2nd Gen (Sandybridge) Core i3/i5/i7
 +
| Socket RPGA989
 +
| WSON-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| INCLUDE_CONFIG_FILE || toplevel || bool || Include the coreboot .config file into the ROM image ||  
+
| [http://en.getac.com/AP/MISC/M0100/F0110_DownLoad_File.aspx?bullid=AllBull&fileid=105261&DomainLang=100020&DomainRegion=100027 Getac]
Include the .config file that was used to compile coreboot
+
| [[Board:getac/p470|P470]]
in the (CBFS) ROM image. This is useful if you want to know which
+
| style="background:#DDff00" | [[#getac/p470|2017-10-09T20:20:40Z]]
options were used to build a specific coreboot.rom image.
+
| Intel® I945
 +
Intel® SUBTYPE I945GM
 +
| Intel® I82801GX
 +
TI PCIXX12
 +
| SMSC® FDC37N972
 +
SMSC® SIO10N268
 +
| Intel® Core™ 2 Duo Mobile, Core™ Duo/Solo, Celeron® M
 +
| Socket mPGA478
 +
| ?
 +
| SPI
 +
| ?
 +
| style="background:lime" | Y
 +
| —
  
Saying Y here will increase the image size by 2-3KB.
+
|- bgcolor="#dddddd"
 +
| Google
 +
( Google )
 +
| [[Board:google/auron|Auron Broadwell Reference Board]]
 +
| style="background:red" | Unknown
 +
|
 +
|
 +
|
 +
|
 +
|
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
You can use the following command to easily list the options:
+
|- bgcolor="#dddddd"
 
+
| [http://h10025.www1.hp.com/ewfrf/wc/product?product=5389124&cc=us&dlc=en&lc=en&jumpid=reg_r1002_usen_c-001_title_r0005 Google]
grep -a CONFIG_ coreboot.rom
+
( HP )
 
+
| [[Board:google/butterfly|Pavilion Chromebook 14]]
Alternatively, you can also use cbfstool to print the image
+
| style="background:#FFff00" | [[#google/butterfly|2014-03-28T20:20:38Z]]
contents (including the raw 'config' item we're looking for).
+
| Intel® IVYBRIDGE
 
+
| Intel® C216
Example:
+
|  
 
+
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
$ cbfstool coreboot.rom print
+
| Socket RPGA989
coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
+
| SOIC-8
offset 0x0
+
| SPI
Alignment: 64 bytes
+
| style="background:red" | N
 
+
| style="background:lime" | Y
Name                          Offset    Type        Size
+
|
cmos_layout.bin                0x0        cmos layout  1159
 
fallback/romstage              0x4c0      stage        339756
 
fallback/ramstage              0x53440    stage        186664
 
fallback/payload              0x80dc0    payload      51526
 
config                        0x8d740    raw          3324
 
(empty)                        0x8e480    null        3610440
 
 
 
||
 
|- bgcolor="#eeeeee"
 
| COLLECT_TIMESTAMPS || toplevel || bool || Create a table of timestamps collected during boot ||
 
Make coreboot create a table of timer-ID/timer-value pairs to
 
allow measuring time spent at different phases of the boot process.
 
 
 
||
 
|- bgcolor="#eeeeee"
 
| TIMESTAMPS_ON_CONSOLE || toplevel || bool || Print the timestamp values on the console ||
 
Print the timestamps to the debug console if enabled at level spew.
 
 
 
||
 
|- bgcolor="#eeeeee"
 
| USE_BLOBS || toplevel || bool || Allow use of binary-only repository ||
 
This draws in the blobs repository, which contains binary files that
 
might be required for some chipsets or boards.
 
This flag ensures that a "Free" option remains available for users.
 
 
 
||
 
|- bgcolor="#eeeeee"
 
| COVERAGE || toplevel || bool || Code coverage support ||
 
Add code coverage support for coreboot. This will store code
 
coverage information in CBMEM for extraction from user space.
 
If unsure, say N.
 
 
 
||
 
|- bgcolor="#eeeeee"
 
| UBSAN || toplevel || bool || Undefined behavior sanitizer support ||
 
Instrument the code with checks for undefined behavior. If unsure,
 
say N because it adds a small performance penalty and may abort
 
on code that happens to work in spite of the UB.
 
 
 
||
 
|- bgcolor="#eeeeee"
 
| RELOCATABLE_RAMSTAGE || toplevel || bool || Build the ramstage to be relocatable in 32-bit address space. ||
 
The reloctable ramstage support allows for the ramstage to be built
 
as a relocatable module. The stage loader can identify a place
 
out of the OS way so that copying memory is unnecessary during an S3
 
wake. When selecting this option the romstage is responsible for
 
determing a stack location to use for loading the ramstage.
 
 
 
||
 
|- bgcolor="#eeeeee"
 
| CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM || toplevel || bool ||  ||
 
The relocated ramstage is saved in an area specified by the
 
by the board and/or chipset.
 
 
 
||
 
|- bgcolor="#eeeeee"
 
| UPDATE_IMAGE || toplevel || bool || Update existing coreboot.rom image ||
 
If this option is enabled, no new coreboot.rom file
 
is created. Instead it is expected that there already
 
is a suitable file for further processing.
 
The bootblock will not be modified.
 
 
 
If unsure, select 'N'
 
 
 
||
 
|- bgcolor="#eeeeee"
 
| BOOTSPLASH_IMAGE || toplevel || bool || Add a bootsplash image ||
 
Select this option if you have a bootsplash image that you would
 
like to add to your ROM.
 
 
 
This will only add the image to the ROM. To actually run it check
 
options under 'Display' section.
 
 
 
||
 
|- bgcolor="#eeeeee"
 
| BOOTSPLASH_FILE || toplevel || string || Bootsplash path and filename ||
 
The path and filename of the file to use as graphical bootsplash
 
screen. The file format has to be jpg.
 
 
 
||
 
 
 
|- bgcolor="#6699dd"
 
! align="left" | Menu: Mainboard || || || ||
 
|- bgcolor="#eeeeee"
 
| || || (comment) || || Important: Run 'make distclean' before switching boards ||
 
|- bgcolor="#eeeeee"
 
| VENDOR_WINNET || mainboard/winnet.name || bool || WinNET ||
 
WinNET boards. Used in various thin client appliances.
 
  
||
+
|- bgcolor="#dddddd"
||
+
| Google
|- bgcolor="#eeeeee"
+
( Google )
| UART_FOR_CONSOLE || mainboard/intel/mohonpeak || int || ||  
+
| [[Board:google/chell|Chell Skylake Reference Board]]
The Mohon Peak board uses COM2 (2f8) for the serial console.
+
| style="background:red" | Unknown
 +
|
 +
|
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Google
| PAYLOAD_CONFIGFILE || mainboard/intel/mohonpeak || string || ||  
+
( Google )
The Avoton/Rangeley chip does not allow devices to write into the 0xe000
+
| [[Board:google/cyan|Cyan Braswell baseboard]]
segment.  This means that USB/SATA devices will not work in SeaBIOS unless
+
| style="background:red" | Unknown
we put the SeaBIOS buffer area down in the 0x9000 segment.
+
|  
 +
|  
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Google
| ENABLE_FSP_MEMORY_DOWN || mainboard/intel/harcuvar || bool || Enable Memory Down ||  
+
( Samsung )
Select this option to enable Memory Down function.
+
| [[Board:google/daisy|ARM Chromebook]]
 +
| style="background:red" | Unknown
 +
|
 +
|  
 +
|  
 +
| Samsung Exynos 5250
 +
| ?
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Google
| SPD_LOC || mainboard/intel/harcuvar || hex || SPD binary location in cbfs ||  
+
( Google )
Location of SPD binary for memory down function.
+
| [[Board:google/eve|Eve]]
 +
| style="background:red" | Unknown
 +
|  
 +
|  
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Google
| VBOOT || mainboard/intel/kblrvp || None || TPM to USE ||  
+
( Google )
This option allows you to select the TPM to use.
+
| [[Board:google/glados|Glados Skylake Reference Board]]
Select whether the board does not have TPM, TPM 1.1 or TPM 2.0
+
| style="background:red" | Unknown
 +
|  
 +
|  
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Google
| UART_FOR_CONSOLE || mainboard/intel/littleplains || int || ||  
+
( Google )
The Little Plains board uses COM2 (2f8) for the serial console.
+
| [[Board:google/lars|Lars Skylake chromebook]]
 +
| style="background:red" | Unknown
 +
|  
 +
|  
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.google.com/intl/en/chrome/devices/chromebooks.html#pixel Google]
| PAYLOAD_CONFIGFILE || mainboard/intel/littleplains || string || ||  
+
| [[Board:google/link|Chromebook Pixel]]
The Avoton/Rangeley chip does not allow devices to write into the 0xe000
+
| style="background:red" | Unknown
segment.  This means that USB/SATA devices will not work in SeaBIOS unless
+
| Intel® IVYBRIDGE
we put the SeaBIOS buffer area down in the 0x9000 segment.
+
| Intel® C216
 +
|  
 +
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
 +
| Socket RPGA989
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Google
| GALILEO_GEN2 || mainboard/intel/galileo || bool || Board generation: GEN1 (n) or GEN2 (y) ||  
+
| [[Board:google/nyan|Nyan]]
The coreboot binary will configure only one generation of the Galileo
+
| style="background:red" | Unknown
board since coreboot can not determine the board generation at
+
|  
runtime.  Select which generation of the Galileo that coreboot
+
|  
should initialize.
+
|
 +
|
 +
|  
 +
| ?
 +
| SPI
 +
| ?
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Google
| FSP_VERSION_1_1 || mainboard/intel/galileo || bool || FSP 1.1 ||  
+
| [[Board:google/nyan_big|Nyan Big]]
Use FSP 1_1 binary
+
| style="background:red" | Unknown
||
+
|  
|- bgcolor="#eeeeee"
+
|  
| FSP_VERSION_2_0 || mainboard/intel/galileo || bool || FSP 2.0 ||
+
|  
Use FSP 2.0 binary
+
|  
 +
|  
 +
| ?
 +
| SPI
 +
| ?
 +
| style="background:lime" | Y
 +
|
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Google
| FSP_BUILD_TYPE_DEBUG || mainboard/intel/galileo || bool || Debug ||  
+
( Google )
Use the debug version of FSP
+
| [[Board:google/nyan_blaze|Nyan Blaze Nvidia Tegra T124 Chromebook]]
||
+
| style="background:red" | Unknown
|- bgcolor="#eeeeee"
+
|  
| FSP_BUILD_TYPE_RELEASE || mainboard/intel/galileo || bool || Release ||
+
|  
Use the release version of FSP
+
|  
 +
|  
 +
|
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
|
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Google
| FSP_TYPE_1_1 || mainboard/intel/galileo || bool || MemInit subroutine ||
+
( Google )
FSP 1.1 implemented as subroutines, no EDK-II cores
+
| [[Board:google/oak|Oak MediaTek MT8173 reference board]]
||
+
| style="background:red" | Unknown
|- bgcolor="#eeeeee"
+
|  
| FSP_TYPE_1_1_PEI || mainboard/intel/galileo || bool || SEC + PEI Core + MemInit PEIM ||  
+
|  
FSP 1.1 implemented using SEC and PEI core
+
|  
||
+
|  
|- bgcolor="#eeeeee"
+
|  
| FSP_TYPE_2_0 || mainboard/intel/galileo || bool || MemInit subroutine ||
+
| ?
FSP 2.0 implemented as subroutines, no EDK-II cores
+
| SPI
||
+
| style="background:red" | N
|- bgcolor="#eeeeee"
+
| style="background:lime" | Y
| FSP_TYPE_2_0_PEI || mainboard/intel/galileo || bool || SEC + PEI Core + MemInit PEIM ||
+
|
FSP 2.0 implemented using SEC and PEI core
 
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Google
| FSP_DEBUG_ALL || mainboard/intel/galileo || bool || Enable all FSP debug support ||  
+
( Google )
Turn on debug support to display HOBS, MTRRS, SMM_MEMORY_MAP, UPD_DATA
+
| [[Board:google/octopus|Octopus GLK Reference Board]]
also turn on FSP 2.0 debug support for ESRAM_LAYOUT,
+
| style="background:red" | Unknown
FSP_CALLS_AND_STATUS, FSP_HEADER, POSTCAR_CONSOLE and VERIFY_HOBS
+
|  
or FSP 1.1 DISPLAY_FSP_ENTRY_POINTS
+
|  
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Google
| VBOOT_WITH_CRYPTO_SHIELD || mainboard/intel/galileo || bool || Verified boot using the Crypto Shield board ||  
+
( Acer )
Perform a verified boot using the TPM on the Crypto Shield board.
+
| [[Board:google/parrot|C7 Chromebook]]
 +
| style="background:#FFff00" | [[#google/parrot|2014-09-13T00:21:02Z]]
 +
| Intel® IVYBRIDGE
 +
| Intel® C216
 +
|
 +
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
 +
| Socket RPGA989
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Google
| DRIVER_TPM_I2C_ADDR || mainboard/intel/galileo || hex || Address of the I2C TPM chip ||  
+
| [[Board:google/peach_pit|Peach Pit]]
I2C address of the TPM chip on the Crypto Shield board.
+
| style="background:red" | Unknown
 +
|  
 +
|  
 +
|  
 +
| Samsung Exynos 5420
 +
| ?
 +
| ?
 +
| SPI
 +
| ?
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Google
| FMDFILE || mainboard/intel/galileo || string || FMAP description file in fmd format ||  
+
( Google )
The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
+
| [[Board:google/poppy|Poppy Kabylake Reference Board]]
but in some cases more complex setups are required.
+
| style="background:red" | Unknown
 +
|  
 +
|  
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
When an FMD descriptionn file is specified, the build system uses it
+
|- bgcolor="#dddddd"
instead of creating a default FMAP file.
+
| Google
 +
( Google )
 +
| [[Board:google/rambi|Rambi Baytrail Reference Board]]
 +
| style="background:red" | Unknown
 +
|
 +
|
 +
|
 +
|
 +
|
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Google
| BASEBOARD_GLKRVP_LAPTOP || mainboard/intel/glkrvp || None || ON BOARD EC ||  
+
( Google )
This option allows you to select the on board EC to use.
+
| [[Board:google/reef|Reef Apollolake Reference Board]]
Select whether the board  has Intel EC or Chrome EC
+
| style="background:red" | Unknown
 +
|  
 +
|  
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#6699dd"
+
| Google
! align="left" | Menu: Debugging || || || ||
+
| [[Board:google/rotor|rotor]]
|- bgcolor="#eeeeee"
+
| style="background:red" | Unknown
| DISABLE_UART_ON_TESTPADS || mainboard/intel/dcp847ske || bool || Disable UART on testpads ||
+
|  
Serial output requires soldering to the testpad next to
+
|  
NCT5577D pin 18 (txd) and gnd.
+
|  
 +
|  
 +
|  
 +
| ?
 +
| parallel flash
 +
| ?
 +
| style="background:lime" | Y
 +
|
  
||
+
|- bgcolor="#dddddd"
 +
| Google
 +
( Google )
 +
| [[Board:google/slippy|Slippy Haswell Chromebook Reference device]]
 +
| style="background:#FFff00" | [[#google/slippy|2017-04-04T20:03:46Z]]
 +
| Intel® HASWELL
 +
| Intel® LYNXPOINT
 +
|
 +
| Intel® 4th Gen (Haswell) Core i3/i5/i7
 +
| ?
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
|- bgcolor="#eeeeee"
+
|- bgcolor="#dddddd"
| VGA_BIOS_FILE || mainboard/intel/strago || string || ||  
+
| Google
The C0 version of the video bios gets computed from this name
+
( Lenovo )
so that they can both be added.  Only the correct one for the
+
| [[Board:google/stout|Thinkpad X131e Chromebook]]
system will be run.
+
| style="background:red" | Unknown
 +
| Intel® IVYBRIDGE
 +
| Intel® C216
 +
|
 +
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
 +
| Socket RPGA989
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Google
| VGA_BIOS_ID || mainboard/intel/strago || string || ||  
+
( Google )
The VGA_BIOS_ID for the C0 version of the video bios is hardcoded
+
| [[Board:google/zoombini|Zoombini Cannonlake Reference Board]]
in soc/intel/braswell/Makefile.inc as 8086,22b1
+
| style="background:red" | Unknown
 +
|  
 +
|  
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOARD_EMULATION_SPIKE_UCB_RISCV || mainboard/emulation/spike-riscv.name || bool || SPIKE ucb riscv ||  
+
| [https://support.hp.com/us-en/product/HP-EliteBook-2570p-Notebook-PC/5259393 HP]
To run coreboot in spike:
+
| [[Board:hp/2570p|EliteBook 2570p]]
* run "make" as usual
+
| style="background:#6Eff00" | [[#hp/2570p|2018-01-29T09:41:35Z]]
* util/riscv/make-spike-elf.sh build/coreboot.{rom,elf}
+
| Intel® IVYBRIDGE
* spike -m1024 build/coreboot.elf
+
| Intel® C216
 +
|  
 +
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
 +
| Socket RPGA989
 +
| SOIC-16
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
||
 
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HUDSON_LEGACY_FREE || mainboard/bap/ode_e21XX || bool || Select DDR3 clock ||  
+
| [https://support.hp.com/us-en/product/hp-elitebook-2760p-tablet-pc/5071191 HP]
Select your preferenced DDR3 clock setting.
+
| [[Board:hp/2760p|EliteBook 2760p]]
 +
| style="background:#E6ff00" | [[#hp/2760p|2017-09-30T20:34:28Z]]
 +
| Intel® SANDYBRIDGE
 +
| Intel® BD82X6X
 +
|
 +
| Intel® 2nd Gen (Sandybridge) Core i3/i5/i7
 +
| Socket RPGA989
 +
| SOIC-8
 +
| SPI
 +
| style="background:lime" | Y
 +
| style="background:red" | N
 +
| —
  
Note: This option changes the total power consumption.
 
 
If unsure, use DDR3-1333.
 
 
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HUDSON_LEGACY_FREE || mainboard/bap/ode_e20XX || bool || Select DDR3 clock ||  
+
| [https://support.hp.com/us-en/product/HP-EliteBook-8460p-Notebook-PC/5056942 HP]
Select your preferred DDR3 clock setting.
+
| [[Board:hp/8460p|EliteBook 8460p]]
 +
| style="background:#B5ff00" | [[#hp/8460p|2017-11-18T12:59:33Z]]
 +
| Intel® SANDYBRIDGE
 +
| Intel® BD82X6X
 +
| SMSC® LPC47N217
 +
| Intel® 2nd Gen (Sandybridge) Core i3/i5/i7
 +
| Socket RPGA989
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
Note: This option changes the total power consumption.
 
 
If unsure, use DDR3-1066.
 
 
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_DP3_DAUGHTER_CARD_IN_J120 || mainboard/amd/lamar || bool || Use J120 as an additional graphics port ||  
+
| [https://support.hp.com/us-en/product/HP-EliteBook-8470p-Notebook-PC/5212907 HP]
The PCI Express slot at J120 can be configured as an additional
+
| [[Board:hp/8470p|EliteBook 8470p]]
DisplayPort connector using an adapter card from AMD or as a normal
+
| style="background:#FFff00" | [[#hp/8470p|2017-08-24T12:08:03Z]]
PCI Express (x4) slot.
+
| Intel® IVYBRIDGE
 
+
| Intel® C216
By default, the connector is configured as a PCI Express (x4) slot.
+
| SMSC® LPC47N217
 
+
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
Select this option to enable the slot for use with one of AMD's
+
| Socket RPGA989
passive graphics port expander cards (only available from AMD).
+
| SOIC-16
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
||
 
|- bgcolor="#eeeeee"
 
| || || (comment) || || Slippy ||
 
|- bgcolor="#eeeeee"
 
| || || (comment) || || Octopus ||
 
|- bgcolor="#eeeeee"
 
| || || (comment) || || Auron ||
 
|- bgcolor="#eeeeee"
 
| || || (comment) || || Gru ||
 
|- bgcolor="#eeeeee"
 
| || || (comment) || || Cyan ||
 
|- bgcolor="#eeeeee"
 
| || || (comment) || || Reef ||
 
|- bgcolor="#eeeeee"
 
| || || (comment) || || Jecht ||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| || || (comment) || || Beltino ||
+
| [https://support.hp.com/us-en/product/HP-EliteBook-8770w-Mobile-Workstation/5257511 HP]
|- bgcolor="#eeeeee"
+
| [[Board:hp/8770w|EliteBook 8770w]]
| || || (comment) || || Rambi ||
+
| style="background:red" | Unknown
|- bgcolor="#eeeeee"
+
| Intel® IVYBRIDGE
| || || (comment) || || Kahlee ||
+
| Intel® C216
|- bgcolor="#eeeeee"
+
| SMSC® LPC47N217
| || || (comment) || || Poppy ||
+
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
|- bgcolor="#eeeeee"
+
| Socket RPGA989
| || || (comment) || || Zoombini ||
+
| SOIC-16
|- bgcolor="#eeeeee"
+
| SPI
| || || (comment) || || Veyron ||
+
| style="background:red" | N
|- bgcolor="#eeeeee"
+
| style="background:red" | N
| || || (comment) || || Oak ||
+
|
|- bgcolor="#eeeeee"
 
| MAINBOARD_PART_NUMBER || mainboard/google/nyan_blaze || string || BCT boot media ||
 
Which boot media to configure the BCT for.
 
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NYAN_BLAZE_BCT_CFG_SPI || mainboard/google/nyan_blaze || bool || SPI ||  
+
| [https://support.hp.com/us-en/product/hp-elitebook-folio-9470m-ultrabook/5271146/product-info HP]
Configure the BCT for booting from SPI.
+
| [[Board:hp/folio_9470m|EliteBook Folio 9470m]]
 +
| style="background:#35ff00" | [[#hp/folio_9470m|2018-03-26T10:25:58Z]]
 +
| Intel® IVYBRIDGE
 +
| Intel® C216
 +
|
 +
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
 +
| Socket RPGA989
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NYAN_BLAZE_BCT_CFG_EMMC || mainboard/google/nyan_blaze || bool || eMMC ||  
+
| HP
Configure the BCT for booting from eMMC.
+
| [[Board:hp/pavilion_m6_1035dx|Pavilion m6 1035dx]]
 +
| style="background:#FFff00" | [[#hp/pavilion_m6_1035dx|2014-12-06T10:30:54Z]]
 +
| AMD Family 15h TN (AGESA)
 +
| AMD AGESA HUDSON
 +
|
 +
| AMD Family 15h TN (AGESA)
 +
| ?
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOOT_DEVICE_SPI_FLASH_BUS || mainboard/google/nyan_blaze || int || SPI bus with boot media ROM ||  
+
| [https://support.hp.com/us-en/product/hp-elitebook-revolve-810-g1-tablet/5298038/product-info HP]
Which SPI bus the boot media is connected to.
+
| [[Board:hp/revolve_810_g1|EliteBook Revolve 810 G1]]
 +
| style="background:#7Eff00" | [[#hp/revolve_810_g1|2018-01-13T04:50:11Z]]
 +
| Intel® IVYBRIDGE
 +
| Intel® C216
 +
|
 +
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
 +
| Socket RPGA989
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Intel
| DISPLAY_SPD_DATA || mainboard/google/cyan || bool || Display Memory Serial Presence Detect Data ||  
+
( Intel )
When enabled displays the memory configuration data.
+
| [[Board:intel/glkrvp|Glkrvp GLK Reference Board]]
 +
| style="background:red" | Unknown
 +
|  
 +
|  
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Intel
| VGA_BIOS_FILE || mainboard/google/cyan || string || ||  
+
( Intel )
The C0 version of the video bios gets computed from this name
+
| [[Board:intel/kunimitsu|Kunimitsu Skylake Reference Board]]
so that they can both be added.  Only the correct one for the
+
| style="background:red" | Unknown
system will be run.
+
|  
 +
|  
 +
|  
 +
|
 +
|
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Intel
| VGA_BIOS_ID || mainboard/google/cyan || string || ||  
+
( Intel )
The VGA_BIOS_ID for the C0 version of the video bios is hardcoded
+
| [[Board:intel/strago|Strago Braswell Reference Board]]
in soc/intel/braswell/Makefile.inc as 8086,22b1
+
| style="background:red" | Unknown
 +
|  
 +
|  
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FMDFILE || mainboard/google/kahlee || string || ||  
+
| Lenovo
The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
+
| [[Board:lenovo/g505s|LENOVO G505S]]
but in some cases more complex setups are required.
+
| style="background:#28ff00" | [[#lenovo/g505s|2018-04-09T01:03:12Z]]
When an fmd is specified, it overrides the default format.
+
| AMD Family 15h TN (AGESA)
 +
| AMD AGESA HUDSON
 +
|  
 +
| AMD Family 15h TN (AGESA)
 +
| ?
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DRAM_SIZE_MB || mainboard/google/smaug || int || BCT boot media ||  
+
| Lenovo
Which boot media to configure the BCT for.
+
| [[Board:lenovo/l520|ThinkPad L520]]
 +
| style="background:red" | Unknown
 +
| Intel® SANDYBRIDGE
 +
| Intel® BD82X6X
 +
|  
 +
| Intel® 2nd Gen (Sandybridge) Core i3/i5/i7
 +
| Socket RPGA989
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SMAUG_BCT_CFG_SPI || mainboard/google/smaug || bool || SPI ||  
+
| Lenovo
Configure the BCT for booting from SPI.
+
| [[Board:lenovo/r400|ThinkPad R400]]
 +
| style="background:#01ff00" | [[#lenovo/t400|2018-05-17T14:26:53Z]]
 +
| Intel® GM45
 +
| Intel® I82801IX
 +
| NSC PC87382
 +
NSC PC87384
 +
| INTEL_SOCKET_MPGA478MN
 +
| INTEL_SOCKET_MPGA478MN
 +
| SOIC-16 or SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SMAUG_BCT_CFG_EMMC || mainboard/google/smaug || bool || eMMC ||  
+
| Lenovo
Configure the BCT for booting from eMMC.
+
| [[Board:lenovo/s230u|ThinkPad S230U (Twist)]]
 +
| style="background:#DEff00" | [[#lenovo/s230u|2017-10-09T07:10:54Z]]
 +
| Intel® IVYBRIDGE
 +
| Intel® C216
 +
|  
 +
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
 +
| Socket RPGA989
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOOT_DEVICE_SPI_FLASH_BUS || mainboard/google/smaug || int || SPI bus with boot media ROM ||  
+
| Lenovo
Which SPI bus the boot media is connected to.
+
| [[Board:lenovo/t400|ThinkPad T400]]
 +
| style="background:#01ff00" | [[#lenovo/t400|2018-05-17T14:26:53Z]]
 +
| Intel® GM45
 +
| Intel® I82801IX
 +
| NSC PC87382
 +
NSC PC87384
 +
| INTEL_SOCKET_MPGA478MN
 +
| INTEL_SOCKET_MPGA478MN
 +
| SOIC-16
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MAINBOARD_PART_NUMBER || mainboard/google/nyan_big || string || BCT boot media ||  
+
| Lenovo
Which boot media to configure the BCT for.
+
| [[Board:lenovo/t420|ThinkPad T420]]
 +
| style="background:#FFff00" | [[#lenovo/t420|2017-04-25T04:15:46Z]]
 +
| Intel® SANDYBRIDGE
 +
| Intel® BD82X6X
 +
|
 +
| Intel® 2nd Gen (Sandybridge) Core i3/i5/i7
 +
| Socket RPGA988B
 +
| SOIC-8 / WSON-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NYAN_BIG_BCT_CFG_SPI || mainboard/google/nyan_big || bool || SPI ||  
+
| Lenovo
Configure the BCT for booting from SPI.
+
| [[Board:lenovo/t420s|ThinkPad T420s]]
 +
| style="background:red" | Unknown
 +
| Intel® SANDYBRIDGE
 +
| Intel® BD82X6X
 +
|  
 +
| Intel® 2nd Gen (Sandybridge) Core i3/i5/i7
 +
| Socket RPGA988B
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NYAN_BIG_BCT_CFG_EMMC || mainboard/google/nyan_big || bool || eMMC ||  
+
| Lenovo
Configure the BCT for booting from eMMC.
+
| [[Board:lenovo/t430|ThinkPad T430]]
 +
| style="background:#2Dff00" | [[#lenovo/t430|2018-04-03T21:38:40Z]]
 +
| Intel® IVYBRIDGE
 +
| Intel® C216
 +
|  
 +
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
 +
| Socket RPGA989
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOOT_DEVICE_SPI_FLASH_BUS || mainboard/google/nyan_big || int || SPI bus with boot media ROM ||  
+
| Lenovo
Which SPI bus the boot media is connected to.
+
| [[Board:lenovo/t430s|ThinkPad T430s]]
 +
| style="background:#B3ff00" | [[#lenovo/t430s|2017-11-21T01:38:42Z]]
 +
| Intel® IVYBRIDGE
 +
| Intel® C216
 +
|  
 +
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
 +
| Socket RPGA989
 +
| SOIC-8 / WSON-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DRAM_SIZE_MB || mainboard/google/foster || int || BCT boot media ||  
+
| Lenovo
Which boot media to configure the BCT for.
+
| [[Board:lenovo/t500|ThinkPad T500]]
 +
| style="background:#01ff00" | [[#lenovo/t400|2018-05-17T14:26:53Z]]
 +
| Intel® GM45
 +
| Intel® I82801IX
 +
| NSC PC87382
 +
NSC PC87384
 +
| INTEL_SOCKET_MPGA478MN
 +
| INTEL_SOCKET_MPGA478MN
 +
| SOIC-16 or SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FOSTER_BCT_CFG_SPI || mainboard/google/foster || bool || SPI ||  
+
| Lenovo
Configure the BCT for booting from SPI.
+
( Lenovo )
 +
| [[Board:lenovo/t520|ThinkPad T520 baseboard]]
 +
| style="background:#FFff00" | [[#lenovo/t520|2016-03-03T08:19:11Z]]
 +
| Intel® SANDYBRIDGE
 +
| Intel® BD82X6X
 +
|  
 +
| Intel® 2nd Gen (Sandybridge) Core i3/i5/i7
 +
| Socket RPGA988B
 +
| WSON-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FOSTER_BCT_CFG_EMMC || mainboard/google/foster || bool || eMMC ||  
+
| Lenovo
Configure the BCT for booting from eMMC.
+
| [[Board:lenovo/t530|ThinkPad T530]]
 +
| style="background:#FFff00" | [[#lenovo/t530|2014-09-11T14:20:53Z]]
 +
| Intel® IVYBRIDGE
 +
| Intel® C216
 +
|  
 +
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
 +
| Socket RPGA989
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOOT_DEVICE_SPI_FLASH_BUS || mainboard/google/foster || int || SPI bus with boot media ROM ||  
+
| Lenovo
Which SPI bus the boot media is connected to.
+
| [[Board:lenovo/t60|T60/T60p]]
 +
| style="background:#82ff00" | [[#lenovo/t60|2018-01-08T19:44:33Z]]
 +
| Intel® I945
 +
Intel® SUBTYPE I945GM
 +
| Intel® I82801GX
 +
TI PCI1X2X
 +
| NSC PC87382
 +
NSC PC87384
 +
| Intel® Core™ 2 Duo Mobile, Core™ Duo/Solo, Celeron® M
 +
| Socket mPGA478
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MAINBOARD_PART_NUMBER || mainboard/google/nyan || string || BCT boot media ||  
+
| Lenovo
Which boot media to configure the BCT for.
+
| [[Board:lenovo/x131e|ThinkPad X131e]]
 +
| style="background:red" | Unknown
 +
| Intel® SANDYBRIDGE
 +
| Intel® C216
 +
|  
 +
| Intel® 2nd Gen (Sandybridge) Core i3/i5/i7
 +
| Socket RPGA989
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NYAN_BCT_CFG_SPI || mainboard/google/nyan || bool || SPI ||  
+
| Lenovo
Configure the BCT for booting from SPI.
+
| [[Board:lenovo/x1_carbon_gen1|ThinkPad X1 carbon gen 1]]
 +
| style="background:#A5ff00" | [[#lenovo/x1_carbon_gen1|2017-12-05T00:29:49Z]]
 +
| Intel® IVYBRIDGE
 +
| Intel® C216
 +
|
 +
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
 +
| Socket RPGA989
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NYAN_BCT_CFG_EMMC || mainboard/google/nyan || bool || eMMC ||  
+
| Lenovo
Configure the BCT for booting from eMMC.
+
| [[Board:lenovo/x200|ThinkPad X200]]
 +
| style="background:#A4ff00" | [[#lenovo/x200|2017-12-05T19:47:14Z]]
 +
| Intel® GM45
 +
| Intel® I82801IX
 +
| NSC PC87382
 +
| Intel® Core 2 Duo (Penryn)
 +
| Socket P
 +
| SOIC-16 or SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOOT_DEVICE_SPI_FLASH_BUS || mainboard/google/nyan || int || SPI bus with boot media ROM ||  
+
| Lenovo
Which SPI bus the boot media is connected to.
+
| [[Board:lenovo/x201|ThinkPad X201]]
 +
| style="background:#03ff00" | [[#lenovo/x201|2018-05-16T06:19:34Z]]
 +
| Intel® NEHALEM
 +
| Intel® IBEXPEAK
 +
| NSC PC87382
 +
| Intel® 1st Gen (Nehalem) Core i3/i5/i7
 +
| ?
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| UART_FOR_CONSOLE || mainboard/adi/rcc-dff || int || ||  
+
| Lenovo
The Mohon Peak board uses COM2 (2f8) for the serial console.
+
| [[Board:lenovo/x220|ThinkPad X220]]
 +
| style="background:#65ff00" | [[#lenovo/x220|2018-02-06T15:30:49Z]]
 +
| Intel® SANDYBRIDGE
 +
| Intel® C216
 +
|  
 +
| Intel® 2nd Gen (Sandybridge) Core i3/i5/i7
 +
| Socket RPGA989
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
|
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PAYLOAD_CONFIGFILE || mainboard/adi/rcc-dff || string || ||  
+
| Lenovo
The Avoton/Rangeley chip does not allow devices to write into the 0xe000
+
| [[Board:lenovo/x230|ThinkPad X230]]
segment.  This means that USB/SATA devices will not work in SeaBIOS unless
+
| style="background:#03ff00" | [[#lenovo/x230|2018-05-16T07:45:28Z]]
we put the SeaBIOS buffer area down in the 0x9000 segment.
+
| Intel® IVYBRIDGE
 +
| Intel® C216
 +
|  
 +
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
 +
| Socket RPGA989
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOARD_ASUS_F2A85_M_DDR3_VOLT_135 || mainboard/asus/f2a85-m || bool || 1.35V ||
+
| Lenovo
Set DRR3 memory voltage to 1.35V
+
| [[Board:lenovo/x60|X60/X60s]]
||
+
| style="background:#04ff00" | [[#lenovo/x60|2018-05-15T03:57:13Z]]
|- bgcolor="#eeeeee"
+
| Intel® I945
| BOARD_ASUS_F2A85_M_DDR3_VOLT_150 || mainboard/asus/f2a85-m || bool || 1.50V ||  
+
Intel® SUBTYPE I945GM
Set DRR3 memory voltage to 1.50V
+
| Intel® I82801GX
||
+
RICOH RL5C476
|- bgcolor="#eeeeee"
+
| NSC PC87382
| BOARD_ASUS_F2A85_M_DDR3_VOLT_165 || mainboard/asus/f2a85-m || bool || 1.65V ||
+
NSC PC87392
Set DRR3 memory voltage to 1.65V
+
| Intel® Core™ 2 Duo Mobile, Core™ Duo/Solo, Celeron® M
||
+
| Socket mPGA478
|- bgcolor="#eeeeee"
+
| SOIC-8
| BOARD_WINNET_G170 || mainboard/winnet/g170.name || bool || WinNET G170 (Neoware CA19, IGEL 2110) ||  
+
| SPI
G170 is a board manufactured by WinNET, used in thin clients including
+
| style="background:red" | N
HP Neoware CA19 and IGEL 2110.
+
| style="background:lime" | Y
 
+
|
||
 
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BMC_INFO_LOC || mainboard/scaleway/tagada || hex || BMC information location in flash ||  
+
| Lenovo
Location of BMC SERIAL information.
+
| [[Board:lenovo/z61t|Z61t]]
 +
| style="background:red" | Unknown
 +
| Intel® I945
 +
Intel® SUBTYPE I945GM
 +
| Intel® I82801GX
 +
TI PCI1X2X
 +
| NSC PC87382
 +
NSC PC87384
 +
| Intel® Core™ 2 Duo Mobile, Core™ Duo/Solo, Celeron® M
 +
| Socket mPGA478
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Packard Bell
| NO_POST || mainboard/purism/librem_skl || int || ||  
+
| [[Board:packardbell/ms2290|EasyNote LM85 (MS2290)]]
This platform does not have any way to see POST codes
+
| style="background:#FFff00" | [[#packardbell/ms2290|2014-08-01T17:32:20Z]]
so disable them by default.
+
| Intel® NEHALEM
 +
| Intel® IBEXPEAK
 +
|  
 +
| Intel® 1st Gen (Nehalem) Core i3/i5/i7
 +
| ?
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DRIVERS_PS2_KEYBOARD || mainboard/purism/librem_bdw || string || ||  
+
| Purism
Default PS/2 Keyboard to enabled on this board.
+
( Purism )
 +
| [[Board:purism/librem_bdw|Librem Broadwell baseboard]]
 +
| style="background:#02ff00" | [[#purism/librem_bdw|2018-05-16T19:00:17Z]]
 +
|
 +
|
 +
|  
 +
|  
 +
|  
 +
| SOIC8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DRIVERS_UART_8250IO || mainboard/purism/librem_bdw || string || ||  
+
| Purism
This platform does not have any way to get standard
+
( Purism )
serial output so disable it by default.
+
| [[Board:purism/librem_skl|Librem Skylake baseboard]]
 +
| style="background:#00ff00" | [[#purism/librem_skl|2018-05-18T19:06:18Z]]
 +
|  
 +
|  
 +
|  
 +
|  
 +
|
 +
| SOIC8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.roda-computer.com/en/products/notebooks/rocky-iii-rk886ex.html Roda]
| NO_POST || mainboard/purism/librem_bdw || int || ||  
+
| [[Board:roda/rk886ex|RK886EX (Rocky III+)]]
This platform does not have any way to see POST codes
+
| style="background:red" | Unknown
so disable them by default.
+
| Intel® I945
 +
Intel® SUBTYPE I945GM
 +
| Intel® I82801GX
 +
TI PCI7420
 +
| SMSC® LPC47N227
 +
RENESAS M3885X
 +
| Intel® Core™ 2 Duo Mobile, Core™ Duo/Solo, Celeron® M
 +
| Socket mPGA478
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Roda
| || || (comment) || || was acquired by ADLINK ||
+
| [[Board:roda/rk9|RK9]]
|- bgcolor="#eeeeee"
+
| style="background:red" | Unknown
| ONBOARD_UARTS_RS485 || mainboard/lippert/spacerunner-lx || bool || Switch on-board serial ports to RS485 ||  
+
| Intel® GM45
If selected, both on-board serial ports will operate in RS485 mode
+
| Intel® I82801IX
instead of RS232.
+
| SMSC® LPC47N227
 +
| Intel® Core 2 Duo (Penryn)
 +
| Socket P
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Roda
| ONBOARD_IDE_SLAVE || mainboard/lippert/spacerunner-lx || bool || Make on-board SSD act as Slave ||  
+
| [[Board:roda/rv11|RV11]]
If selected, the on-board SSD will act as IDE Slave instead of Master.
+
| style="background:red" | Unknown
 +
| Intel® IVYBRIDGE
 +
| Intel® C216
 +
| ITE™ IT8783EF if BOARD RODA RW11
 +
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
 +
| Socket RPGA989
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
|
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOARD_OLD_REVISION || mainboard/lippert/hurricane-lx || bool || Board is old pre-3.0 revision ||  
+
| SAMSUNG
Look on the bottom side for a number like 406-0001-30.  The last 2
+
( Samsung )
digits state the PCB revision (3.0 in this example).  For 2.0 or older
+
| [[Board:samsung/lumpy|Series 5 550 Chromebook]]
boards choose Y, for 3.0 and newer say N.
+
| style="background:#FFff00" | [[#samsung/lumpy|2017-03-17T21:13:34Z]]
 +
| Intel® SANDYBRIDGE
 +
| Intel® BD82X6X
 +
| SMSC® MEC1308
 +
SMSC® LPC47N207
 +
| Intel® 2nd Gen (Sandybridge) Core i3/i5/i7
 +
| Socket RPGA989
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
Old revision boards need a jumper shorting the power button to
+
|- bgcolor="#6699ff"
power on automatically.  You may enable the button only after this
+
| colspan="13" | <h4>Servers</h4>
jumper has been removed.  New revision boards are not restricted
 
in this way, and always have the power button enabled.
 
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| AMD
| ONBOARD_UARTS_RS485 || mainboard/lippert/hurricane-lx || bool || Switch on-board serial ports to RS485 ||  
+
| [[Board:amd/serengeti_cheetah|Serengeti Cheetah]]
If selected, both on-board serial ports will operate in RS485 mode
+
| style="background:red" | Unknown
instead of RS232.
+
| AMD AMDK8
 +
| AMD AMD8132
 +
AMD AMD8151
 +
AMD AMD8111
 +
AMD AMD8131
 +
| Winbond™ W83627HF
 +
| AMD Opteron™
 +
| Socket F
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| AMD
| ONBOARD_UARTS_RS485 || mainboard/lippert/literunner-lx || bool || Switch on-board serial ports 1 &amp; 2 to RS485 ||  
+
| [[Board:amd/serengeti_cheetah_fam10|Serengeti Cheetah (Fam10)]]
If selected, the first two on-board serial ports will operate in RS485
+
| style="background:red" | Unknown
mode instead of RS232.
+
| AMD Family 10h
 +
| AMD AMD8111
 +
AMD AMD8132
 +
| Winbond™ W83627HF
 +
| AMD Opteron™
 +
| Socket F 1207
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ONBOARD_IDE_SLAVE || mainboard/lippert/literunner-lx || bool || Make on-board CF socket act as Slave ||  
+
| [ftp://ftp.aopen.com/pub/server/motherboard/dxplpu/manual/dxplpu-ol-e.pdf AOpen]
If selected, the on-board Compact Flash card socket will act as IDE
+
| [[Board:aopen/dxplplusu|DXPL Plus-U]]
Slave instead of Master.
+
| style="background:#FFff00" | [[#aopen/dxplplusu|2016-12-04T02:03:58Z]]
 +
| Intel® E7505
 +
| Intel® I82870
 +
Intel® I82801DX
 +
| SMSC® LPC47M10X
 +
| Intel® Xeon®
 +
| Socket 604
 +
| PLCC
 +
| FWH
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| ASUS
| ONBOARD_UARTS_RS485 || mainboard/lippert/roadrunner-lx || bool || Switch on-board serial ports to RS485 ||  
+
| [[Board:asus/kcma-d8|KCMA-D8]]
If selected, both on-board serial ports will operate in RS485 mode
+
| style="background:#1Dff00" | [[#asus/kcma-d8|2018-04-19T15:05:08Z]]
instead of RS232.
+
| AMD Family 10h
 +
| AMD SR5650
 +
AMD SB700
 +
AMD SUBTYPE SP5100
 +
| Winbond™ W83667HG A
 +
| AMD Opteron™ Magny-Cours/Interlagos
 +
| Socket C32
 +
| DIP-8
 +
| SPI
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| ASUS
| || || (comment) || || see under vendor LiPPERT ||
+
| [[Board:asus/kfsn4-dre|KFSN4-DRE]]
|- bgcolor="#eeeeee"
+
| style="background:#5Cff00" | [[#asus/kfsn4-dre|2018-02-15T18:30:23Z]]
| || || (comment) || || WARNING: This mainboard uses LATE_CBMEM_INIT, which is deprecated ||
+
| AMD Family 10h
|- bgcolor="#eeeeee"
+
| NVIDIA CK804
| BOARD_ROMSIZE_KB_65536 || mainboard || bool || ROM chip size ||
+
| Winbond™ W83627THG
Select the size of the ROM chip you intend to flash coreboot on.
+
| AMD Opteron™
 +
| Socket F 1207
 +
| PLCC-32
 +
| LPC
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
|
  
The build system will take care of creating a coreboot.rom file
+
|- bgcolor="#dddddd"
of the matching size.
+
| ASUS
 +
| [[Board:asus/kfsn4-dre_k8|KFSN4-DRE_K8]]
 +
| style="background:#FFff00" | [[#asus/kfsn4-dre_k8|2016-08-22T02:19:24Z]]
 +
| AMD AMDK8
 +
| NVIDIA CK804
 +
| Winbond™ W83627THG
 +
| AMD Opteron™
 +
| Socket F
 +
| PLCC-32
 +
| LPC
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| ASUS
| COREBOOT_ROMSIZE_KB_64 || mainboard || bool || 64 KB ||  
+
| [[Board:asus/kgpe-d16|KGPE-D16]]
Choose this option if you have a 64 KB ROM chip.
+
| style="background:#0Fff00" | [[#asus/kgpe-d16|2018-05-03T17:31:02Z]]
 +
| AMD Family 10h
 +
| AMD SR5650
 +
AMD SB700
 +
AMD SUBTYPE SP5100
 +
| Winbond™ W83667HG A
 +
| AMD Opteron™ Magny-Cours/Interlagos
 +
| Socket G34
 +
| DIP-8
 +
| SPI
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_128 || mainboard || bool || 128 KB ||  
+
| [http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us&objectID=c00346784&prodTypeId=15351&prodSeriesId=3219755 HP]
Choose this option if you have a 128 KB ROM chip.
+
| [[Board:hp/dl145_g1|ProLiant DL145 G1]]
 +
| style="background:red" | Unknown
 +
| AMD AMDK8
 +
| AMD AMD8131
 +
AMD AMD8111
 +
| Winbond™ W83627HF
 +
| AMD Opteron™
 +
| Socket 940
 +
| PLCC
 +
| LPC
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_256 || mainboard || bool || 256 KB ||  
+
| [http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?objectID=c00816835&lang=en&cc=us&taskId=101&prodSeriesId=3219755&prodTypeId=15351 HP]
Choose this option if you have a 256 KB ROM chip.
+
| [[Board:hp/dl145_g3|ProLiant DL145 G3]]
 +
| style="background:red" | Unknown
 +
| AMD AMDK8
 +
| BROADCOM BCM21000
 +
BROADCOM BCM5785
 +
| SERVERENGINES PILOT
 +
NSC PC87417
 +
| AMD Opteron™
 +
| Socket F
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_512 || mainboard || bool || 512 KB ||  
+
| [http://h20000.www2.hp.com/bizsupport/TechSupport/Document.jsp?lang=en&cc=us&objectID=c01765799 HP]
Choose this option if you have a 512 KB ROM chip.
+
| [[Board:hp/dl165_g6_fam10|ProLiant DL165 G6 (Fam10)]]
 +
| style="background:red" | Unknown
 +
| AMD Family 10h
 +
| BROADCOM BCM21000
 +
BROADCOM BCM5785
 +
| SERVERENGINES PILOT
 +
NSC PC87417
 +
| AMD Opteron™
 +
| Socket F 1207
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://web.archive.org/web/20060507170150/http://www.iwill.net/product_2.asp?p_id=98 IWILL]
| COREBOOT_ROMSIZE_KB_1024 || mainboard || bool || 1024 KB (1 MB) ||  
+
| [[Board:iwill/dk8_htx|DK8-HTX]]
Choose this option if you have a 1024 KB (1 MB) ROM chip.
+
| style="background:red" | Unknown
 +
| AMD AMDK8
 +
| AMD AMD8111
 +
AMD AMD8131
 +
| Winbond™ W83627HF
 +
| AMD Opteron™
 +
| Socket 940
 +
| ?
 +
| ?
 +
| ?
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_2048 || mainboard || bool || 2048 KB (2 MB) ||  
+
| [http://www.msiserver.de/de/Produkte/Server_Mainboards/K9SD_Master_S2R_MS_9185.aspx MSI]
Choose this option if you have a 2048 KB (2 MB) ROM chip.
+
| [[Board:msi/ms9185|K9SD Master-S2R (MS-9185)]]
 +
| style="background:red" | Unknown
 +
| AMD AMDK8
 +
| BROADCOM BCM5780
 +
BROADCOM BCM5785
 +
| NSC PC87417
 +
| AMD Opteron™
 +
| Socket F
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_4096 || mainboard || bool || 4096 KB (4 MB) ||  
+
| [http://cweb.msi.com.tw/program/products/server/svr/pro_svr_detail.php?UID=632 MSI]
Choose this option if you have a 4096 KB (4 MB) ROM chip.
+
| [[Board:msi/ms9282|K9SD Master (MS-9282)]]
 +
| style="background:red" | Unknown
 +
| AMD AMDK8
 +
| NVIDIA MCP55
 +
| Winbond™ W83627EHG
 +
| AMD Opteron™
 +
| Socket F
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Open Compute Project
| COREBOOT_ROMSIZE_KB_8192 || mainboard || bool || 8192 KB (8 MB) ||  
+
| [[Board:ocp/monolake|Mono Lake]]
Choose this option if you have a 8192 KB (8 MB) ROM chip.
+
| style="background:red" | Unknown
 +
|  
 +
|  
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| SPI
 +
| yes
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Open Compute Project
| COREBOOT_ROMSIZE_KB_10240 || mainboard || bool || 10240 KB (10 MB) ||  
+
| [[Board:ocp/wedge100s|Wedge 100S]]
Choose this option if you have a 10240 KB (10 MB) ROM chip.
+
| style="background:red" | Unknown
 +
|  
 +
|  
 +
| ITE™ COMMON ROMSTAGE
 +
|  
 +
|  
 +
| ?
 +
| SPI
 +
| yes
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| COREBOOT_ROMSIZE_KB_12288 || mainboard || bool || 12288 KB (12 MB) ||  
+
| Scaleway
Choose this option if you have a 12288 KB (12 MB) ROM chip.
+
( Scaleway )
 +
| [[Board:scaleway/tagada|Tagada]]
 +
| style="background:red" | Unknown
 +
|
 +
|
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.supermicro.com/Aplus/motherboard/Opteron2000/MCP55/H8DME-2.cfm Supermicro]
| COREBOOT_ROMSIZE_KB_16384 || mainboard || bool || 16384 KB (16 MB) ||  
+
| [[Board:supermicro/h8dme|H8DME-2]]
Choose this option if you have a 16384 KB (16 MB) ROM chip.
+
| style="background:red" | Unknown
 +
| AMD AMDK8
 +
| NVIDIA MCP55
 +
| Winbond™ W83627HF
 +
| AMD Opteron™
 +
| Socket F
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.supermicro.com/Aplus/motherboard/Opteron2000/MCP55/H8DMR-i2.cfm Supermicro]
| COREBOOT_ROMSIZE_KB_32768 || mainboard || bool || 32768 KB (32 MB) ||  
+
| [[Board:supermicro/h8dmr|H8DMR-i2]]
Choose this option if you have a 32768 KB (32 MB) ROM chip.
+
| style="background:red" | Unknown
 +
| AMD AMDK8
 +
| NVIDIA MCP55
 +
| Winbond™ W83627HF
 +
| AMD Opteron™
 +
| Socket F
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Supermicro
| COREBOOT_ROMSIZE_KB_65536 || mainboard || bool || 65536 KB (64 MB) ||  
+
| [[Board:supermicro/h8dmr_fam10|H8DMR-i2 (Fam10)]]
Choose this option if you have a 65536 KB (64 MB) ROM chip.
+
| style="background:red" | Unknown
 +
| AMD Family 10h
 +
| NVIDIA MCP55
 +
| Winbond™ W83627HF
 +
| AMD Opteron™
 +
| Socket F 1207
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.supermicro.com/Aplus/motherboard/Opteron8000/MCP55/H8QME-2.cfm Supermicro]
| ENABLE_POWER_BUTTON || mainboard || bool || Enable the power button ||  
+
| [[Board:supermicro/h8qme_fam10|H8QME-2+ (Fam10)]]
The selected mainboard can optionally have the power button tied
+
| style="background:red" | Unknown
to ground with a jumper so that the button appears to be
+
| AMD Family 10h
constantly depressed. If this option is enabled and the jumper is
+
| AMD AMD8132
installed then the board will turn on, but turn off again after a
+
NVIDIA MCP55
short timeout, usually 4 seconds.
+
| Winbond™ W83627HF
 +
| AMD Opteron™
 +
| Socket F 1207
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
Select Y here if you have removed the jumper and want to use an
+
|- bgcolor="#dddddd"
actual power button. Select N if you have the jumper installed.
+
| Supermicro
 +
| [[Board:supermicro/h8scm_fam10|H8SCM (Fam10)]]
 +
| style="background:red" | Unknown
 +
| AMD Family 10h
 +
| AMD SR5650
 +
AMD SB700
 +
AMD SUBTYPE SP5100
 +
| Winbond™ W83627HF
 +
Nuvoton  WPCM450
 +
| AMD Opteron™ Magny-Cours/Interlagos
 +
| Socket C32
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DEVICETREE || toplevel || string || ||  
+
| [http://www.tyan.com/product_board_detail.aspx?pid=157 Tyan]
This symbol allows mainboards to select a different file under their
+
| [[Board:tyan/s2912|Thunder n3600R (S2912)]]
mainboard directory for the devicetree.cb file.  This allows the board
+
| style="background:red" | Unknown
variants that need different devicetrees to be in the same directory.
+
| AMD AMDK8
 
+
| NVIDIA MCP55
Examples: "devicetree.variant.cb"
+
| Winbond™ W83627HF
"variant/devicetree.cb"
+
| AMD Opteron™
 +
| Socket F
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CBFS_SIZE || toplevel || hex || Size of CBFS filesystem in ROM ||  
+
| Tyan
This is the part of the ROM actually managed by CBFS, located at the
+
| [[Board:tyan/s2912_fam10|S2912 (Fam10)]]
end of the ROM (passed through cbfstool -o) on x86 and at at the start
+
| style="background:red" | Unknown
of the ROM (passed through cbfstool -s) everywhere else. It defaults
+
| AMD Family 10h
to span the whole ROM on all but Intel systems that use an Intel Firmware
+
| NVIDIA MCP55
Descriptor.  It can be overridden to make coreboot live alongside other
+
| Winbond™ W83627HF
components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
+
| AMD Opteron™
binaries.
+
| Socket F 1207
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#6699ff"
|- bgcolor="#eeeeee"
+
| colspan="13" | <h4>Desktops / Workstations</h4>
| FMDFILE || toplevel || string || fmap description file in fmd format ||  
 
The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
 
but in some cases more complex setups are required.
 
When an fmd is specified, it overrides the default format.
 
  
||
+
|- bgcolor="#dddddd"
 +
| [http://www.asrock.com/mb/overview.asp?Model=939A785GMH/128M&s=939 ASROCK]
 +
| [[Board:asrock/939a785gmh|939A785GMH/128M]]
 +
| style="background:#B5ff00" | [[#asrock/939a785gmh|2017-11-19T01:50:13Z]]
 +
| AMD AMDK8
 +
| AMD RS780
 +
AMD SB700
 +
| Winbond™ W83627DHG
 +
| AMD Athlon™ 64 / FX / X2
 +
| Socket 939
 +
| DIP8
 +
| SPI
 +
| ?
 +
| ?
 +
| —
  
|- bgcolor="#eeeeee"
+
|- bgcolor="#dddddd"
| CBFS_AUTOGEN_ATTRIBUTES || toplevel || bool ||  ||  
+
| [http://www.asrock.com/mb/Intel/B75%20Pro3-M/ ASROCK]
If this option is selected, every file in cbfs which has a constraint
+
| [[Board:asrock/b75pro3-m|B75 Pro3-M]]
regarding position or alignment will get an additional file attribute
+
| style="background:#DBff00" | [[#asrock/b75pro3-m|2017-10-12T02:45:41Z]]
which describes this constraint.
+
| Intel® IVYBRIDGE
 +
| Intel® C216
 +
| Nuvoton NCT6776
 +
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
 +
| Socket RPGA989
 +
| DIP-8
 +
| SPI
 +
| style="background:lime" | Y
 +
| style="background:red" | N
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#6699dd"
+
| [http://www.asrock.com/mb/intel/g41c-gs/ ASROCK]
! align="left" | Menu: Chipset || || || ||
+
| [[Board:asrock/g41c-gs|G41C-GS R2.0]]
|- bgcolor="#eeeeee"
+
| style="background:#FFff00" | [[#asrock/g41c-gs|2017-08-31T13:23:34Z]]
| || || (comment) || || SoC ||
+
| Intel® X4X
|- bgcolor="#eeeeee"
+
| Intel® I82801GX
| MAINBOARD_DO_DSI_INIT || soc/nvidia/tegra210 || bool || Use dsi graphics interface ||
+
| Nuvoton  NCT6776
Initialize dsi display
+
| Intel® Core 2, Pentium 4/D
 +
| Socket LGA775
 +
| DIP-8
 +
| SPI
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
|
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MAINBOARD_DO_SOR_INIT || soc/nvidia/tegra210 || bool || Use dp graphics interface ||  
+
| [http://www.asus.com/Motherboards/AMD_Socket_939/A8NE/ ASUS]
Initialize dp display
+
| [[Board:asus/a8n_e|A8N-E]]
 +
| style="background:#FFff00" | [[#asus/a8n_e|2014-02-25T19:03:49Z]]
 +
| AMD AMDK8
 +
| NVIDIA CK804
 +
| ITE™ IT8712F
 +
| AMD Athlon™ 64 / FX / X2
 +
| Socket 939
 +
| PLCC
 +
| LPC
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_TEGRA210_UARTA || soc/nvidia/tegra210 || bool || UARTA ||  
+
| [http://www.asus.com/Motherboards/AMD_Socket_939/A8NSLI/ ASUS]
Serial console on UART A.
+
| [[Board:asus/a8n_sli|A8N-SLI]]
 +
| style="background:#FFff00" | [[#asus/a8n_e|2014-02-25T19:03:49Z]]
 +
| AMD AMDK8
 +
| NVIDIA CK804
 +
| ITE™ IT8712F
 +
| AMD Athlon™ 64 / FX / X2
 +
| Socket 939
 +
| PLCC
 +
| ?
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_TEGRA210_UARTB || soc/nvidia/tegra210 || bool || UARTB ||  
+
| [http://www.asus.com/Motherboards/AMD_Socket_939/A8VE_Deluxe/ ASUS]
Serial console on UART B.
+
| [[Board:asus/a8v-e_deluxe|A8V-E Deluxe]]
 +
| style="background:red" | Unknown
 +
| AMD AMDK8
 +
| VIA VT8237R
 +
VIA K8T890
 +
VIA SUBTYPE K8T890
 +
| Winbond™ W83627EHG
 +
| AMD Athlon™ 64 / FX / X2
 +
| Socket 939
 +
| PLCC
 +
| ?
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_TEGRA210_UARTC || soc/nvidia/tegra210 || bool || UARTC ||  
+
| [http://www.asus.com/Motherboards/AMD_Socket_939/A8VE_SE/ ASUS]
Serial console on UART C.
+
| [[Board:asus/a8v-e_se|A8V-E SE]]
 +
| style="background:#FFff00" | [[#asus/a8v-e_se|2014-01-03T17:47:48Z]]
 +
| AMD AMDK8
 +
| VIA VT8237R
 +
VIA K8T890
 +
VIA SUBTYPE K8T890
 +
| Winbond™ W83627EHG
 +
| AMD Athlon™ 64 / FX / X2
 +
| Socket 939
 +
| PLCC
 +
| LPC
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_TEGRA210_UARTD || soc/nvidia/tegra210 || bool || UARTD ||  
+
| [http://www.asus.com/Motherboards/AMD_Socket_FM2/F2A85M/ ASUS]
Serial console on UART D.
+
| [[Board:asus/f2a85-m|F2A85-M]]
 +
| style="background:#FFff00" | [[#asus/f2a85-m|2017-09-04T11:13:36Z]]
 +
| AMD Family 15h TN (AGESA)
 +
| AMD AGESA HUDSON
 +
| ITE™ IT8728F if BOARD ASUS F2A85 M || BOARD ASUS F2A85 M LE
 +
Nuvoton  NCT6779D if BOARD ASUS F2A85 M PRO
 +
| AMD Family 15h TN (AGESA)
 +
| ?
 +
| DIP8
 +
| [http://www.winbond-usa.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/SerialFlash/W25Q64BV.htm SPI]
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_TEGRA210_UARTE || soc/nvidia/tegra210 || bool || UARTE ||  
+
| ASUS
Serial console on UART E.
+
| [[Board:asus/k8v-x|K8V-X]]
 +
| style="background:red" | Unknown
 +
| AMD AMDK8
 +
| VIA VT8237R
 +
VIA K8T890
 +
VIA SUBTYPE K8T800 OLD
 +
| Winbond™ W83697HF
 +
| AMD Sempron™ / Athlon™ 64 / Turion™ 64
 +
| Socket 754
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
|
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CONSOLE_SERIAL_TEGRA210_UART_ADDRESS || soc/nvidia/tegra210 || hex || ||  
+
| [http://www.asus.com/Motherboards/AMD_AM2/M2NE/ ASUS]
Map the UART names to the respective MMIO addres.
+
| [[Board:asus/m2n-e|M2N-E]]
 +
| style="background:red" | Unknown
 +
| AMD AMDK8
 +
| NVIDIA MCP55
 +
| ITE™ IT8716F
 +
| ?
 +
| Socket AM2
 +
| PLCC
 +
| LPC
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| BOOTROM_SDRAM_INIT || soc/nvidia/tegra210 || bool || SoC BootROM does SDRAM init with full BCT ||  
+
| [http://www.asus.com/Motherboards/AMD_AM2/M2V/ ASUS]
Use during Foster LPDDR4 bringup.
+
| [[Board:asus/m2v|M2V]]
 +
| style="background:red" | Unknown
 +
| AMD AMDK8
 +
| VIA VT8237R
 +
VIA K8T890
 +
VIA SUBTYPE K8T890
 +
| ITE™ IT8712F
 +
| ?
 +
| Socket AM2
 +
| PLCC
 +
| LPC
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| TRUSTZONE_CARVEOUT_SIZE_MB || soc/nvidia/tegra210 || hex || Size of Trust Zone region ||  
+
| [http://www.asus.com/Motherboards/AMD_AM2/M2VMX_SE/ ASUS]
Size of Trust Zone area in MiB to reserve in memory map.
+
| [[Board:asus/m2v-mx_se|M2V-MX SE]]
 +
| style="background:#A1ff00" | [[#asus/m2v-mx_se|2017-12-09T03:28:27Z]]
 +
| AMD AMDK8
 +
| VIA VT8237R
 +
VIA K8T890
 +
VIA SUBTYPE K8M890
 +
| ITE™ IT8712F
 +
| ?
 +
| Socket AM2
 +
| DIP8
 +
| SPI
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| TTB_SIZE_MB || soc/nvidia/tegra210 || hex || Size of TTB ||  
+
| [http://www.asus.com/Motherboards/AMD_AM2Plus/M4A78EM/ ASUS]
Maximum size of Translation Table Buffer in MiB.
+
| [[Board:asus/m4a78-em|M4A78-EM]]
 +
| style="background:red" | Unknown
 +
| AMD Family 10h
 +
| AMD RS780
 +
AMD SB700
 +
| ITE™ IT8712F
 +
| AMD Athlon™ 64 / FX / X2
 +
| Socket AM3
 +
| DIP8
 +
| SPI
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SEC_COMPONENT_SIZE_MB || soc/nvidia/tegra210 || hex || Size of resident EL3 components ||  
+
| [http://www.asus.com/Motherboards/AMD_AM2Plus/M4A785M/ ASUS]
Maximum size of resident EL3 components in MiB including BL31 and
+
| [[Board:asus/m4a785-m|M4A785-M]]
Secure OS.
+
| style="background:red" | Unknown
 +
| AMD Family 10h
 +
| AMD RS780
 +
AMD SB700
 +
| ITE™ IT8712F
 +
| AMD Athlon™ 64 / FX / X2
 +
| Socket AM3
 +
| DIP8
 +
| SPI
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HAVE_MTC || soc/nvidia/tegra210 || bool || Add external Memory controller Training Code binary ||  
+
| [http://www.asus.com/Motherboards/AMD_AM3/M4A785TM/ ASUS]
Select this option to add emc training firmware
+
| [[Board:asus/m4a785t-m|M4A785T-M]]
 +
| style="background:#FFff00" | [[#asus/m4a785t-m|2015-10-22T18:20:48Z]]
 +
| AMD Family 10h
 +
| AMD RS780
 +
AMD SB700
 +
| ITE™ IT8712F
 +
| AMD Athlon™ 64 / FX / X2
 +
| Socket AM3
 +
| DIP8
 +
| SPI
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MTC_FILE || soc/nvidia/tegra210 || string || tegra mtc firmware filename ||  
+
| [http://www.asus.com/Motherboards/AMD_AM3Plus/M5A88V_EVO/ ASUS]
The filename of the mtc firmware
+
| [[Board:asus/m5a88-v|M5A88-V]]
 +
| style="background:red" | Unknown
 +
| AMD Family 10h
 +
| AMD RS780
 +
AMD SB800
 +
| ITE™ IT8721F
 +
| AMD Athlon™ 64 / FX / X2
 +
| Socket AM3
 +
| DIP8
 +
| SPI
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MTC_DIRECTORY || soc/nvidia/tegra210 || string || Directory where MTC firmware file is located ||  
+
| [https://www.asus.com/ROG-Republic-Of-Gamers/MAXIMUS_IV_GENEZ/ ASUS]
Path to directory where MTC firmware file is located.
+
| [[Board:asus/maximus_iv_gene-z|Maximus IV GENE-Z]]
 +
| style="background:#2Aff00" | [[#asus/maximus_iv_gene-z|2018-04-06T10:29:01Z]]
 +
| Intel® SANDYBRIDGE
 +
| Intel® BD82X6X
 +
| Nuvoton  NCT6776
 +
| Intel® 2nd Gen (Sandybridge) Core i3/i5/i7
 +
| Socket LGA1155
 +
| DIP-8
 +
| SPI
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MTC_ADDRESS || soc/nvidia/tegra210 || hex || ||  
+
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b/ ASUS]
The DRAM location where MTC firmware to be loaded in. This location
+
| [[Board:asus/p2b|P2B]]
needs to be consistent with the location defined in tegra_mtc.ld
+
| style="background:#9Bff00" | [[#asus/p2b|2017-12-15T03:32:04Z]]
 +
| Intel® I440BX
 +
| Intel® I82371EB
 +
| Winbond™ W83977TF
 +
| Intel® Pentium® II/III, Celeron®
 +
| Slot 1
 +
| DIP32
 +
| Parallel
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_APOLLOLAKE || soc/intel/apollolake || bool || ||  
+
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-d/ ASUS]
Intel Apollolake support
+
| [[Board:asus/p2b-d|P2B-D]]
 +
| style="background:red" | Unknown
 +
| Intel® I440BX
 +
| Intel® I82371EB
 +
| Winbond™ W83977TF
 +
| Intel® Pentium® II/III, Celeron®
 +
| Slot 1
 +
| DIP32
 +
| Parallel
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_GLK || soc/intel/apollolake || bool || ||  
+
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-ds/ ASUS]
Intel GLK support
+
| [[Board:asus/p2b-ds|P2B-DS]]
 +
| style="background:red" | Unknown
 +
| Intel® I440BX
 +
| Intel® I82371EB
 +
| Winbond™ W83977TF
 +
| Intel® Pentium® II/III, Celeron®
 +
| Slot 1
 +
| DIP32
 +
| Parallel
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| TPM_ON_FAST_SPI || soc/intel/apollolake || bool || ||  
+
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-f/ ASUS]
TPM part is conntected on Fast SPI interface, but the LPC MMIO
+
| [[Board:asus/p2b-f|P2B-F]]
TPM transactions are decoded and serialized over the SPI interface.
+
| style="background:red" | Unknown
 +
| Intel® I440BX
 +
| Intel® I82371EB
 +
| Winbond™ W83977TF
 +
| Intel® Pentium® II/III, Celeron®
 +
| Slot 1
 +
| DIP32
 +
| Parallel
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PCR_BASE_ADDRESS || soc/intel/apollolake || hex || ||  
+
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-ls/ ASUS]
This option allows you to select MMIO Base Address of sideband bus.
+
| [[Board:asus/p2b-ls|P2B-LS]]
 +
| style="background:#F7ff00" | [[#asus/p2b-ls|2017-09-13T17:26:27Z]]
 +
| Intel® I440BX
 +
| Intel® I82371EB
 +
| Winbond™ W83977TF
 +
| Intel® Pentium® II/III, Celeron®
 +
| Slot 1
 +
| DIP32
 +
| Parallel
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DCACHE_RAM_SIZE || soc/intel/apollolake || hex || ||  
+
| [ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p3b-f/ ASUS]
The size of the cache-as-ram region required during bootblock
+
| [[Board:asus/p3b-f|P3B-F]]
and/or romstage.
+
| style="background:#F7ff00" | [[#asus/p3b-f|2017-09-13T17:26:27Z]]
 +
| Intel® I440BX
 +
| Intel® I82371EB
 +
| Winbond™ W83977TF
 +
| Intel® Pentium® II/III, Celeron®
 +
| Slot 1
 +
| DIP32
 +
| Parallel
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DCACHE_BSP_STACK_SIZE || soc/intel/apollolake || hex || ||  
+
| [https://www.asus.com/Motherboards/P5GCMX/ ASUS]
The amount of anticipated stack usage in CAR by bootblock and
+
| [[Board:asus/p5gc-mx|P5GC-MX]]
other stages.
+
| style="background:#FFff00" | [[#asus/p5gc-mx|2017-06-17T18:00:03Z]]
 +
| Intel® I945
 +
Intel® SUBTYPE I945GC
 +
| Intel® I82801GX
 +
| Winbond™ W83627DHG
 +
| Intel® Core 2, Pentium 4/D
 +
| Socket LGA775
 +
| DIP-8
 +
| SPI
 +
| style="background:lime" | Y
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.avalue.com.tw/en/product/detail.aspx?ccid=2&cid=9&id=68&zid=245 AVALUE]
| ROMSTAGE_ADDR || soc/intel/apollolake || hex || ||  
+
| [[Board:avalue/eax-785e|EAX-785E]]
The base address (in CAR) where romstage should be linked
+
| style="background:red" | Unknown
 +
| AMD Family 10h
 +
| AMD RS780
 +
AMD SB800
 +
| Winbond™ W83627HF #COM1, COM2
 +
#FINTEK F81216AD #COM3, COM4
 +
| AMD Athlon™ 64 / FX / X2
 +
| Socket AM3
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| VERSTAGE_ADDR || soc/intel/apollolake || hex || ||  
+
| [http://www.foxconnchannel.com/ProductDetail.aspx?T=motherboard&U=en-us0000455 Foxconn]
The base address (in CAR) where verstage should be linked
+
| [[Board:foxconn/g41s-k|G41S-K]]
 +
| style="background:#9Fff00" | [[#foxconn/g41s-k|2017-12-11T07:06:21Z]]
 +
| Intel® X4X
 +
| Intel® I82801GX
 +
| ITE™ IT8720F
 +
| Intel® Core 2, Pentium 4/D
 +
| Socket LGA775
 +
| DIP-8
 +
| SPI
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.gigabyte.com/products/product-page.aspx?pid=2669#ov GIGABYTE]
| FSP_M_ADDR || soc/intel/apollolake || hex || ||  
+
| [[Board:gigabyte/ga-945gcm-s2l|GA-945GCM-S2L]]
The address FSP-M will be relocated to during build time
+
| style="background:#FFff00" | [[#gigabyte/ga-945gcm-s2l|2017-04-17T16:12:02Z]]
 +
| Intel® I945
 +
Intel® SUBTYPE I945GC
 +
| Intel® I82801GX
 +
| ITE™ IT8718F
 +
| Intel® Core 2, Pentium 4/D
 +
| Socket LGA775
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.gigabyte.com/products/product-page.aspx?pid=4150#sp GIGABYTE]
| NEED_LBP2 || soc/intel/apollolake || bool || Write contents for logical boot partition 2. ||  
+
| [[Board:gigabyte/ga-b75m-d3h|GA-B75M-D3H]]
Write the contents from a file into the logical boot partition 2
+
| style="background:#B5ff00" | [[#gigabyte/ga-b75m-d3h|2017-11-19T01:50:13Z]]
region defined by LBP2_FMAP_NAME.
+
| Intel® IVYBRIDGE
 +
| Intel® C216
 +
| ITE™ IT8728F
 +
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
 +
| Socket LGA1155
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.gigabyte.com/products/product-page.aspx?pid=4151#ov GIGABYTE]
| LBP2_FMAP_NAME || soc/intel/apollolake || string || Name of FMAP region to put logical boot partition 2 ||  
+
| [[Board:gigabyte/ga-b75m-d3v|GA-B75M-D3V]]
Name of FMAP region to write logical boot partition 2 data.
+
| style="background:#B5ff00" | [[#gigabyte/ga-b75m-d3v|2017-11-19T01:50:13Z]]
 +
| Intel® IVYBRIDGE
 +
| Intel® C216
 +
| ITE™ IT8728F
 +
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
 +
| Socket LGA1155
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.gigabyte.com/products/product-page.aspx?pid=3024#ov GIGABYTE]
| LBP2_FILE_NAME || soc/intel/apollolake || string || Path of file to write to logical boot partition 2 region ||  
+
| [[Board:gigabyte/ga-g41m-es2l|GA-G41M-ES2L]]
Name of file to store in the logical boot partition 2 region.
+
| style="background:#0Dff00" | [[#gigabyte/ga-g41m-es2l|2018-05-06T06:18:48Z]]
 +
| Intel® X4X
 +
| Intel® I82801GX
 +
| ITE™ IT8718F
 +
| Intel® Core 2, Pentium 4/D
 +
| Socket LGA775
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.computerbase.de/news/hardware/mainboards/amd-systeme/2007/mai/gigabyte_dtx-mainboard/ GIGABYTE]
| NEED_IFWI || soc/intel/apollolake || bool || Write content into IFWI region ||  
+
| [[Board:gigabyte/ga_2761gxdk|GA-2761GXDK (Churchill)]]
Write the content from a file into IFWI region defined by
+
| style="background:red" | Unknown
IFWI_FMAP_NAME.
+
| AMD AMDK8
 +
| SIS SIS966
 +
| ITE™ IT8716F
 +
| ?
 +
| Socket AM2
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.gigabyte.com/products/product-page.aspx?pid=2287#ov GIGABYTE]
| IFWI_FMAP_NAME || soc/intel/apollolake || string || Name of FMAP region to pull IFWI into ||  
+
| [[Board:gigabyte/m57sli|GA-M57SLI-S4]]
Name of FMAP region to write IFWI.
+
| style="background:#FFff00" | [[#gigabyte/m57sli|2017-04-17T16:31:52Z]]
 +
| AMD AMDK8
 +
| NVIDIA MCP55
 +
| ITE™ IT8716F
 +
| ?
 +
| Socket AM2
 +
| ?
 +
| ?
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| [[Gigabyte m57sli Vendor Cooperation Score|3]]
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.gigabyte.us/products/product-page.aspx?pid=3447#sp GIGABYTE]
| IFWI_FILE_NAME || soc/intel/apollolake || string || Path of file to write to IFWI region ||  
+
| [[Board:gigabyte/ma785gm|GA-MA785GM-US2H]]
Name of file to store in the IFWI region.
+
| style="background:red" | Unknown
 +
| AMD Family 10h
 +
| AMD RS780
 +
AMD SB700
 +
| ITE™ IT8718F
 +
| AMD Athlon™ 64 / FX / X2
 +
| Socket AM3
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
|
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.gigabyte.com/products/product-page.aspx?pid=3156#ov GIGABYTE]
| NHLT_DMIC_1CH_16B || soc/intel/apollolake || bool || ||  
+
| [[Board:gigabyte/ma785gmt|GA-MA785GMT-UD2H]]
Include DSP firmware settings for 1 channel 16B DMIC array.
+
| style="background:#FFff00" | [[#gigabyte/ma785gmt|2015-07-02T05:20:16Z]]
 +
| AMD Family 10h
 +
| AMD RS780
 +
AMD SB700
 +
| ITE™ IT8718F
 +
| AMD Athlon™ 64 / FX / X2
 +
| Socket AM3
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
|
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.gigabyte.com/products/product-page.aspx?pid=2995#ov GIGABYTE]
| NHLT_DMIC_2CH_16B || soc/intel/apollolake || bool || ||  
+
| [[Board:gigabyte/ma78gm|GA-MA78GM-US2H]]
Include DSP firmware settings for 2 channel 16B DMIC array.
+
| style="background:red" | Unknown
 +
| AMD Family 10h
 +
| AMD RS780
 +
AMD SB700
 +
| ITE™ IT8718F
 +
| AMD Athlon™ 64 / X2 / FX, Sempron™
 +
| Socket AM2+
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
|
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NHLT_DMIC_4CH_16B || soc/intel/apollolake || bool || ||  
+
| Google
Include DSP firmware settings for 4 channel 16B DMIC array.
+
( Google )
 +
| [[Board:google/fizz|Fizz Kabylake Reference Board]]
 +
| style="background:red" | Unknown
 +
|  
 +
|  
 +
|
 +
|
 +
|
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.intel.com/p/en_US/support/highlights/dsktpboards/d510mo Intel]
| NHLT_MAX98357 || soc/intel/apollolake || bool || ||  
+
| [[Board:intel/d510mo|D510MO]]
Include DSP firmware settings for headset codec.
+
| style="background:#0Dff00" | [[#intel/d510mo|2018-05-06T06:18:48Z]]
 +
| Intel® PINEVIEW
 +
| Intel® I82801GX
 +
| Winbond™ W83627THG
 +
| INTEL_SOCKET_FCBGA559
 +
| INTEL_SOCKET_FCBGA559
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.intel.com/support/motherboards/desktop/d945gclf/sb/CS-029163.htm?wapkw=d945gclf+overview Intel]
| NHLT_DA7219 || soc/intel/apollolake || bool || ||  
+
| [[Board:intel/d945gclf|D945GCLF]]
Include DSP firmware settings for headset codec.
+
| style="background:#E7ff00" | [[#intel/d945gclf|2017-09-30T01:24:47Z]]
 +
| Intel® I945
 +
Intel® SUBTYPE I945GC
 +
| Intel® I82801GX
 +
| SMSC® LPC47M15X
 +
| Intel® Atom™ 230
 +
| Socket 441
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Intel
| NHLT_RT5682 || soc/intel/apollolake || bool || ||  
+
| [[Board:intel/dcp847ske|Intel NUC DCP847SKE]]
Include DSP firmware settings for headset codec.
+
| style="background:red" | Unknown
 +
| Intel® SANDYBRIDGE
 +
| Intel® C216
 +
| Nuvoton  NCT6776
 +
| Intel® 2nd Gen (Sandybridge) Core i3/i5/i7
 +
| Socket RPGA989
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [https://ark.intel.com/products/41036/Intel-Desktop-Board-DG43GT Intel]
| NHLT_RT5682 || soc/intel/apollolake || bool || Cache-as-ram implementation ||  
+
| [[Board:intel/dg43gt|DG43GT]]
This option allows you to select how cache-as-ram (CAR) is set up.
+
| style="background:#EDff00" | [[#intel/dg43gt|2017-09-23T22:29:35Z]]
 +
| Intel® X4X
 +
| Intel® I82801JX
 +
| Winbond™ W83627DHG
 +
| Intel® Core 2, Pentium 4/D
 +
| Socket LGA775
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| CAR_NEM || soc/intel/apollolake || bool || Non-evict mode ||  
+
| [http://www.jetway.com.tw/jw/motherboard_view.asp?productid=567&proname=PA78VM5 Jetway]
Traditionally, CAR is set up by using Non-Evict mode. This method
+
| [[Board:jetway/pa78vm5|PA78VM5 (Fam10)]]
does not allow CAR and cache to co-exist, because cache fills are
+
| style="background:red" | Unknown
block in NEM mode.
+
| AMD Family 10h
 +
| AMD RS780
 +
AMD SB700
 +
| FINTEK F71863FG
 +
| AMD Athlon™ 64 / X2 / FX, Sempron™
 +
| Socket AM2+
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://no.msi.com/product/mb/K8N-Neo3.html MSI]
| CAR_CQOS || soc/intel/apollolake || bool || Cache Quality of Service ||  
+
| [[Board:msi/ms7135|MS-7135 (K8N Neo3)]]
Cache Quality of Service allows more fine-grained control of cache
+
| style="background:#4Dff00" | [[#msi/ms7135|2018-03-02T15:21:54Z]]
usage. As result, it is possible to set up portion of L2 cache for
+
| AMD AMDK8
CAR and use remainder for actual caching.
+
| NVIDIA CK804
 +
| Winbond™ W83627THG
 +
| AMD Sempron™ / Athlon™ 64 / Turion™ 64
 +
| Socket 754
 +
| PLCC
 +
| LPC
 +
| variable
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://no.msi.com/product/mb/K9N-Neo--PCB-1-0-.html MSI]
| USE_APOLLOLAKE_FSP_CAR || soc/intel/apollolake || bool || Use FSP CAR ||  
+
| [[Board:msi/ms7260|MS-7260 (K9N Neo)]]
Use FSP APIs to initialize &amp; tear down the Cache-As-Ram.
+
| style="background:red" | Unknown
 +
| AMD AMDK8
 +
| NVIDIA MCP55
 +
| Winbond™ W83627EHG
 +
| ?
 +
| Socket AM2
 +
| PLCC
 +
| ?
 +
| style="background:lime" | Y
 +
| style="background:yellow" | ...<sup>6</sup>
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [https://www.msi.com/Motherboard/FM2-A75MA-E35.html MSI]
| APL_SKIP_SET_POWER_LIMITS || soc/intel/apollolake || bool || ||  
+
| [[Board:msi/ms7721|MS-7721]]
Some Apollo Lake mainboards do not need the Running Average Power
+
| style="background:#27ff00" | [[#msi/ms7721|2018-04-09T12:06:51Z]]
Limits (RAPL) algorithm for a constant power management.
+
| AMD Family 15h TN (AGESA)
Set this config option to skip the RAPL configuration.
+
| AMD AGESA HUDSON
 +
| FINTEK F71869AD
 +
| AMD Family 15h TN (AGESA)
 +
| ?
 +
| SOIC8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| MSI
| SOC_ESPI || soc/intel/apollolake || bool || ||  
+
| [[Board:msi/ms9652_fam10|MS-9652]]
Use eSPI bus instead of LPC
+
| style="background:red" | Unknown
 +
| AMD Family 10h
 +
| NVIDIA MCP55
 +
| Winbond™ W83627EHG
 +
| AMD Opteron™
 +
| Socket F 1207
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_BAYTRAIL || soc/intel/baytrail || bool || ||  
+
| [http://docs.oracle.com/cd/E19127-01/ultra40.ws/820-0123-13/intro.html Sun Microsystems]
Bay Trail M/D part support.
+
| [[Board:sunw/ultra40|Ultra 40]]
 +
| style="background:red" | Unknown
 +
| AMD AMDK8
 +
| NVIDIA CK804
 +
| SMSC® LPC47B397
 +
SMSC® LPC47M10X
 +
| AMD Opteron™
 +
| Socket 940
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HAVE_MRC || soc/intel/baytrail || bool || Add a Memory Reference Code binary ||  
+
| [http://docs.oracle.com/cd/E19127-01/ultra40.ws/820-0123-13/intro.html Sun Microsystems]
Select this option to add a blob containing
+
| [[Board:sunw/ultra40m2|Ultra 40 M2]]
memory reference code.
+
| style="background:red" | Unknown
Note: Without this binary coreboot will not work
+
| AMD AMDK8
 +
| NVIDIA MCP55
 +
| SMSC® DME1737
 +
| AMD Opteron™
 +
| Socket F
 +
| PLCC
 +
| LPC
 +
| style="background:lime" | Y
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.win-ent.com/network-computing/network-systems/desktop-platforms/440-pl-60640.html Win Enterprises]
| MRC_FILE || soc/intel/baytrail || string || Intel memory refeference code path and filename ||  
+
| [[Board:winent/pl6064|PL60640]]
The path and filename of the file to use as System Agent
+
| style="background:red" | Unknown
binary. Note that this points to the sandybridge binary file
+
| AMD LX
which is will not work, but it serves its purpose to do builds.
+
| AMD CS5536
 +
| Winbond™ W83627HF
 +
| AMD Geode™ LX
 +
|
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#6699ff"
|- bgcolor="#eeeeee"
+
| colspan="13" | <h4>Embedded / PC/104 / Half-size boards</h4>
| DCACHE_RAM_SIZE || soc/intel/baytrail || hex ||  ||
 
The size of the cache-as-ram region required during bootblock
 
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
 
must add up to a power of 2.
 
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.aaeonusa.com/products/details/?item_id=1043 Aaeon]
| DCACHE_RAM_MRC_VAR_SIZE || soc/intel/baytrail || hex || ||  
+
| [[Board:aaeon/pfm-540i_revb|PFM-540I Rev.B]]
The amount of cache-as-ram region required by the reference code.
+
| style="background:red" | Unknown
 +
| AMD LX
 +
| AMD CS5536
 +
| SMSC® SMSC®SUPERIO
 +
| AMD Geode™ LX
 +
|
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| RESET_ON_INVALID_RAMSTAGE_CACHE || soc/intel/baytrail || bool || Reset the system on S3 wake when ramstage cache invalid. ||  
+
| [http://www.adlinktech.com/PD/web/PD_detail.php?pid=1277 ADLINK]
The baytrail romstage code caches the loaded ramstage program
+
| [[Board:adlink/CM2-GF|CoreModule2-GF]]
in SMM space. On S3 wake the romstage will copy over a fresh
+
| style="background:#FFff00" | [[#lippert/frontrunner-af|2017-09-01T05:15:05Z]]
ramstage that was cached in the SMM space. This option determines
+
| AMD Family 14h (AGESA)
the action to take when the ramstage cache is invalid. If selected
+
| AMD CIMX SB800
the system will reset otherwise the ramstage will be reloaded from
+
| SMSC® SMSC®SUPERIO
cbfs.
+
| AMD Family 14h (AGESA)
 +
| ?
 +
| SOIC8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_BUILTIN_COM1 || soc/intel/baytrail || bool || Enable builtin COM1 Serial Port ||  
+
| [http://www.adlinktech.com/PD/web/PD_detail.php?pid=1132 ADLINK]
The PMC has a legacy COM1 serial port. Choose this option to
+
| [[Board:adlink/cExpress-GFR|cExpress-GFR]]
configure the pads and enable it. This serial port can be used for
+
| style="background:red" | Unknown
the debug console.
+
| AMD Family 14h (AGESA)
 +
| AMD CIMX SB800
 +
| Winbond™ W83627DHG
 +
| AMD Family 14h (AGESA)
 +
| ?
 +
| SOIC8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.amd.com/Documents/40631a_epic_rdk_pb.pdf AMD]
| HAVE_REFCODE_BLOB || soc/intel/baytrail || bool || An external reference code blob should be put into cbfs. ||  
+
| [[Board:amd/samba|Samba]]
The reference code blob will be placed into cbfs.
+
| style="background:red" | Unknown
 +
| AMD LX
 +
| AMD CS5536
 +
| ITE™ IT8712F
 +
| AMD Geode™ LX
 +
|
 +
| SOIC8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| REFCODE_BLOB_FILE || soc/intel/baytrail || string || Path and filename to reference code blob. ||  
+
| [http://www.digitallogic.ch/english/products/datasheets/ms_pc104_detail.asp?id=MSM800SEV DIGITAL-LOGIC]
The path and filename to the file to be added to cbfs.
+
| [[Board:digitallogic/msm800sev|MSM800SEV]]
 +
| style="background:red" | Unknown
 +
| AMD LX
 +
| AMD CS5536
 +
| Winbond™ W83627HF
 +
| AMD Geode™ LX
 +
|
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| GizmoSphere
| SOC_INTEL_BRASWELL || soc/intel/braswell || bool || ||  
+
| [[Board:gizmosphere/gizmo|Gizmo]]
Braswell M/D part support.
+
| style="background:#FFff00" | [[#gizmosphere/gizmo|2017-08-25T20:33:26Z]]
 +
| AMD Family 14h (AGESA)
 +
| AMD CIMX SB800
 +
|  
 +
| AMD Family 14h (AGESA)
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DCACHE_RAM_SIZE || soc/intel/braswell || hex || ||  
+
| Google
The size of the cache-as-ram region required during bootblock
+
( Google )
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
+
| [[Board:google/beltino|Beltino Haswell Chromebox Reference device]]
must add up to a power of 2.
+
| style="background:red" | Unknown
 +
| Intel® HASWELL
 +
| Intel® LYNXPOINT
 +
| ITE™ IT8772F
 +
| Intel® 4th Gen (Haswell) Core i3/i5/i7
 +
| ?
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://web.archive.org/web/20111208234719/http://ieiworld.com/product_groups/industrial/content.aspx?gid=00001000010000000001&cid=09050652111816087425&id=09069696333360342284 IEI]
| RESET_ON_INVALID_RAMSTAGE_CACHE || soc/intel/braswell || bool || Reset the system on S3 wake when ramstage cache invalid. ||  
+
| [[Board:iei/kino-780am2-fam10|Kino-780AM2]]
The haswell romstage code caches the loaded ramstage program
+
| style="background:red" | Unknown
in SMM space. On S3 wake the romstage will copy over a fresh
+
| AMD Family 10h
ramstage that was cached in the SMM space. This option determines
+
| AMD RS780
the action to take when the ramstage cache is invalid. If selected
+
AMD SB700
the system will reset otherwise the ramstage will be reloaded from
+
| FINTEK F71859
cbfs.
+
| AMD Athlon™ 64 / X2 / FX, Sempron™
 +
| Socket AM2+
 +
| ?
 +
| SPI
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.ieiworld.com/en/product_IPC.asp?model=PCISA-LX IEI]
| ENABLE_BUILTIN_COM1 || soc/intel/braswell || bool || Enable builtin COM1 Serial Port ||  
+
| [[Board:iei/pcisa-lx-800-r10|PCISA-LX-800-R10]]
The PMC has a legacy COM1 serial port. Choose this option to
+
| style="background:red" | Unknown
configure the pads and enable it. This serial port can be used for
+
| AMD LX
the debug console.
+
| AMD CS5536
 +
| Winbond™ W83627HF
 +
| AMD Geode™ LX
 +
|
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.ieiworld.com/product_groups/industrial/content.aspx?gid=00001000010000000001&cid=09050665574743104681&id=08142307826854456110#.UCLx8cLlgao IEI]
| SOC_INTEL_BROADWELL || soc/intel/broadwell || bool || ||  
+
| [[Board:iei/pm-lx-800-r11|PM-LX-800-R11]]
Intel Broadwell and Haswell ULT support.
+
| style="background:red" | Unknown
 +
| AMD LX
 +
| AMD CS5536
 +
| Winbond™ W83627EHG
 +
| AMD Geode™ LX
 +
|
 +
| PLCC
 +
| LPC
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.ieiworld.com/product_groups/industrial/content.aspx?gid=00001000010000000001&cid=09050665574743104681&id=09034367569861123956#.UI2CfiExUao IEI]
| DCACHE_RAM_SIZE || soc/intel/broadwell || hex || ||  
+
| [[Board:iei/pm-lx2-800-r10|PM-LX2-800-R10]]
The size of the cache-as-ram region required during bootblock
+
| style="background:red" | Unknown
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
+
| AMD LX
must add up to a power of 2.
+
| AMD CS5536
 +
| SMSC® SMSC®SUPERIO
 +
| AMD Geode™ LX
 +
|
 +
| PLCC
 +
| LPC
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DCACHE_RAM_MRC_VAR_SIZE || soc/intel/broadwell || hex || ||  
+
| [http://www.adlinktech.com/PD/web/PD_detail.php?pid=1277 LiPPERT]
The amount of cache-as-ram region required by the reference code.
+
| [[Board:lippert/frontrunner-af|FrontRunner-AF]]
 +
| style="background:#FFff00" | [[#lippert/frontrunner-af|2017-09-01T05:15:05Z]]
 +
| AMD Family 14h (AGESA)
 +
| AMD CIMX SB800
 +
| SMSC® SMSC®SUPERIO
 +
| AMD Family 14h (AGESA)
 +
| ?
 +
| SOIC8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| HAVE_MRC || soc/intel/broadwell || bool || Add a Memory Reference Code binary ||  
+
| [http://www.adlinktech.com/PD/web/PD_detail.php?pid=1154 LiPPERT]
Select this option to add a Memory Reference Code binary to
+
| [[Board:lippert/hurricane-lx|Hurricane-LX]]
the resulting coreboot image.
+
| style="background:red" | Unknown
 +
| AMD LX
 +
| AMD CS5536
 +
| ITE™ IT8712F
 +
| AMD Geode™ LX
 +
|
 +
| SOIC8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
Note: Without this binary coreboot will not work
 
 
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| MRC_FILE || soc/intel/broadwell || string || Intel Memory Reference Code path and filename ||  
+
| [http://www.adlinktech.com/PD/web/PD_detail.php?pid=1128 LiPPERT]
The filename of the file to use as Memory Reference Code binary.
+
| [[Board:lippert/literunner-lx|Cool LiteRunner-LX]]
 +
| style="background:red" | Unknown
 +
| AMD LX
 +
| AMD CS5536
 +
| ITE™ IT8712F
 +
| AMD Geode™ LX
 +
| —
 +
| SOIC8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PRE_GRAPHICS_DELAY || soc/intel/broadwell || int || Graphics initialization delay in ms ||  
+
| [http://www.adlinktech.com/PD/web/PD_detail.php?pid=1147 LiPPERT]
On some systems, coreboot boots so fast that connected monitors
+
| [[Board:lippert/roadrunner-lx|Cool RoadRunner-LX]]
(mostly TVs) won't be able to wake up fast enough to talk to the
+
| style="background:red" | Unknown
VBIOS. On those systems we need to wait for a bit before executing
+
| AMD LX
the VBIOS.
+
| AMD CS5536
 +
| ITE™ IT8712F
 +
| AMD Geode™ LX
 +
|
 +
| PLCC
 +
| FWH
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| RESET_ON_INVALID_RAMSTAGE_CACHE || soc/intel/broadwell || bool || Reset the system on S3 wake when ramstage cache invalid. ||  
+
| [http://www.adlinktech.com/PD/web/PD_detail.php?pid=1148 LiPPERT]
The romstage code caches the loaded ramstage program in SMM space.
+
| [[Board:lippert/spacerunner-lx|Cool SpaceRunner-LX]]
On S3 wake the romstage will copy over a fresh ramstage that was
+
| style="background:red" | Unknown
cached in the SMM space. This option determines the action to take
+
| AMD LX
when the ramstage cache is invalid. If selected the system will
+
| AMD CS5536
reset otherwise the ramstage will be reloaded from cbfs.
+
| ITE™ IT8712F
 +
| AMD Geode™ LX
 +
|
 +
| SOIC8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SERIRQ_CONTINUOUS_MODE || soc/intel/broadwell || bool || ||  
+
| [http://www.adlinktech.com/PD/web/PD_detail.php?pid=1132 LiPPERT]
If you set this option to y, the serial IRQ machine will be
+
| [[Board:lippert/toucan-af|Toucan-AF]]
operated in continuous mode.
+
| style="background:red" | Unknown
 +
| AMD Family 14h (AGESA)
 +
| AMD CIMX SB800
 +
| Winbond™ W83627DHG
 +
| AMD Family 14h (AGESA)
 +
| ?
 +
| SOIC8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://pcengines.ch/alix1c.htm PC Engines]
| HAVE_REFCODE_BLOB || soc/intel/broadwell || bool || An external reference code blob should be put into cbfs. ||  
+
| [[Board:pcengines/alix1c|alix1c]]
The reference code blob will be placed into cbfs.
+
| style="background:#7Cff00" | [[#pcengines/alix1c|2018-01-15T00:44:43Z]]
 +
| AMD LX
 +
| AMD CS5536
 +
| Winbond™ W83627HF
 +
| AMD Geode™ LX
 +
|
 +
| PLCC-32
 +
| LPC
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| style="background:lime"| [[PC Engines ALIX.1C Vendor Cooperation Score|4]]
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://pcengines.ch/alix2c3.htm PC Engines]
| REFCODE_BLOB_FILE || soc/intel/broadwell || string || Path and filename to reference code blob. ||  
+
| [[Board:pcengines/alix2c|alix2c]]
The path and filename to the file to be added to cbfs.
+
| style="background:red" | Unknown
 +
|
 +
|  
 +
|  
 +
|  
 +
|  
 +
| TSOP-32
 +
| LPC
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://pcengines.ch/alix2d0.htm PC Engines]
| SOC_INTEL_CANNONLAKE || soc/intel/cannonlake || bool || ||  
+
| [[Board:pcengines/alix2d|alix2d]]
Intel Cannonlake support
+
| style="background:#7Cff00" | [[#pcengines/alix2d|2018-01-15T00:44:43Z]]
 +
| AMD LX
 +
| AMD CS5536
 +
|  
 +
| AMD Geode™ LX
 +
|
 +
| TSOP-32
 +
| LPC
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://pcengines.ch/alix6f2.htm PC Engines]
| UART_FOR_CONSOLE || soc/intel/cannonlake || int || Index for LPSS UART port to use for console ||  
+
| [[Board:pcengines/alix6|alix6f]]
Index for LPSS UART port to use for console:
+
| style="background:red" | Unknown
0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
+
|
 +
|  
 +
|  
 +
|  
 +
|  
 +
| TSOP-32
 +
| LPC
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.pcengines.ch/apu1d4.htm PC Engines]
| DCACHE_RAM_SIZE || soc/intel/cannonlake || int ||  ||  
+
| [[Board:pcengines/apu1|apu1]]
The size of the cache-as-ram region required during bootblock
+
| style="background:#13ff00" | [[#pcengines/apu1|2018-04-29T18:26:46Z]]
and/or romstage.
+
| AMD Family 14h (AGESA)
 +
| AMD CIMX SB800
 +
| Nuvoton NCT5104D
 +
| AMD Family 14h (AGESA)
 +
| ?
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.pcengines.ch/apu2c2.htm PC Engines]
| DCACHE_BSP_STACK_SIZE || soc/intel/cannonlake || hex ||  ||  
+
| [[Board:pcengines/apu2|apu2 apu3 apu4 apu5]]
The amount of anticipated stack usage in CAR by bootblock and
+
| style="background:#7Cff00" | [[#pcengines/apu2|2018-01-15T00:44:43Z]]
other stages.
+
| AMD 00730F01 (PI)
 +
| AMD PI AVALON
 +
| Nuvoton NCT5104D
 +
| AMD_PI_00730F01
 +
| AMD_PI_00730F01
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NHLT_DMIC_1CH_16B || soc/intel/cannonlake || bool || ||  
+
| SAMSUNG
Include DSP firmware settings for 1 channel 16B DMIC array.
+
( Samsung )
 +
| [[Board:samsung/stumpy|Series 3 Chromebox]]
 +
| style="background:#FFff00" | [[#samsung/stumpy|2014-01-21T04:39:46Z]]
 +
| Intel® SANDYBRIDGE
 +
| Intel® BD82X6X
 +
| ITE™ IT8772F
 +
SMSC® LPC47N207
 +
| Intel® 2nd Gen (Sandybridge) Core i3/i5/i7
 +
| Socket RPGA989
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Siemens
| NHLT_DMIC_2CH_16B || soc/intel/cannonlake || bool ||  ||  
+
| [[Board:siemens/sitemp_g1p1|MB SITEMP-G1 (U1P0/U1P1)]]
Include DSP firmware settings for 2 channel 16B DMIC array.
+
| style="background:red" | Unknown
 +
| AMD AMDK8
 +
| AMD RS690
 +
AMD SB600
 +
| ITE™ IT8712F
 +
| AMD Turion™ / X2 Sempron™
 +
| Socket S1G1
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NHLT_DMIC_4CH_16B || soc/intel/cannonlake || bool ||  ||  
+
| [http://www.technexion.com/index.php/embedded-mainboards/amd/tim-5690 Technexion]
Include DSP firmware settings for 4 channel 16B DMIC array.
+
| [[Board:technexion/tim5690|TIM-5690]]
 +
| style="background:red" | Unknown
 +
| AMD AMDK8
 +
| AMD RS690
 +
AMD SB600
 +
| ITE™ IT8712F
 +
| AMD Turion™ / X2 Sempron™
 +
| Socket S1G1
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NHLT_MAX98357 || soc/intel/cannonlake || bool ||  ||  
+
| [http://www.technexion.com/index.php/tim-8690 Technexion]
Include DSP firmware settings for headset codec.
+
| [[Board:technexion/tim8690|TIM-8690]]
 +
| style="background:red" | Unknown
 +
| AMD AMDK8
 +
| AMD RS690
 +
AMD SB600
 +
| ITE™ IT8712F
 +
| AMD Turion™ / X2 Sempron™
 +
| Socket S1G1
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.traverse.com.au/geos11-adsl2-x86-router-appliance Traverse Technologies]
| NHLT_MAX98373 || soc/intel/cannonlake || bool || ||  
+
| [[Board:traverse/geos|Geos]]
Include DSP firmware settings for headset codec.
+
| style="background:red" | Unknown
 +
| AMD LX
 +
| AMD CS5536
 +
|  
 +
| AMD Geode™ LX
 +
|
 +
| PLCC
 +
| ?
 +
| style="background:lime" | Y
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NHLT_DA7219 || soc/intel/cannonlake || bool || ||  
+
| Win Enterprises
Include DSP firmware settings for headset codec.
+
| [[Board:winent/mb6047|MB6047]]
 +
| style="background:red" | Unknown
 +
| AMD AMDK8
 +
| NVIDIA CK804
 +
| Winbond™ W83627THG
 +
| AMD Opteron™
 +
| Socket 940
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#6699ff"
|- bgcolor="#eeeeee"
+
| colspan="13" | <h4>Mini-ITX / Micro-ITX / Nano-ITX</h4>
| PCR_BASE_ADDRESS || soc/intel/cannonlake || hex ||  ||
 
This option allows you to select MMIO Base Address of sideband bus.
 
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.advansus.com.tw/products/247/A785E-I Advansus]
| STACK_SIZE || soc/intel/cannonlake || hex || Cache-as-ram implementation ||  
+
| [[Board:advansus/a785e-i|A785E-I]]
This option allows you to select how cache-as-ram (CAR) is set up.
+
| style="background:red" | Unknown
 +
| AMD Family 10h
 +
| AMD RS780
 +
AMD SB800
 +
| Winbond™ W83627HF #COM1, COM2
 +
#FINTEK F81216AD #COM3, COM4
 +
| AMD Turion™ II Neo/Athlon™ II Neo
 +
| ASB2 (BGA812)
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| USE_CANNONLAKE_CAR_NEM_ENHANCED || soc/intel/cannonlake || bool || Enhanced Non-evict mode ||  
+
| AMD
A current limitation of NEM (Non-Evict mode) is that code and data
+
| [[Board:amd/f2950|F2950]]
sizes are derived from the requirement to not write out any modified
+
| style="background:red" | Unknown
cache line. With NEM, if there is no physical memory behind the
+
| AMD LX
cached area, the modified data will be lost and NEM results will be
+
| AMD CS5536
inconsistent. ENHANCED NEM guarantees that modified data is always
+
| Winbond™ W83627HF
kept in cache while clean data is replaced.
+
| AMD Geode™ LX
 +
| —
 +
| PLCC
 +
| LPC
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.asrock.com/mb/overview.asp?Model=E350M1 ASROCK]
| USE_CANNONLAKE_FSP_CAR || soc/intel/cannonlake || bool || Use FSP CAR ||  
+
| [[Board:asrock/e350m1|E350M1]]
Use FSP APIs to initialize and tear down the Cache-As-Ram.
+
| style="background:#01ff00" | [[#asrock/e350m1|2018-05-17T14:26:53Z]]
 +
| AMD Family 14h (AGESA)
 +
| AMD CIMX SB800
 +
| Nuvoton  NCT5572D
 +
| AMD Family 14h (AGESA)
 +
| ?
 +
| DIP8
 +
| SPI
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.asrock.com/ipc/overview.asp?Model=IMB-A180 ASROCK]
| SOC_INTEL_DENVERTON_NS || soc/intel/denverton_ns || bool || ||  
+
| [[Board:asrock/imb-a180|IMB-A180]]
Intel Denverton-NS SoC support
+
| style="background:#FFff00" | [[#asrock/imb-a180|2017-08-24T10:37:14Z]]
 +
| AMD Family 16h KB (AGESA)
 +
| AMD AGESA YANGTZE
 +
| Winbond™ W83627UHG
 +
| AMD Family 16h KB (AGESA)
 +
| ?
 +
| DIP8
 +
| SPI
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_T_ADDR || soc/intel/denverton_ns || hex || Intel FSP-T (temp ram init) binary location ||  
+
| [https://www.asus.com/us/Motherboards/AM1IA/ ASUS]
The memory location of the Intel FSP-T binary for this platform.
+
| [[Board:asus/am1i-a|AM1I-A]]
 +
| style="background:#0Fff00" | [[#asus/am1i-a|2018-05-03T17:31:02Z]]
 +
| AMD Family 16h KB (AGESA)
 +
| AMD AGESA YANGTZE
 +
| ITE™ IT8623E
 +
| AMD Family 16h KB (AGESA)
 +
| ?
 +
| DIP8
 +
| SPI
 +
| style="background:lime" | Y
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.biostar.com.tw/app/en/mb/introduction.php?S_ID=694 Biostar]
| FSP_M_ADDR || soc/intel/denverton_ns || hex || Intel FSP-M (memory init) binary location ||  
+
| [[Board:biostar/am1ml|AM1ML]]
The memory location of the Intel FSP-M binary for this platform.
+
| style="background:#FFff00" | [[#biostar/am1ml|2015-04-13T11:03:01Z]]
 +
| AMD Family 16h KB (AGESA)
 +
| AMD AGESA YANGTZE
 +
| ITE™ IT8728F
 +
| AMD Family 16h KB (AGESA)
 +
| ?
 +
| DIP8
 +
| SPI
 +
| style="background:lime" | Y
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_S_ADDR || soc/intel/denverton_ns || hex || Intel FSP-S (silicon init) binary location ||  
+
| HP
The memory location of the Intel FSP-S binary for this platform.
+
| [[Board:hp/abm|ABM]]
 +
| style="background:red" | Unknown
 +
| AMD Family 16h KB (AGESA)
 +
| AMD AGESA YANGTZE
 +
| Nuvoton  NCT5104D
 +
| AMD Family 16h KB (AGESA)
 +
| ?
 +
| SOIC8
 +
| SPI
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.ibase.com.tw/mb899.htm iBase]
| PCR_BASE_ADDRESS || soc/intel/denverton_ns || hex || ||  
+
| [[Board:ibase/mb899|MB899]]
This option allows you to select MMIO Base Address of sideband bus.
+
| style="background:red" | Unknown
 +
| Intel® I945
 +
Intel® SUBTYPE I945GM
 +
| Intel® I82801GX
 +
| Winbond™ W83627EHG
 +
| Intel® Core™ 2 Duo Mobile, Core™ Duo/Solo, Celeron® M
 +
| Socket mPGA478
 +
| PLCC
 +
| FWH
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| IQAT_MEMORY_REGION_SIZE || soc/intel/denverton_ns || hex || ||  
+
| [http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=279&proname=J7F2 Jetway]
Do not change this value
+
| [[Board:jetway/j7f2|J7f2]]
 +
| style="background:red" | Unknown
 +
| VIA CN700
 +
| VIA VT8237R
 +
| FINTEK F71805F
 +
| VIA C7™
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NON_LEGACY_UART_MODE || soc/intel/denverton_ns || bool || Non Legacy Mode ||  
+
| [http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=279&proname=J7F4K1G2E Jetway]
Disable legacy UART mode
+
| [[Board:jetway/j7f4k1g2e|J7f4K1G2E]]
 +
| style="background:red" | Unknown
 +
| VIA CN700
 +
| VIA VT8237R
 +
| FINTEK F71805F
 +
| VIA C7™
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
 
|- bgcolor="#eeeeee"
 
| LEGACY_UART_MODE || soc/intel/denverton_ns || bool || Legacy Mode ||
 
Enable legacy UART mode
 
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DENVERTON_NS_CAR_NEM_ENHANCED || soc/intel/denverton_ns || bool || Enhanced Non-evict mode ||  
+
| [http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=279&proname=J7F4K1G5D Jetway]
A current limitation of NEM (Non-Evict mode) is that code and data sizes
+
| [[Board:jetway/j7f4k1g5d|J7f4K1G5D]]
are derived from the requirement to not write out any modified cache line.
+
| style="background:red" | Unknown
With NEM, if there is no physical memory behind the cached area,
+
| VIA CN700
the modified data will be lost and NEM results will be inconsistent.
+
| VIA VT8237R
ENHANCED NEM guarantees that modified data is always
+
| FINTEK F71805F
kept in cache while clean data is replaced.
+
| VIA C7™
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_FSP_BAYTRAIL || soc/intel/fsp_baytrail || bool || ||  
+
| [http://www.jetway.com.tw/jw/ipcboard_view.asp?productid=822&proname=NF81-T56N-LF Jetway]
Bay Trail I part support using the Intel FSP.
+
| [[Board:jetway/nf81-t56n-lf|NF81-T56N-LF]]
 +
| style="background:#FFff00" | [[#jetway/nf81-t56n-lf|2014-03-29T03:40:24Z]]
 +
| AMD Family 14h (AGESA)
 +
| AMD CIMX SB800
 +
| FINTEK F71869AD
 +
| AMD Family 14h (AGESA)
 +
| ?
 +
| SOIC8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.kontron.de/products/boards-and-mezzanines/embedded-motherboards/mini-itx-motherboards/986lcd-m-mitx.html Kontron]
| SMM_TSEG_SIZE || soc/intel/fsp_baytrail || hex || ||  
+
| [[Board:kontron/986lcd-m|986LCD-M/mITX]]
This is set by the FSP
+
| style="background:red" | Unknown
 +
| Intel® I945
 +
Intel® SUBTYPE I945GM
 +
| Intel® I82801GX
 +
| Winbond™ W83627THG
 +
| Intel® Core™ 2 Duo Mobile, Core™ Duo/Solo, Celeron® M
 +
| Socket mPGA478
 +
| PLCC
 +
| FWH
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://emea.kontron.com/products/boards+and+mezzanines/embedded+motherboards/miniitx+motherboards/kt690mitx+bga.html?searchtermresultpage=kt690%2Fmitx Kontron]
| VGA_BIOS_ID || soc/intel/fsp_baytrail || string ||  ||  
+
| [[Board:kontron/kt690|KT690/mITX]]
This is the default PCI ID for the Bay Trail graphics
+
| style="background:red" | Unknown
devices.  This string names the vbios ROM in cbfs.
+
| AMD AMDK8
 +
| AMD RS690
 +
AMD SB600
 +
| Winbond™ W83627DHG
 +
| AMD Turion™ / X2 Sempron™
 +
| Socket S1G1
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Kontron
| ENABLE_BUILTIN_COM1 || soc/intel/fsp_baytrail || bool || Enable built-in legacy Serial Port ||  
+
| [[Board:kontron/ktqm77|KTQM77/mITX]]
The Baytrail SOC has one legacy serial port. Choose this option to
+
| style="background:red" | Unknown
configure the pads and enable it. This serial port can be used for
+
| Intel® IVYBRIDGE
the debug console.
+
| Intel® C216
 +
| Winbond™ W83627DHG
 +
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
 +
| Socket RPGA989
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_FILE || soc/intel/fsp_baytrail/fsp || string || ||  
+
| Sapphire
The path and filename of the Intel FSP binary for this platform.
+
| [[Board:sapphire/pureplatinumh61|Pure Platinum H61]]
 +
| style="background:#FFff00" | [[#sapphire/pureplatinumh61|2017-08-26T16:30:37Z]]
 +
| Intel® IVYBRIDGE
 +
| Intel® BD82X6X
 +
| FINTEK F71808A
 +
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
 +
| Socket LGA1155
 +
| SOIC-8
 +
| SPI
 +
| style="background:lime" | Y
 +
| style="background:red" | N
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.via.com.tw/en/products/mainboards/motherboards.jsp?motherboard_id=400 VIA]
| FSP_LOC || soc/intel/fsp_baytrail/fsp || hex || ||  
+
| [[Board:via/epia-cn|EPIA-CN10000EG / EPIA-CN13000G]]
The location in CBFS that the FSP is located. This must match the
+
| style="background:red" | Unknown
value that is set in the FSP binary.  If the FSP needs to be moved,
+
| VIA CN700
rebase the FSP with Intel's BCT (tool).
+
| VIA VT8237R
 +
| VIA VT1211
 +
| VIA C7™
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
The Bay Trail FSP is built with a preferred base address of
+
|- bgcolor="#dddddd"
0xFFFC0000.
+
| [http://www.viaembedded.com/en/products/boards/670/1/EPIA-M700_%28EOL%29.html VIA]
 +
| [[Board:via/epia-m700|EPIA-M700]]
 +
| style="background:red" | Unknown
 +
| VIA VX800
 +
|
 +
| Winbond™ W83697HF
 +
| VIA C7™
 +
| ?
 +
| SOIC8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
 +
| [http://www.viaembedded.com/en/products/boards/1290/1/EPIA-M850.html VIA]
 +
| [[Board:via/epia-m850|EPIA-M850]]
 +
| style="background:red" | Unknown
 +
| VIA VX900
 +
|
 +
| FINTEK F81865F
 +
| VIA Nano™
 +
| ?
 +
| SOIC8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.idot.com.tw/en/products/mb-pc2500e/ VIA]
| SOC_INTEL_FSP_BROADWELL_DE || soc/intel/fsp_broadwell_de || bool || ||  
+
| [[Board:via/pc2500e|pc2500e]]
Broadwell-DE support using the Intel FSP.
+
| style="background:red" | Unknown
 +
| VIA CN700
 +
| VIA VT8237R
 +
| ITE™ IT8716F
 +
| VIA C7™
 +
| ?
 +
| PLCC
 +
| ?
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| INTEGRATED_UART || soc/intel/fsp_broadwell_de || bool || Integrated UART ports ||  
+
| WinNET
Use Broadwell-DE Integrated UART ports @3F8h and 2F8h.
+
( WinNET )
 +
| [[Board:winnet/g170|G170]]
 +
| style="background:red" | Unknown
 +
| VIA CN700
 +
| VIA VT8237R
 +
| Winbond™ W83697HF
 +
| VIA C7™
 +
| ?
 +
| PLCC
 +
| Parallel
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#6699ff"
|- bgcolor="#eeeeee"
+
| colspan="13" | <h4>Set-top-boxes / Thin clients</h4>
| SERIRQ_CONTINUOUS_MODE || soc/intel/fsp_broadwell_de || bool ||  ||
 
If you set this option to y, the serial IRQ machine will be
 
operated in continuous mode.
 
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.artecgroup.com/thincan/index.php?option=com_content&task=blogcategory&id=15&Itemid=34 Artec Group]
| FSP_FILE || soc/intel/fsp_broadwell_de/fsp || string || ||  
+
| [[Board:artecgroup/dbe61|DBE61]]
The path and filename of the Intel FSP binary for this platform.
+
| style="background:red" | Unknown
 +
| AMD LX
 +
| AMD CS5536
 +
|
 +
| AMD Geode™ LX
 +
| —
 +
| ?
 +
| ?
 +
| ?
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_LOC || soc/intel/fsp_broadwell_de/fsp || hex || ||  
+
| Bachmann electronic
The location in CBFS that the FSP is located. This must match the
+
| [[Board:bachmann/ot200|OT200]]
value that is set in the FSP binary.  If the FSP needs to be moved,
+
| style="background:red" | Unknown
rebase the FSP with Intel's BCT (tool).
+
| AMD LX
 +
| AMD CS5536
 +
|  
 +
| AMD Geode™ LX
 +
|
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
The Broadwell-DE FSP is built with a preferred base address of
+
|- bgcolor="#dddddd"
0xffeb0000.
+
| BCOM
 +
| [[Board:bcom/winnetp680|WinNET P680]]
 +
| style="background:red" | Unknown
 +
| VIA CN700
 +
| VIA VT8237R
 +
| Winbond™ W83697HF
 +
| VIA C7™
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DCACHE_RAM_BASE || soc/intel/fsp_broadwell_de/fsp || hex || ||  
+
| Google
This address needs to match the setup performed inside FSP.
+
( Google )
On Broadwell-DE the FSP allocates temporary RAM starting at 0xfe100000.
+
| [[Board:google/jecht|Jecht Broadwell Chromebox]]
 +
| style="background:red" | Unknown
 +
|
 +
|
 +
| ITE™ IT8772F
 +
|  
 +
|  
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DCACHE_RAM_SIZE || soc/intel/fsp_broadwell_de/fsp || hex || ||  
+
| Google
The DCACHE is shared between FSP itself and the rest of the coreboot
+
( Google )
stages. A size of 0x8000 works fine while providing enough space for
+
| [[Board:google/storm|Storm Qualcomm IPQ806X board]]
features like VBOOT in verstage. Further increase to a power of two
+
| style="background:red" | Unknown
aligned value leads to errors in FSP.
+
|  
 +
|  
 +
|  
 +
|
 +
|
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.linutop.com Linutop]
| FSP_MEMORY_DOWN || soc/intel/fsp_broadwell_de/fsp || bool || Enable Memory Down ||  
+
| [[Board:linutop/linutop1|Linutop-1]]
Load SPD data from ROM instead of trying to read from SMBus.
+
| style="background:red" | Unknown
 +
| AMD LX
 +
| AMD CS5536
 +
|  
 +
| AMD Geode™ LX
 +
|
 +
| ?
 +
| ?
 +
| ?
 +
| style="background:lime" | Y
 +
| —
  
If the platform has DIMM sockets, say N. If memory is down, say Y and
+
|- bgcolor="#6699ff"
supply the appropriate SPD data for each Channel/DIMM.
+
| colspan="13" | <h4>Devel/Eval Boards</h4>
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| ADI
| FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT || soc/intel/fsp_broadwell_de/fsp || bool || Channel 0, DIMM 0 Present ||  
+
| [[Board:adi/rcc-dff|ADI RCC-DFF]]
Select Y if Channel 0, DIMM 0 is present.
+
| style="background:red" | Unknown
 +
| Intel® RANGELEY (FSP)
 +
| Intel® FSP RANGELEY
 +
|  
 +
| INTEL_FSP_RANGELEY
 +
| Socket RPGA989
 +
| ?
 +
| SPI
 +
| ?
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_MEMORY_DOWN_CH0DIMM0_SPD_FILE || soc/intel/fsp_broadwell_de/fsp || string || Channel 0, DIMM 0 SPD File ||  
+
| AMD
Path to the file which contains the SPD data for Channel 0, DIMM 0.
+
| [[Board:amd/bettong|FP4]]
 +
| style="background:red" | Unknown
 +
| AMD 00660F01 (PI)
 +
| AMD PI KERN
 +
|
 +
| AMD_PI_00660F01
 +
| AMD_PI_00660F01
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT || soc/intel/fsp_broadwell_de/fsp || bool || Channel 0, DIMM 1 Present ||  
+
| AMD
Select Y if Channel 0, DIMM 1 is present.
+
| [[Board:amd/bimini_fam10|Bimini (Fam10)]]
 +
| style="background:red" | Unknown
 +
| AMD Family 10h
 +
| AMD RS780
 +
AMD SB800
 +
| ITE™ IT8718F
 +
| AMD Turion™ II Neo/Athlon™ II Neo
 +
| ASB2 (BGA812)
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
|
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_MEMORY_DOWN_CH0DIMM1_SPD_FILE || soc/intel/fsp_broadwell_de/fsp || string || Channel 0, DIMM 1 SPD File ||  
+
| [http://wwwd.amd.com/amd/devsite.nsf/platforms/db-ft3-lc.htm AMD]
Path to the file which contains the SPD data for Channel 0, DIMM 1.
+
| [[Board:amd/db-ft3b-lc|DB-FT3b-LC]]
 +
| style="background:red" | Unknown
 +
| AMD 00730F01 (PI)
 +
| AMD PI AVALON
 +
|
 +
| AMD_PI_00730F01
 +
| AMD_PI_00730F01
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT || soc/intel/fsp_broadwell_de/fsp || bool || Channel 1, DIMM 0 Present ||  
+
| [http://www.amd.com/us/products/embedded/develop-and-design/Pages/development-boards-lx.aspx AMD]
Select Y if Channel 1, DIMM 0 is present.
+
| [[Board:amd/db800|DB800 (Salsa)]]
 +
| style="background:red" | Unknown
 +
| AMD LX
 +
| AMD CS5536
 +
| Winbond™ W83627HF
 +
| AMD Geode™ LX
 +
| —
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_MEMORY_DOWN_CH1DIMM0_SPD_FILE || soc/intel/fsp_broadwell_de/fsp || string || Channel 1, DIMM 0 SPD File ||  
+
| [http://support.amd.com/us/ChipsetMotherboard_TechDocs/42655A_S1DBM680T_PB.pdf AMD]
Path to the file which contains the SPD data for Channel 1, DIMM 0.
+
| [[Board:amd/dbm690t|dbM690T (Herring)]]
 +
| style="background:red" | Unknown
 +
| AMD AMDK8
 +
| AMD RS690
 +
AMD SB600
 +
| ITE™ IT8712F
 +
| AMD Turion™ / X2  Sempron™
 +
| Socket S1G1
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT || soc/intel/fsp_broadwell_de/fsp || bool || Channel 1, DIMM 1 Present ||  
+
| AMD
Select Y if Channel 1, DIMM 1 is present.
+
| [[Board:amd/gardenia|GARDENIA]]
 +
| style="background:#FFff00" | [[#amd/gardenia|2017-01-06T16:30:58Z]]
 +
|
 +
|
 +
|
 +
|  
 +
|  
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_MEMORY_DOWN_CH1DIMM1_SPD_FILE || soc/intel/fsp_broadwell_de/fsp || string || Channel 1, DIMM 1 SPD File ||  
+
| AMD
Path to the file which contains the SPD data for Channel 1, DIMM 1.
+
| [[Board:amd/inagua|Inagua]]
 +
| style="background:red" | Unknown
 +
| AMD Family 14h (AGESA)
 +
| AMD CIMX SB800
 +
| SMSC® KBC1100
 +
| AMD Family 14h (AGESA)
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_HYPERTHREADING || soc/intel/fsp_broadwell_de/fsp || bool || Enable Hyper-Threading ||  
+
| AMD
Enable Intel(r) Hyper-Threading Technology for the Broadwell-DE SoC.
+
| [[Board:amd/lamar|DB-FP3 (Lamar)]]
 +
| style="background:#FFff00" | [[#amd/lamar|2015-04-30T02:12:19Z]]
 +
| AMD 00630F01 (PI)
 +
| AMD PI BOLTON
 +
| FINTEK F81216H
 +
| AMD_PI_00630F01
 +
| AMD_PI_00630F01
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_EHCI1_ENABLE || soc/intel/fsp_broadwell_de/fsp || bool || EHCI1 Enable ||  
+
| AMD
Enable EHCI controller 1
+
| [[Board:amd/mahogany|DB780E (Mahogany)]]
 +
| style="background:red" | Unknown
 +
| AMD AMDK8
 +
| AMD RS780
 +
AMD SB700
 +
| ITE™ IT8718F
 +
| ?
 +
| Socket AM2
 +
| ?
 +
| SPI
 +
| ?
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_EHCI2_ENABLE || soc/intel/fsp_broadwell_de/fsp || bool || EHCI2 Enable ||  
+
| AMD
Enable EHCI controller 2
+
| [[Board:amd/mahogany_fam10|Mahogany (Fam10)]]
 +
| style="background:red" | Unknown
 +
| AMD Family 10h
 +
| AMD RS780
 +
AMD SB700
 +
| ITE™ IT8718F
 +
| AMD Athlon™ 64 / X2 / FX, Sempron™
 +
| Socket AM2+
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
|
  
||
 
 
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_QUARK || soc/intel/quark || bool || ||  
+
| AMD
Intel Quark support
+
| [[Board:amd/norwich|Norwich]]
 +
| style="background:red" | Unknown
 +
| AMD LX
 +
| AMD CS5536
 +
|  
 +
| AMD Geode™ LX
 +
|
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_BUILTIN_HSUART0 || soc/intel/quark || bool || Enable built-in HSUART0 ||  
+
| AMD
The Quark SoC has two HSUART. Choose this option to configure the pads
+
| [[Board:amd/olivehill|DB-FT3]]
and enable HSUART0, which can be used for the debug console.
+
| style="background:#FFff00" | [[#amd/olivehill|2014-10-08T13:44:17Z]]
 +
| AMD Family 16h KB (AGESA)
 +
| AMD AGESA YANGTZE
 +
|  
 +
| AMD Family 16h KB (AGESA)
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_BUILTIN_HSUART1 || soc/intel/quark || bool || Enable built-in HSUART1 ||  
+
| [http://wwwd.amd.com/amd/devsite.nsf/platforms/DB-FT3.htm AMD]
The Quark SoC has two HSUART. Choose this option to configure the pads
+
| [[Board:amd/olivehillplus|DB-FT3b (Olive Hill+)]]
and enable HSUART1, which can be used for the debug console.
+
| style="background:#FFff00" | [[#amd/olivehillplus|2014-09-24T05:58:25Z]]
 +
| AMD 00730F01 (PI)
 +
| AMD PI AVALON
 +
|  
 +
| AMD_PI_00730F01
 +
| AMD_PI_00730F01
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| TTYS0_BASE || soc/intel/quark || hex || HSUART Base Address ||  
+
| AMD
Memory mapped MMIO of HSUART.
+
| [[Board:amd/parmer|DB-FS1r2 (Parmer)]]
 +
| style="background:red" | Unknown
 +
| AMD Family 15h TN (AGESA)
 +
| AMD AGESA HUDSON
 +
|
 +
| AMD Family 15h TN (AGESA)
 +
| ?
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_DEBUG_LED || soc/intel/quark || bool || ||  
+
| AMD
Enable the use of the SD LED for early debugging before serial output
+
| [[Board:amd/persimmon|DBFT1-00-EVAL-KT (Persimmon)]]
is available.  Setting this LED indicates that control has reached the
+
| style="background:#FFff00" | [[#amd/persimmon|2017-08-29T11:37:06Z]]
desired check point.
+
| AMD Family 14h (AGESA)
 +
| AMD CIMX SB800
 +
| FINTEK F81865F
 +
| AMD Family 14h (AGESA)
 +
| ?
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_DEBUG_LED_ESRAM || soc/intel/quark || bool || SD LED indicates ESRAM initialized ||  
+
| AMD
Indicate that ESRAM has been successfully initialized.  If the SD LED
+
| [[Board:amd/pistachio|Pistachio]]
does not light then the ESRAM initialization needs to be debugged.
+
| style="background:red" | Unknown
 +
| AMD AMDK8
 +
| AMD RS690
 +
AMD SB600
 +
|  
 +
| ?
 +
| Socket AM2
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_DEBUG_LED_FINDFSP || soc/intel/quark || bool || SD LED indicates fsp.bin file was found ||  
+
| AMD
Indicate that fsp.bin was found.  If the SD LED does not light then
+
| [[Board:amd/south_station|South Station]]
the code between ESRAM initialization through find_fsp needs to
+
| style="background:red" | Unknown
debugged.  Start by verifying that the correct fsp.bin is in the
+
| AMD Family 14h (AGESA)
image.
+
| AMD CIMX SB800
 +
| FINTEK F81865F
 +
| AMD Family 14h (AGESA)
 +
| ?
 +
| SOIC8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY || soc/intel/quark || bool || SD LED indicates bootblock.c successfully entered ||  
+
| AMD
Indicate that bootblock_c_entry was entered.  If the SD LED does not
+
| [[Board:amd/thatcher|DB-FP2 (Thatcher)]]
light then debug the code between ESRAM and bootblock_c_entry.  For
+
| style="background:#FFff00" | [[#amd/thatcher|2016-02-04T18:30:40Z]]
FSP 1.1, use ENABLE_DEBUG_LED_FINDFSP to split this code.
+
| AMD Family 15h TN (AGESA)
 +
| AMD AGESA HUDSON
 +
| SMSC® LPC47N217
 +
| AMD Family 15h TN (AGESA)
 +
| ?
 +
| SOIC-8
 +
| SPI
 +
| style="background:red" | N
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY || soc/intel/quark || bool || SD LED indicates bootblock_soc_early_init successfully entered ||  
+
| AMD
Indicate that bootblock_soc_early_init was entered.  If the SD LED
+
| [[Board:amd/tilapia_fam10|Tilapia (Fam10)]]
does not light then debug the code in bootblock_main_with_timestamp.
+
| style="background:red" | Unknown
 +
| AMD Family 10h
 +
| AMD RS780
 +
AMD SB700
 +
| ITE™ IT8718F
 +
| AMD Athlon™ 64 / FX / X2
 +
| Socket AM3
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
|
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_DEBUG_LED_SOC_EARLY_INIT_EXIT || soc/intel/quark || bool || SD LED indicates bootblock_soc_early_init successfully exited ||  
+
| AMD
Indicate that bootblock_soc_early_init exited.  If the SD LED does not
+
| [[Board:amd/torpedo|Torpedo]]
light then debug the scripts in bootblock_soc_early_init.
+
| style="background:red" | Unknown
 +
| AMD Family 12h (AGESA)
 +
| AMD CIMX SB900
 +
| SMSC® KBC1100
 +
| AMD Family 12h (AGESA)
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ENABLE_DEBUG_LED_SOC_INIT_ENTRY || soc/intel/quark || bool || SD LED indicates bootblock_soc_init successfully entered ||  
+
| AMD
Indicate that bootblock_soc_init was entered.  If the SD LED does not
+
| [[Board:amd/union_station|Union Station]]
light then debug the code in bootblock_mainboard_early_init and
+
| style="background:red" | Unknown
console_init.  If the SD LED does light but there is no serial then
+
| AMD Family 14h (AGESA)
debug the serial port configuration and initialization.
+
| AMD CIMX SB800
 +
|  
 +
| AMD Family 14h (AGESA)
 +
| ?
 +
| SOIC8
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| BAP
| DISPLAY_ESRAM_LAYOUT || soc/intel/quark || bool || Display ESRAM layout ||  
+
| [[Board:bap/ode_e20XX|ODE_E20XX]]
Select this option to display coreboot's use of ESRAM.
+
| style="background:red" | Unknown
 +
| AMD Family 16h KB (AGESA)
 +
| AMD AGESA YANGTZE
 +
| FINTEK F81866D
 +
| AMD Family 16h KB (AGESA)
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://www.unibap.com/advanced-heterogeneous-computing-modules/ BAP]
| CBFS_SIZE || soc/intel/quark || hex || ||  
+
| [[Board:bap/ode_e21XX|ODE_e21xx]]
Specify the size of the coreboot file system in the read-only (recovery)
+
| style="background:red" | Unknown
portion of the flash part.  On Quark systems the firmware image stores
+
| AMD 00730F01 (PI)
more than just coreboot, including:
+
| AMD PI AVALON
- The chipset microcode (RMU) binary file located at 0xFFF00000
+
| FINTEK F81866D
- Intel Trusted Execution Engine firmware
+
| AMD_PI_00730F01
 +
| AMD_PI_00730F01
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| ADD_FSP_RAW_BIN || soc/intel/quark || bool || Add the Intel FSP binary to the flash image without relocation ||  
+
| Biostar
Select this option to add an Intel FSP binary to
+
| [[Board:biostar/a68n_5200|A68N5200]]
the resulting coreboot image.
+
| style="background:red" | Unknown
 +
| AMD Family 16h KB (AGESA)
 +
| AMD AGESA YANGTZE
 +
| ITE™ IT8728F
 +
| AMD Family 16h KB (AGESA)
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
Note: Without this binary, coreboot builds relying on the FSP
+
|- bgcolor="#dddddd"
will not boot
+
| Broadcom
 +
| [[Board:broadcom/blast|Blast]]
 +
| style="background:red" | Unknown
 +
| AMD AMDK8
 +
| BROADCOM BCM5780
 +
BROADCOM BCM5785
 +
| NSC PC87417
 +
| AMD Opteron™
 +
| Socket 940
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| FSP_FILE || soc/intel/quark || string || Intel FSP binary path and filename ||  
+
| GizmoSphere
The path and filename of the Intel FSP binary for this platform.
+
| [[Board:gizmosphere/gizmo2|Gizmo2]]
 +
| style="background:red" | Unknown
 +
| AMD Family 16h KB (AGESA)
 +
| AMD AGESA YANGTZE
 +
|  
 +
| AMD Family 16h KB (AGESA)
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Google
| FSP_LOC || soc/intel/quark || hex || ||  
+
( Google )
The location in CBFS that the FSP is located. This must match the
+
| [[Board:google/cheza|Cheza Qualcomm SDM845 reference board]]
value that is set in the FSP binary.  If the FSP needs to be moved,
+
| style="background:red" | Unknown
rebase the FSP with Intel's BCT (tool).
+
|  
 +
|  
 +
|  
 +
|
 +
|
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Google
| FSP_ESRAM_LOC || soc/intel/quark || hex || ||  
+
( Google )
The location in ESRAM where a copy of the FSP binary is placed.
+
| [[Board:google/foster|Foster Nvidia Tegra210 reference board]]
 +
| style="background:red" | Unknown
 +
|  
 +
|  
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Google
| RELOCATE_FSP_INTO_DRAM || soc/intel/quark || bool || Relocate FSP into DRAM ||  
+
( Google )
Relocate the FSP binary into DRAM before the call to SiliconInit.
+
| [[Board:google/gale|Gale]]
 +
| style="background:red" | Unknown
 +
|  
 +
|  
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Google
| ADD_RMU_FILE || soc/intel/quark || bool || Should the RMU binary be added to the flash image? ||  
+
( Google )
The RMU file is required to get the chip out of reset.
+
| [[Board:google/gru|Gru Rockchip RK3399 reference board]]
 +
| style="background:red" | Unknown
 +
|  
 +
|
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Google
| RMU_FILE || soc/intel/quark || string || ||  
+
| [[Board:google/kahlee|KAHLEE]]
The path and filename of the Intel Quark RMU binary.
+
| style="background:red" | Unknown
 +
|  
 +
|  
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Google
| RMU_LOC || soc/intel/quark || hex || ||  
+
( Google )
The location in CBFS that the RMU is located. It must match the
+
| [[Board:google/purin|Purin Broadcom Cygnus reference board]]
strap-determined base address.
+
| style="background:red" | Unknown
 +
|  
 +
|  
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Google
| STORAGE_TEST || soc/intel/quark || bool || Test SD/MMC/eMMC card or device access ||  
+
( Google )
Read block 0 from each parition of the storage device.  User
+
| [[Board:google/urara|Urara Imgtec Pistachio reference board]]
must also enable one or both of COMMONLIB_STORAGE_SD or
+
| style="background:red" | Unknown
COMMONLIB_STORAGE_MMC.
+
|  
 +
|  
 +
|  
 +
| IMGTEC_PISTACHIO
 +
| IMGTEC_PISTACHIO
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| I2C_DEBUG || soc/intel/quark || bool || Enable I2C debugging ||  
+
| Intel
Display the I2C segments and controller errors
+
( Intel )
 +
| [[Board:intel/apollolake_rvp|Apollolake RVP Reference Board]]
 +
| style="background:red" | Unknown
 +
|  
 +
|  
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_SKYLAKE || soc/intel/skylake || bool || ||  
+
| Intel
Intel Skylake support
+
| [[Board:intel/baskingridge|BASKING RIDGE]]
 +
| style="background:red" | Unknown
 +
| Intel® HASWELL
 +
| Intel® LYNXPOINT
 +
|  
 +
| Intel® 4th Gen (Haswell) Core i3/i5/i7
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
|
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_KABYLAKE || soc/intel/skylake || bool || ||  
+
| Intel
Intel Kabylake support
+
| [[Board:intel/bayleybay_fsp|Bayley Bay]]
 +
| style="background:#FFff00" | [[#intel/bayleybay_fsp|2014-06-25T23:32:28Z]]
 +
|
 +
|
 +
|
 +
|
 +
|  
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DCACHE_RAM_SIZE || soc/intel/skylake || hex || ||  
+
| Intel
The size of the cache-as-ram region required during bootblock
+
| [[Board:intel/camelbackmountain_fsp|Camelback Mountain]]
and/or romstage.
+
| style="background:#0Eff00" | [[#intel/camelbackmountain_fsp|2018-05-04T10:30:24Z]]
 +
|  
 +
|  
 +
|  
 +
|  
 +
|
 +
| ?
 +
| SPI
 +
| yes
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| DCACHE_BSP_STACK_SIZE || soc/intel/skylake || hex || ||  
+
| Intel
The amount of anticipated stack usage in CAR by bootblock and
+
( Intel )
other stages.
+
| [[Board:intel/cannonlake_rvp|Cannonlake rvp]]
 +
| style="background:red" | Unknown
 +
|
 +
|  
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| EXCLUDE_NATIVE_SD_INTERFACE || soc/intel/skylake || bool || ||  
+
| Intel
If you set this option to n, will not use native SD controller.
+
| [[Board:intel/cougar_canyon2|Cougar Canyon 2]]
 +
| style="background:red" | Unknown
 +
| Intel® IVYBRIDGE (FSP)
 +
| Intel® FSP BD82X6X
 +
| SMSC® SIO1007
 +
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
 +
| Socket RPGA989
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
|
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| PCR_BASE_ADDRESS || soc/intel/skylake || hex || ||  
+
| Intel
This option allows you to select MMIO Base Address of sideband bus.
+
| [[Board:intel/emeraldlake2|EMERALD LAKE 2]]
 +
| style="background:red" | Unknown
 +
| Intel® IVYBRIDGE
 +
| Intel® C216
 +
| SMSC® SIO1007
 +
| Intel® 3rd Gen (Ivybridge) Core i3/i5/i7
 +
| Socket RPGA989
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
|
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SERIRQ_CONTINUOUS_MODE || soc/intel/skylake || bool || ||  
+
| Intel
If you set this option to y, the serial IRQ machine will be
+
( Intel )
operated in continuous mode.
+
| [[Board:intel/harcuvar|Harcuvar]]
 +
| style="background:red" | Unknown
 +
|
 +
|  
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| UART_FOR_CONSOLE || soc/intel/skylake || int || Index for LPSS UART port to use for console ||  
+
| Intel
Index for LPSS UART port to use for console:
+
( Intel )
0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
+
| [[Board:intel/kblrvp|Kabylake RVP Reference Board]]
 +
| style="background:red" | Unknown
 +
|  
 +
|  
 +
|  
 +
|
 +
|
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SKYLAKE_SOC_PCH_H || soc/intel/skylake || bool || ||  
+
| Intel
Choose this option if you have a PCH-H chipset.
+
( Intel )
 +
| [[Board:intel/leafhill|Leafhill Reference Board]]
 +
| style="background:red" | Unknown
 +
|  
 +
|  
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| SPI
 +
| style="background:lime" | Y
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NHLT_DMIC_2CH || soc/intel/skylake || bool || ||  
+
| Intel
Include DSP firmware settings for 2 channel DMIC array.
+
| [[Board:intel/littleplains|Little Plains]]
 +
| style="background:red" | Unknown
 +
| Intel® RANGELEY (FSP)
 +
| Intel® FSP RANGELEY
 +
|  
 +
| INTEL_FSP_RANGELEY
 +
| Socket RPGA989
 +
| ?
 +
| SPI
 +
| ?
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NHLT_DMIC_4CH || soc/intel/skylake || bool || ||  
+
| Intel
Include DSP firmware settings for 4 channel DMIC array.
+
( Intel )
 +
| [[Board:intel/minnow3|MinnowBoard 3]]
 +
| style="background:red" | Unknown
 +
|  
 +
|  
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NHLT_NAU88L25 || soc/intel/skylake || bool || ||  
+
| Intel
Include DSP firmware settings for nau88l25 headset codec.
+
| [[Board:intel/mohonpeak|Mohon Peak CRB]]
 +
| style="background:red" | Unknown
 +
| Intel® RANGELEY (FSP)
 +
| Intel® FSP RANGELEY
 +
|  
 +
| INTEL_FSP_RANGELEY
 +
| Socket RPGA989
 +
| ?
 +
| SPI
 +
| ?
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NHLT_MAX98357 || soc/intel/skylake || bool ||  ||  
+
| Intel
Include DSP firmware settings for max98357 amplifier.
+
( Intel )
 +
| [[Board:intel/saddlebrook|Saddle Brook Skylake Reference Board]]
 +
| style="background:red" | Unknown
 +
|  
 +
|
 +
| Nuvoton  NCT6776
 +
Nuvoton NCT6776 COM A
 +
|  
 +
|
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NHLT_MAX98373 || soc/intel/skylake || bool || ||  
+
| Intel
Include DSP firmware settings for max98373 amplifier.
+
| [[Board:intel/stargo2|Stargo2]]
 +
| style="background:red" | Unknown
 +
| Intel® IVYBRIDGE (FSP)
 +
| Intel® FSP I89XX
 +
| Winbond™ WPCD376I
 +
INTEL I8900
 +
| INTEL_SOCKET_BGA1284
 +
| INTEL_SOCKET_BGA1284
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NHLT_SSM4567 || soc/intel/skylake || bool || ||  
+
| Intel
Include DSP firmware settings for ssm4567 smart amplifier.
+
| [[Board:intel/wtm2|WHITETIP MOUNTAIN 2]]
 +
| style="background:red" | Unknown
 +
|
 +
|
 +
|  
 +
|
 +
|  
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [https://www.google.com/search?q=Tutorial+for+the+debug+preview+of+lowRISC&oq=Tutorial+for+the+debug+preview+of+lowRISC&btnI lowrisc]
| NHLT_RT5514 || soc/intel/skylake || bool || ||  
+
| [[Board:lowrisc/nexys4ddr|lowrisc nexys4ddr]]
Include DSP firmware settings for rt5514 DSP.
+
| style="background:red" | Unknown
 +
|  
 +
|  
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NHLT_RT5663 || soc/intel/skylake || bool || ||  
+
| NVIDIA
Include DSP firmware settings for rt5663 headset codec.
+
| [[Board:nvidia/l1_2pvv|l1_2pvv]]
 +
| style="background:red" | Unknown
 +
| AMD AMDK8
 +
| NVIDIA MCP55
 +
| Winbond™ W83627EHG
 +
| AMD Opteron™
 +
| Socket F
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [https://www.crowdsupply.com/sifive/hifive-unleashed SiFive]
| NHLT_MAX98927 || soc/intel/skylake || bool || ||  
+
| [[Board:sifive/hifive-unleashed|HiFive Unleashed]]
Include DSP firmware settings for max98927 amplifier.
+
| style="background:red" | Unknown
 +
|  
 +
|  
 +
|  
 +
|  
 +
|  
 +
| SOIC-16
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| NHLT_DA7219 || soc/intel/skylake || bool || ||  
+
| VIA
Include DSP firmware settings for DA7219 headset codec.
+
| [[Board:via/vt8454c|VT8454c]]
 +
| style="background:red" | Unknown
 +
| VIA CX700
 +
|  
 +
| VIA VT1211
 +
| VIA C7™
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#6699ff"
|- bgcolor="#eeeeee"
+
| colspan="13" | <h4>Single-Board computer</h4>
| NHLT_DA7219 || soc/intel/skylake || bool || Cache-as-ram implementation ||
 
This option allows you to select how cache-as-ram (CAR) is set up.
 
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| CompuLab
| USE_SKYLAKE_CAR_NEM_ENHANCED || soc/intel/skylake || bool || Enhanced Non-evict mode ||  
+
( CompuLab )
A current limitation of NEM (Non-Evict mode) is that code and data
+
| [[Board:compulab/intense_pc|Intense-PC]]
sizes are derived from the requirement to not write out any modified
+
| style="background:red" | Unknown
cache line. With NEM, if there is no physical memory behind the
+
| Intel® IVYBRIDGE
cached area, the modified data will be lost and NEM results will be
+
| Intel® C216
inconsistent. ENHANCED NEM guarantees that modified data is always
+
| SMSC® SIO1007
kept in cache while clean data is replaced.
+
| INTEL_SOCKET_FCBGA1023
 +
| INTEL_SOCKET_FCBGA1023
 +
| SOIC-16
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:red" | N
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| USE_SKYLAKE_FSP_CAR || soc/intel/skylake || bool || Use FSP CAR ||  
+
| Cubietech
Use FSP APIs to initialize and tear down the Cache-As-Ram.
+
| [[Board:cubietech/cubieboard|Cubieboard A10]]
 +
| style="background:red" | Unknown
 +
|
 +
|  
 +
|  
 +
| Allwinner A10
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| ELMEX
| SKIP_FSP_CAR || soc/intel/skylake || bool || Skip cache as RAM setup in FSP ||  
+
| [[Board:elmex/pcm205400|PCM205400]]
Skip Cache as RAM setup in FSP.
+
| style="background:red" | Unknown
 +
| AMD Family 14h (AGESA)
 +
| AMD CIMX SB800
 +
| FINTEK F81865F
 +
| AMD Family 14h (AGESA)
 +
| ?
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| ELMEX
| NO_FADT_8042 || soc/intel/skylake || bool || ||  
+
| [[Board:elmex/pcm205401|PCM205401]]
Choose this option if you want to disable 8042 Keyboard
+
| style="background:red" | Unknown
 +
|
 +
|  
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON || soc/intel/common || bool || ||  
+
| electronic system design
common code for Intel SOCs
+
| [[Board:esd/atom15|esd atom15]]
 +
| style="background:red" | Unknown
 +
|
 +
|
 +
|
 +
|
 +
|  
 +
| ?
 +
| SPI
 +
| ?
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Intel
| || || (comment) || || Intel SoC Common Code ||
+
| [[Board:intel/galileo|Galileo]]
|- bgcolor="#eeeeee"
+
| style="background:red" | Unknown
| SOC_INTEL_COMMON_BLOCK || soc/intel/common/block || bool || ||  
+
|  
SoC driver for intel common IP code
+
|  
 +
|  
 +
|
 +
|  
 +
| ?
 +
| SPI
 +
| ?
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Intel
| || || (comment) || || Intel SoC Common IP Code ||
+
| [[Board:intel/minnowmax|Minnow Max]]
|- bgcolor="#eeeeee"
+
| style="background:#FFff00" | [[#intel/minnowmax|2017-09-06T06:53:39Z]]
| SOC_INTEL_COMMON_BLOCK_TIMER || soc/intel/common/block/timer || bool || ||  
+
|
Intel Processor common TIMER support
+
|  
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| SPI
 +
| ?
 +
| style="background:lime" | Y
 +
| —
  
||
 
||
 
 
|- bgcolor="#eeeeee"
 
|- bgcolor="#eeeeee"
| SOC_INTEL_COMMON_BLOCK_XDCI || soc/intel/common/block/xdci || bool || ||  
+
| TI
Intel Processor common XDCI support
+
| [[Board:ti/beaglebone|Beaglebone]]
 +
| style="background:red" | Unknown
 +
|
 +
|
 +
|  
 +
| TI AM335X
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#6699ff"
||
+
| colspan="13" | <h4>Emulation</h4>
|- bgcolor="#eeeeee"
 
| SOC_INTEL_COMMON_BLOCK_SCS || soc/intel/common/block/scs || bool ||  ||
 
Intel Processor common storage and communication subsystem support
 
  
||
+
|- bgcolor="#dddddd"
||
+
| [http://wiki.qemu.org/Main_Page Emulation]
|- bgcolor="#eeeeee"
+
| [[Board:emulation/qemu-armv7|QEMU armv7 (vexpress-a9)]]
| SOC_INTEL_COMMON_BLOCK_SATA || soc/intel/common/block/sata || bool || ||  
+
| style="background:red" | Unknown
Intel Processor common SATA support
+
|  
 +
|  
 +
|  
 +
| ARM Cortex A9
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://wiki.qemu.org/Main_Page Emulation]
| SOC_AHCI_PORT_IMPLEMENTED_INVERT || soc/intel/common/block/sata || bool || ||  
+
| [[Board:emulation/qemu-i440fx|QEMU x86 i440fx/piix4]]
SATA PCI configuration space offset 0x92 Port
+
| style="background:#FFff00" | [[#emulation/qemu-i440fx|2017-05-17T17:09:18Z]]
implement register bit 0-2 represents respective
+
|  
SATA port enable status as in 0 = Disable; 1 = Enable.
+
| Intel® I82371EB
If this option is selected then port enable status will be
+
|  
inverted as in 0 = Enable; 1 = Disable.
+
| QEMU x86
 +
|
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
||
+
| Emulation
|- bgcolor="#eeeeee"
+
| [[Board:emulation/qemu-power8|QEMU POWER8]]
| SOC_INTEL_COMMON_BLOCK_LPC || soc/intel/common/block/lpc || bool || ||  
+
| style="background:red" | Unknown
Use common LPC code for platform. Only soc specific code needs to
+
|  
be implemented as per requirement.
+
|  
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| [http://wiki.qemu.org/Main_Page Emulation]
| SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE || soc/intel/common/block/lpc || bool || ||  
+
| [[Board:emulation/qemu-q35|QEMU x86 q35/ich9]]
By default COMA range to LPC is enable. COMB range to LPC is optional
+
| style="background:#66ff00" | [[#emulation/qemu-q35|2018-02-06T06:14:30Z]]
and should select based on platform dedicated selection.
+
|  
 +
| Intel® I82801IX
 +
|  
 +
| QEMU x86
 +
|
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
||
+
| [https://github.com/riscv/riscv-qemu Emulation]
|- bgcolor="#eeeeee"
+
| [[Board:emulation/qemu-riscv|QEMU RISCV]]
| SOC_INTEL_COMMON_BLOCK_SPI || soc/intel/common/block/spi || bool || ||  
+
| style="background:red" | Unknown
Intel Processor common SPI support
+
|  
 +
|  
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#dddddd"
||
+
| [https://github.com/riscv/riscv-isa-sim Emulation]
|- bgcolor="#eeeeee"
+
| [[Board:emulation/spike-riscv|Spike RISCV]]
| SOC_INTEL_COMMON_BLOCK_P2SB || soc/intel/common/block/p2sb || bool || ||  
+
| style="background:red" | Unknown
Intel Processor common P2SB driver
+
|  
 +
|  
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| ?
 +
| ?
 +
| ?
 +
| —
  
||
+
|- bgcolor="#6699ff"
||
+
| colspan="13" | <h4>Miscellaneous</h4>
|- bgcolor="#eeeeee"
 
| SOC_INTEL_COMMON_BLOCK_SMM || soc/intel/common/block/smm || bool ||  ||
 
Intel Processor common SMM support
 
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Google
| SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP || soc/intel/common/block/smm || bool || ||  
+
( Google )
Intel Processor trap flag if it is supported
+
| [[Board:google/smaug|Smaug Nvidia Tegra210 tablet]]
 +
| style="background:red" | Unknown
 +
|  
 +
|  
 +
|  
 +
|
 +
|
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Google
| SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS || soc/intel/common/block/smm || int || ||  
+
( Google )
Time in milliseconds that SLP_SMI for S5 waits for before
+
| [[Board:google/veyron|Veyron Rockchip RK3288 boards]]
enabling sleep. This is required to avoid any race between
+
| style="background:red" | Unknown
SLP_SMI and PWRBTN SMI.
+
|  
 +
|  
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
||
+
| Google
|- bgcolor="#eeeeee"
+
( Google )
| SOC_INTEL_COMMON_BLOCK_SA || soc/intel/common/block/systemagent || bool || ||  
+
| [[Board:google/veyron_mickey|Veyron Mickey Rockchip RK3288 board]]
Intel Processor common System Agent support
+
| style="background:red" | Unknown
 +
|
 +
|
 +
|  
 +
|  
 +
|  
 +
| ?
 +
| SPI
 +
| style="background:red" | N
 +
| style="background:lime" | Y
 +
| —
  
||
+
|- bgcolor="#dddddd"
|- bgcolor="#eeeeee"
+
| Google
| SA_PCIEX_LENGTH || soc/intel/common/block/systemagent || hex || ||  
+
( Google )
This option allows you to select length of PCIEX region.
+
| [[Board:google/veyron_rialto|Veyron Rialto Rockchip RK3288 board]]
 +
| style="background:red" | Unknown
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|  
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|  
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|  
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|
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