Difference between revisions of "Talk:Board:asus/f2a85-m"

Revision as of 09:15, 8 December 2013

Linux complains about prefetchable memory regions: http://www.coreboot.org/pipermail/coreboot/2012-December/073133.html

[    0.648901] pci 0000:00:02.0: no compatible bridge window for [mem 0xb0000000-0xbfffffff 64bit pref]
[    0.658001] pci 0000:00:15.1: no compatible bridge window for [mem 0xc0000000-0xc00fffff 64bit pref]
[    0.667124] pci 0000:01:00.0: no compatible bridge window for [mem 0xb0000000-0xbfffffff 64bit pref]
[    0.676229] pci 0000:04:00.0: no compatible bridge window for [mem 0xc0004000-0xc0004fff 64bit pref]
[    0.685332] pci 0000:04:00.0: no compatible bridge window for [mem 0xc0000000-0xc0003fff 64bit pref]

That it mentions prefetchable memory is kind of minor: it's an address that requires 64-bit decoding, and it's an address that can be prefetched, but that's just the way the PCI device BAR is set. If the memory is prefetchable, it must also use 64-bit decoding. Prefetchable memory is the most efficient, so unless there are memory-mapped registers of a particular kind, it makes sense to always use 64-bit prefetchable memory. In fact, none of the regions in these error messages use more than 32 bits anyway.

0:00.0 1022:1410 Host Bridge
0:01.0 1002:9993 ATI Radeon HD 7480D
0:01.1 1002:9902 ATI Radeon HDMI Audio
0:02.0 1022:1412 PCI-PCI bridge PCIe root port to integrated graphics
   PCI-PCI bridge: bus 0 to bus 1
      1:00.0 1002:954f ATI Radeon HD 4300/4500
      1:00.1 1002:aa38 ATI Radeon HDMI Audio

0:10.0 1022:7812 USB 3.0 XHCI HCD (Hudson)
0:10.1 1022:7812 USB 3.0 XHCI HCD (Hudson)
0:11.0 1022:7801 SATA controller, AHCI mode (Hudson)
0:12.0 1022:7807 USB 1.0 OHCI HCD
0:12.2 1022:7808 USB 2.0 EHCI HCD
0:13.0 1022:7807 USB 1.0 OHCI HCD
0:13.2 1022:7808 USB 2.0 EHCI HCD
0:14.0 1022:780b SMBus (Hudson)
0:14.1 1022:780c IDE Controller, pata_atiixp http://openbenchmarking.org/linux/PCI/0101/1022:780c -- but hidden/disabled on this motherboard
0:14.2 1022:780d Azalia audio controller (Hudson)
0:14.3 1022:780e LPC Bridge (Hudson)
0:14.4 1022:780f PCI-PCI Bridge PCIe root port
   PCI-PCI bridge: bus 0 to bus 2

0:14.5 1022:7809 USB 1.0 OHCI HCD
0:14.7 1022:7806 SD card controller

0:15.0 1022:43a0 PCI-PCI Bridge
   PCI-PCI bridge: bus 0 to bus 3

0:15.1 1022:43a1 PCI-PCI Bridge PCIe root port
   PCI-PCI bridge: bus 0 to bus 4
      4:00.0 10ec:8168 RTL8168/8111 PCI-E Gigabit Ethernet

0:18.0 1022:1400
0:18.1 1022:1401
0:18.2 1022:1402
0:18.3 1022:1403
0:18.4 1022:1404
0:18.5 1022:1405

So that helps break down those error messages:

0:02.0: mem 0xb0000000-0xbfffffff 64bit pref This PCI device is just a PCI-PCI bridge, but the memory is routed through this to 1:00.0. Once the problem with 1:00.0 is fixed, the problem with 0:02.0 will be fixed.

It might be that because 1:00.0 is the on-chip VGA it is not correctly set up on the host bridge. Or maybe 0:02.0 needs to map the addresses.

0:15.1: mem 0xc0000000-0xc00fffff 64bit pref This PCI device is also a PCI-PCI bridge, so the problem is really at 4:00.0

There are two memory regions on the RTL8168/8111 card, and they need to be mapped.

I'm confident coreboot already has code to perform these mappings, so this might be only a correction in the devicetree file.