[coreboot-gerrit] New patch to review for coreboot: 864a181 AMD RS780, SR5650: PcieTrainPort: Fix typo *i*gnoring in comment

[Paul Menzel (paulepanter@users.sourceforge.net)]

Paul Menzel (paulepanter at users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3062

-gerrit

commit 864a1811caea4d68beb0d5a9876ed493fd2f8f81
Author: Paul Menzel <paulepanter at users.sourceforge.net>
Date:   Wed Apr 10 11:33:37 2013 +0200

    AMD RS780, SR5650: PcieTrainPort: Fix typo *i*gnoring in comment
    
    Reading the paste of code in a message to the mailing list [1],
    a typo was spotted and found in one more place.
    
        $ git grep egnoring
        src/southbridge/amd/rs780/cmn.c:                         * egnoring the reversal case
        src/southbridge/amd/sr5650/sr5650.c:                     * egnoring the reversal case
    
    These typos are there since when the code was committed and are
    now corrected.
    
    [1] http://www.coreboot.org/pipermail/coreboot/2013-April/075644.html
    
    Change-Id: I55c65f71e4834f209b60d678f0d44bc2f4217099
    Signed-off-by: Paul Menzel <paulepanter at users.sourceforge.net>
---
 src/southbridge/amd/rs780/cmn.c     | 2 +-
 src/southbridge/amd/sr5650/sr5650.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c
index 3c6d22d..cf09b9a 100644
--- a/src/southbridge/amd/rs780/cmn.c
+++ b/src/southbridge/amd/rs780/cmn.c
@@ -301,7 +301,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
 			/* 4 means 7:4 and 15:12
 			 * 3 means 7:2 and 15:10
 			 * 2 means 7:1 and 15:9
-			 * egnoring the reversal case
+			 * ignoring the reversal case
 			 */
 			lane_mask = (0xFF << (current_link_width - 2) * 2) & 0xFF;
 			reg = nbpcie_ind_read_index(nb_dev, 0x65 | gfx_gpp_sb_sel);
diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c
index 0bb246e..7fdecf1 100644
--- a/src/southbridge/amd/sr5650/sr5650.c
+++ b/src/southbridge/amd/sr5650/sr5650.c
@@ -202,7 +202,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
 			/* 4 means 7:4 and 15:12
 			 * 3 means 7:2 and 15:10
 			 * 2 means 7:1 and 15:9
-			 * egnoring the reversal case
+			 * ignoring the reversal case
 			 */
 			lane_mask = (0xFF << (current_link_width - 2) * 2) & 0xFF;
 			reg = nbpcie_ind_read_index(nb_dev, 0x65 | gpp_sb_sel);