[coreboot-gerrit] Patch merged into coreboot/master: 6cf5c8e AMD Fam16: Add secondary bus number to CRES method
gerrit at coreboot.org
gerrit at coreboot.org
Thu Aug 15 18:40:29 CEST 2013
the following patch was just integrated into master:
commit 6cf5c8ee655ab80d897b7a86bfc4dbde6fb462d5
Author: Mike Loptien <mike.loptien at se-eng.com>
Date: Thu Jul 18 10:16:31 2013 -0600
AMD Fam16: Add secondary bus number to CRES method
Adding the 'WordBusNumber' macro to the PCI0
CRES ResourceTemplate in the AMD FCH ACPI code.
This sets up the bus number for the PCI0 device
and the secondary bus number in the CRS method.
This change came in response to a 'dmesg' error
which states:
'[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS'
By adding the 'WordBusNumber' macro, ACPI can set
up a valid range for the PCIe downstream busses,
thereby relieving the Linux kernel from "guessing"
the valid range based off _BBN or assuming [0-0xFF].
The Linux kernel code that checks this bus range is
in `drivers/acpi/pci_root.c`. PCI busses can have
up to 256 secondary busses connected to them via
a PCI-PCI bridge. However, these busses do not
have to be sequentially numbered, so leaving out a
section of the range (eg. allowing [0-0x7F]) will
unnecessarily restrict the downstream busses.
Change-Id: Ib2d36f69a26b715798ef1ea17deb0905fa0cad87
Signed-off-by: Mike Loptien <mike.loptien at se-eng.com>
Reviewed-on: http://review.coreboot.org/3822
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
See http://review.coreboot.org/3822 for details.
-gerrit
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