[coreboot-gerrit] New patch to review for coreboot: 942f93a exynos5250: Correct DDR3 Phy-reset value names.

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4357

-gerrit

commit 942f93a1f91ce43389461280feed61bf3f2858dc
Author: Hung-Te Lin <hungte at chromium.org>
Date:   Mon Jul 8 18:41:02 2013 +0800

    exynos5250: Correct DDR3 Phy-reset value names.
    
    The name "LPDDR3PHY_CTRL_PHY_RESET_OFF" is not appropriate because the real
    phy-reset is a low-active pin, so "off(0)" will trigger "start to reset".
    
    To prevent confusion, we should rename the constants to "RESET_ENABLE" and
    "RESET_DISABLE".
    
    Change-Id: Iccba5ef3a2e992f877dea90741f0308c161758c9
    Reviewed-on: https://gerrit.chromium.org/gerrit/61081
    Tested-by: Hung-Te Lin <hungte at chromium.org>
    Reviewed-by: David Hendricks <dhendrix at chromium.org>
    Commit-Queue: Hung-Te Lin <hungte at chromium.org>
---
 src/cpu/samsung/exynos5250/dmc_init_ddr3.c | 4 ++--
 src/cpu/samsung/exynos5250/setup.h         | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c
index 554f4c2..ae76b41 100644
--- a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c
+++ b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c
@@ -33,8 +33,8 @@ static void reset_phy_ctrl(void)
 {
 	struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
 
-	writel(LPDDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl);
-	writel(LPDDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl);
+	writel(LPDDR3PHY_CTRL_PHY_RESET_ENABLE, &clk->lpddr3phy_ctrl);
+	writel(LPDDR3PHY_CTRL_PHY_RESET_DISABLE, &clk->lpddr3phy_ctrl);
 
 #if 0
 	/*
diff --git a/src/cpu/samsung/exynos5250/setup.h b/src/cpu/samsung/exynos5250/setup.h
index 9f10786..2ed4f22 100644
--- a/src/cpu/samsung/exynos5250/setup.h
+++ b/src/cpu/samsung/exynos5250/setup.h
@@ -624,8 +624,8 @@ struct exynos5_phy_control;
  */
 #define DECPROTXSET		0xFF
 
-#define LPDDR3PHY_CTRL_PHY_RESET	(1 << 0)
-#define LPDDR3PHY_CTRL_PHY_RESET_OFF	(0 << 0)
+#define LPDDR3PHY_CTRL_PHY_RESET_DISABLE	(1 << 0)
+#define LPDDR3PHY_CTRL_PHY_RESET_ENABLE		(0 << 0	)
 
 #define PHY_CON0_RESET_VAL	0x17020a40
 #define P0_CMD_EN		(1 << 14)