[coreboot-gerrit] Patch set updated for coreboot: 7439b11 falco: fix usb port settings

Stefan Reinauer (stefan.reinauer@coreboot.org) gerrit at coreboot.org
Sat Dec 7 04:43:12 CET 2013


Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4350

-gerrit

commit 7439b11335a4ff0e32291200f22960a20eef5096
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Jul 9 11:08:52 2013 -0700

    falco: fix usb port settings
    
    USB2 Port A set to 6.4" and Back Panel
    USB2 Port B set to 5.2" and Back Panel
    USB2 Port C set to 12.3" and Internal
    
    Other devices all set to Internal.
    
    build and boot on falco and check settings.
    
    Based on the config settings all ports end up with
    tuning param 1 == 5 and param 2 == 2
    
    U2ECR[0] = 0x00059501
    U2ECR[1] = 0x00059501
    U2ECR[2] = 0x00059501
    U2ECR[3] = 0x00059501
    U2ECR[4] = 0x00059501
    U2ECR[5] = 0x00059501
    U2ECR[6] = 0x00059501
    U2ECR[7] = 0x00059e01
    
    Change-Id: I6b9e6df2679036a501355e6b389a486a6f178f99
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/61297
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/mainboard/google/falco/romstage.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/mainboard/google/falco/romstage.c b/src/mainboard/google/falco/romstage.c
index e284491..fcf06a9 100644
--- a/src/mainboard/google/falco/romstage.c
+++ b/src/mainboard/google/falco/romstage.c
@@ -134,22 +134,22 @@ void mainboard_romstage_entry(unsigned long bist)
 		max_ddr3_freq: 1600,
 		usb2_ports: {
 			/* Length, Enable, OCn#, Location */
-			{ 0x0040, 1, 0,               /* P0: Port A, CN8 */
+			{ 0x0064, 1, 0,               /* P0: Port A, CN8 */
 			  USB_PORT_BACK_PANEL },
-			{ 0x0040, 1, 0,               /* P1: Port B, CN9  */
+			{ 0x0052, 1, 0,               /* P1: Port B, CN9  */
 			  USB_PORT_BACK_PANEL },
 			{ 0x0040, 1, USB_OC_PIN_SKIP, /* P2: CCD */
 			  USB_PORT_INTERNAL },
 			{ 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */
-			  USB_PORT_MINI_PCIE },
+			  USB_PORT_INTERNAL },
 			{ 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */
-			  USB_PORT_MINI_PCIE },
+			  USB_PORT_INTERNAL },
 			{ 0x0040, 1, USB_OC_PIN_SKIP, /* P5: TOUCH */
-			  USB_PORT_FLEX },
+			  USB_PORT_INTERNAL },
 			{ 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */
-			  USB_PORT_FLEX },
-			{ 0x0040, 1, 3,               /* P7: USB2 Port */
-			  USB_PORT_FRONT_PANEL },
+			  USB_PORT_INTERNAL },
+			{ 0x0123, 1, 3,               /* P7: USB2 Port */
+			  USB_PORT_INTERNAL },
 		},
 		usb3_ports: {
 			/* Enable, OCn# */



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