[coreboot-gerrit] Patch merged into coreboot/master: 31eeaab exynos5250: Correct DDR3 Phy-reset value names.

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 31eeaabf3126a986c7947d7b4e7d438b310476d2
Author: Hung-Te Lin <hungte at chromium.org>
Date:   Mon Jul 8 18:41:02 2013 +0800

    exynos5250: Correct DDR3 Phy-reset value names.
    
    The name "LPDDR3PHY_CTRL_PHY_RESET_OFF" is not appropriate because the real
    phy-reset is a low-active pin, so "off(0)" will trigger "start to reset".
    
    To prevent confusion, we should rename the constants to "RESET_ENABLE" and
    "RESET_DISABLE".
    
    Change-Id: Iccba5ef3a2e992f877dea90741f0308c161758c9
    Reviewed-on: https://gerrit.chromium.org/gerrit/61081
    Tested-by: Hung-Te Lin <hungte at chromium.org>
    Reviewed-by: David Hendricks <dhendrix at chromium.org>
    Commit-Queue: Hung-Te Lin <hungte at chromium.org>


See http://review.coreboot.org/4357 for details.

-gerrit