[coreboot-gerrit] Patch set updated for coreboot: 096ff6c lynxpoint: Don't write to non-existent EHCI

[Stefan Reinauer (stefan.reinauer@coreboot.org)]

Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4405

-gerrit

commit 096ff6ccac646b720663dff2e01298653f0c24c9
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Jul 30 15:45:25 2013 -0700

    lynxpoint: Don't write to non-existent EHCI
    
    The LynxPoint-LP chipset only has one EHCI controller so we should
    not attempt to write into the second one that only exists on LynxPoint-H.
    
    Change-Id: I1eae060c7f0a5873c9684e5abfeea5cb5895ab62
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/63799
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/southbridge/intel/lynxpoint/early_pch.c | 6 ++++++
 src/southbridge/intel/lynxpoint/early_usb.c | 5 ++---
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index 38506c9..9909bb6 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -42,6 +42,12 @@ const struct rcba_config_instruction pch_early_config[] = {
 	RCBA_END_CONFIG,
 };
 
+int pch_is_lp(void)
+{
+	u8 id = pci_read_config8(PCH_LPC_DEV, PCI_DEVICE_ID + 1);
+	return id == PCH_TYPE_LPT_LP;
+}
+
 static void pch_enable_bars(void)
 {
 	/* Setting up Southbridge. In the northbridge code. */
diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c
index 9a1a4cb..d328ef6 100644
--- a/src/southbridge/intel/lynxpoint/early_usb.c
+++ b/src/southbridge/intel/lynxpoint/early_usb.c
@@ -54,7 +54,6 @@ static void enable_usb_bar_on_device(device_t dev, u32 bar)
 void enable_usb_bar(void)
 {
 	enable_usb_bar_on_device(PCH_EHCI1_DEV, PCH_EHCI1_TEMP_BAR0);
-#if !CONFIG_INTEL_LYNXPOINT_LP
-	enable_usb_bar_on_device(PCH_EHCI2_DEV, PCH_EHCI2_TEMP_BAR0);
-#endif
+	if (!pch_is_lp())
+		enable_usb_bar_on_device(PCH_EHCI2_DEV, PCH_EHCI2_TEMP_BAR0);
 }