[coreboot-gerrit] Patch set updated for coreboot: bacede8 lynxpoint: Avoid any ME device communication in S3 path

Patrick Georgi (patrick@georgi-clan.de) gerrit at coreboot.org
Fri Dec 20 23:32:05 CET 2013


Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4376

-gerrit

commit bacede8b4079b7a19ff964d6a41f66855c1ca901
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Mon Jul 22 08:47:43 2013 -0700

    lynxpoint: Avoid any ME device communication in S3 path
    
    The management engine is occasionally hanging the system on resume
    when it is accessed.  Since we actually don't need to do anything
    with it on resume it can be disabled early in the resume path and
    avoid assigning resources just to remove them later.
    
    suspend/resume on falco and check /sys/firmware/log
    to ensure that device 00:16.0 is disabled early and that no
    resources are probed or assigned and that the device init path
    does not execute.
    
    Change-Id: I35573681e3a1d43d816d24954842cbe9c61f3484
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/62897
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/southbridge/intel/lynxpoint/me_9.x.c | 32 +++++++++++++-------------------
 1 file changed, 13 insertions(+), 19 deletions(-)

diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index 5aa74f0..eebc451 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -574,13 +574,6 @@ static me_bios_path intel_me_path(device_t dev)
 	struct me_hfs hfs;
 	struct me_hfs2 hfs2;
 
-#if CONFIG_HAVE_ACPI_RESUME
-	/* S3 wake skips all MKHI messages */
-	if (acpi_slp_type == 3) {
-		return ME_S3WAKE_BIOS_PATH;
-	}
-#endif
-
 	pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
 	pci_read_dword_ptr(dev, &hfs2, PCI_ME_HFS2);
 
@@ -721,13 +714,6 @@ static int intel_me_extend_valid(device_t dev)
 	return 0;
 }
 
-/* Hide the ME virtual PCI devices */
-static void intel_me_hide(device_t dev)
-{
-	dev->enabled = 0;
-	pch_enable(dev);
-}
-
 /* Check whether ME is present and do basic init */
 static void intel_me_init(device_t dev)
 {
@@ -737,10 +723,7 @@ static void intel_me_init(device_t dev)
 	/* Do initial setup and determine the BIOS path */
 	printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]);
 
-	if (path == ME_S3WAKE_BIOS_PATH) {
-		intel_me_hide(dev);
-		return;
-	} else if (path == ME_NORMAL_BIOS_PATH) {
+	if (path == ME_NORMAL_BIOS_PATH) {
 		/* Validate the extend register */
 		/* FIXME: force recovery mode on failure. */
 		intel_me_extend_valid(dev);
@@ -794,12 +777,23 @@ static struct pci_operations pci_ops = {
 	.set_subsystem = set_subsystem,
 };
 
+static void intel_me_enable(device_t dev)
+{
+#if CONFIG_HAVE_ACPI_RESUME
+	/* Avoid talking to the device in S3 path */
+	if (acpi_slp_type == 3) {
+		dev->enabled = 0;
+		pch_disable_devfn(dev);
+	}
+#endif
+}
+
 static struct device_operations device_ops = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
+	.enable			= intel_me_enable,
 	.init			= intel_me_init,
-	.scan_bus		= scan_static_bus,
 	.ops_pci		= &pci_ops,
 };
 



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