[coreboot-gerrit] Patch set updated for coreboot: b2f76b1 falco: add rtd2132 settings to device tree

Patrick Georgi (patrick@georgi-clan.de) gerrit at coreboot.org
Fri Dec 20 23:32:26 CET 2013


Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4472

-gerrit

commit b2f76b159ae8c9b8bec060b0d5311b4bd82ffc07
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Wed Aug 14 11:31:39 2013 -0500

    falco: add rtd2132 settings to device tree
    
    Now that the rtd2132 device has the full settings the
    panel timings need to be implemented. Sadly, the Tx timings
    in the rtd2132 aren't 1:1 with the panel's Tx timings. Below
    is the table equivalent:
    
      RTD2132 | Falco Panel
      --------+------------
         T1   |    T2
      --------+------------
         T2   | T8+T10+T12
      --------+------------
         T3   |    T14
      --------+------------
         T4   |    T15
      --------+------------
         T5   | T9+T11+T13
      --------+------------
         T6   |    T3
      --------+------------
         T7   |    T4
      --------+------------
    
    Change-Id: I10a3ad475d6b9485a707eb49e31afd197fc8d24d
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65858
    Reviewed-by: Stefan Reinauer <reinauer at google.com>
---
 src/mainboard/google/falco/devicetree.cb | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/src/mainboard/google/falco/devicetree.cb b/src/mainboard/google/falco/devicetree.cb
index f453fd2..ab8beae 100644
--- a/src/mainboard/google/falco/devicetree.cb
+++ b/src/mainboard/google/falco/devicetree.cb
@@ -116,6 +116,27 @@ chip northbridge/intel/haswell
 			device pci 1f.2 on end # SATA Controller
 			device pci 1f.3 on # SMBus
 				chip drivers/i2c/rtd2132
+					# Panel Power Timings (1 ms units)
+					# Note: the panel Tx timings are very
+					# different from the LVDS bridge
+					# Tx timing settings. Below is a mapping
+					# for RTD2132 -> Panel timings.
+					# T1 = T2
+					# T2 = T8 + T10 + T12
+					# T3 = T14
+					# T4 = T15
+					# T5 = T9 + T11 + T13
+					# T6 = T3
+					# T7 = T4
+					register "t1" = "20"
+					register "t2" = "16"
+					register "t3" = "1"
+					register "t4" = "1"
+					register "t5" = "16"
+					register "t6" = "20"
+					register "t7" = "500"
+					# LVDS Swap settings are normal.
+					register "lvds_swap" = "0"
 					# Enable Spread Sprectrum at 1.0%
 					register "sscg_percent" = "0x10"
 					device i2c 35 on end



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