[coreboot-gerrit] Patch merged into coreboot/master: 4cdface lynxpoint xhci: Add ACPI D0/D3 workarounds

gerrit at coreboot.org gerrit at coreboot.org
Sat Dec 21 07:38:39 CET 2013


the following patch was just integrated into master:
commit 4cdface8d70a3bca49c33219b8d8e348e6b9e8bf
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Jul 19 08:41:38 2013 -0700

    lynxpoint xhci: Add ACPI D0/D3 workarounds
    
    There are specific programming requirements for the usb3 ports
    on all LynxPoint chipsets when transitioning to D0 or D3.
    
    LynxPoint-LP has additional workaround steps needed involving
    resetting the disconnected ports when transitioning to D0.
    
    The workarounds are implemented in ACPI code so the controller
    can transition properly into D3 at runtime.
    
    Change-Id: I3b428562f48c9cb250b97779a3b2753ed4f81509
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/62632
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See http://review.coreboot.org/4374 for details.

-gerrit



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