[coreboot-gerrit] Patch set updated for coreboot: 91ba3cb haswell: add option to change DqPinsInterleaved

Patrick Georgi (patrick@georgi-clan.de) gerrit at coreboot.org
Sat Dec 21 09:14:45 CET 2013


Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4474

-gerrit

commit 91ba3cb23f969d0a7f4d3e078a8605f9d3bc0260
Author: Stefan Reinauer <reinauer at chromium.org>
Date:   Tue Aug 13 11:18:42 2013 -0700

    haswell: add option to change DqPinsInterleaved
    
    Some mainboards will need to have this set.
    
    Signed-off-by: Stefan Reinauer <reinauer at google.com>
    
    Change-Id: I4732a9af822a60b5050d03d2ac4bb7cbd6c723d0
    Reviewed-on: https://gerrit.chromium.org/gerrit/65722
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Tested-by: Stefan Reinauer <reinauer at google.com>
    Commit-Queue: Stefan Reinauer <reinauer at google.com>
---
 src/northbridge/intel/haswell/pei_data.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h
index f9d6e8b..f92c0a6 100644
--- a/src/northbridge/intel/haswell/pei_data.h
+++ b/src/northbridge/intel/haswell/pei_data.h
@@ -31,7 +31,7 @@
 #define PEI_DATA_H
 
 typedef void (*tx_byte_func)(unsigned char byte);
-#define PEI_VERSION 14
+#define PEI_VERSION 15
 
 #define MAX_USB2_PORTS 16
 #define MAX_USB3_PORTS 16
@@ -92,6 +92,7 @@ struct pei_data
 	int dimm_channel1_disabled;
 	/* Enable 2x Refresh Mode */
 	int ddr_refresh_2x;
+	int dq_pins_interleaved;
 	/* Data read from flash and passed into MRC */
 	unsigned char *mrc_input;
 	unsigned int mrc_input_len;



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