[coreboot-gerrit] Patch set updated for coreboot: 7b698dd lynxpoint: Add devicetree config option to force enable ASPM

[Patrick Georgi (patrick@georgi-clan.de)]

Patrick Georgi (patrick at georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4453

-gerrit

commit 7b698dd3cfe05cca8ed6931678839cd01ea0e98f
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Fri Aug 9 09:06:41 2013 -0700

    lynxpoint: Add devicetree config option to force enable ASPM
    
    The PCIe root port has ASPM settings/workarounds that are only applied
    based on the value of an undocumented bit in PCI config register 0x32C.
    
    If that bit is not set for some reason then the settings are not applied.
    This devicetree config option will force the ASPM settings for each port
    based on the bit map.
    
    Change-Id: I40b08ca9a0ef52742609bac72fb821454a373799
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
    Reviewed-on: https://gerrit.chromium.org/gerrit/65314
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
---
 src/southbridge/intel/lynxpoint/chip.h | 2 ++
 src/southbridge/intel/lynxpoint/pcie.c | 8 ++++++++
 2 files changed, 10 insertions(+)

diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h
index a0e2232..bb4c004 100644
--- a/src/southbridge/intel/lynxpoint/chip.h
+++ b/src/southbridge/intel/lynxpoint/chip.h
@@ -85,6 +85,8 @@ struct southbridge_intel_lynxpoint_config {
 
 	/* Enable linear PCIe Root Port function numbers starting at zero */
 	uint8_t pcie_port_coalesce;
+	/* Force root port ASPM configuration with port bitmap */
+	uint8_t pcie_port_force_aspm;
 
 	/* Serial IO configuration */
 	/* Put devices into ACPI mode instead of a PCI device */
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index e133feb..6a4d75c 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -495,6 +495,7 @@ static void pch_pcie_early(struct device *dev)
 	int rp;
 	int do_aspm;
 	int is_lp;
+	struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
 
 	rp = root_port_number(dev);
 	do_aspm = 0;
@@ -542,6 +543,13 @@ static void pch_pcie_early(struct device *dev)
 		}
 	}
 
+	/* Allow ASPM to be forced on in devicetree */
+	if (config && (config->pcie_port_force_aspm & (1 << (rp - 1))))
+		do_aspm = 1;
+
+	printk(BIOS_DEBUG, "PCIe Root Port %d ASPM is %sabled\n",
+	       rp, do_aspm ? "en" : "dis");
+
 	if (do_aspm) {
 		/* Set ASPM bits in MPC2 register. */
 		pcie_update_cfg(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2));