[coreboot-gerrit] Patch merged into coreboot/master: a6d6ddf lynxpoint: Fix an issue clearing port change status bits
gerrit at coreboot.org
gerrit at coreboot.org
Sat Dec 21 23:55:00 CET 2013
the following patch was just integrated into master:
commit a6d6ddf7688258a3aa66ccbf2ea580ad750e9577
Author: Duncan Laurie <dlaurie at chromium.org>
Date: Tue Aug 13 13:32:28 2013 -0700
lynxpoint: Fix an issue clearing port change status bits
The coreboot and ACPI code that clears USB3 PORTSC change status
bits was not properly preserving the state of the PED (port enabled
or disabled) status bit, and it could write 0 back to this field
which would disable the port.
Additionally add back the code that resets disconnected USB3 ports
on the way into suspend (as stated in the BWG) but take care to
clear the PME status bit so we don't immediately wake.
suspend/resume with USB3 devices
1) suspend with no devices, plug in while suspended, then resume
and verify that the devices are detected
2) suspend with USB3 devices inserted, then suspend and resume
and verify that the devices are detected
3) suspend with USB3 devices inserted, then remove the devices
while suspended, resume and ensure they can be detected again
when inserted after resume
Change-Id: Ic7e8d375dfe645cf0dc1f041c3a3d09d0ead1a51
Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65733
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Commit-Queue: Aaron Durbin <adurbin at chromium.org>
See http://review.coreboot.org/4473 for details.
-gerrit
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