[coreboot-gerrit] New patch to review for coreboot: b1cfdca exynos5420: Change some clock settings.

Gabe Black (gabeblack@chromium.org) gerrit at coreboot.org
Tue Jul 9 05:29:37 CEST 2013


Gabe Black (gabeblack at chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3700

-gerrit

commit b1cfdcaf828e5f64a9dfa8a32a4f21ff4ad558d4
Author: Gabe Black <gabeblack at google.com>
Date:   Sat Jun 22 20:05:37 2013 -0700

    exynos5420: Change some clock settings.
    
    This change adjusts some clock settings so that they match U-Boot. There are
    three different changes.
    
    1. Change the source for psgen from the oscillator clock to the pclk.
    2. Change the pll feeding the SPI busses from epll to mpll, as suggested in
       the manual.
    3. Change the SPI prescaller.
    
    Change-Id: Ib54a255bc14fc286629dac86db9b8cf8e75a610b
    Signed-off-by: Gabe Black <gabeblack at chromium.org>
---
 src/cpu/samsung/exynos5420/setup.h | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/src/cpu/samsung/exynos5420/setup.h b/src/cpu/samsung/exynos5420/setup.h
index 7d486f0..7d63772 100644
--- a/src/cpu/samsung/exynos5420/setup.h
+++ b/src/cpu/samsung/exynos5420/setup.h
@@ -227,7 +227,7 @@ struct exynos5_phy_control;
 #define CLK_SRC_TOP2_VAL	0x11101000
 #define CLK_SRC_TOP3_VAL	0x11111111
 #define CLK_SRC_TOP4_VAL	0x11110111
-#define CLK_SRC_TOP5_VAL	0x11111100
+#define CLK_SRC_TOP5_VAL	0x11111110
 #define CLK_SRC_TOP7_VAL	0x00022200
 
 /* CLK_DIV_TOP */
@@ -332,10 +332,11 @@ struct exynos5_phy_control;
 				| (UART0_SEL << 4))
 
 /* CLK_SRC_PERIC1 */
+/* SRC_CLOCK = SCLK_MPLL */
+#define SPI0_SEL		3
+#define SPI1_SEL		3
+#define SPI2_SEL		3
 /* SRC_CLOCK = SCLK_EPLL */
-#define SPI0_SEL		6
-#define SPI1_SEL		6
-#define SPI2_SEL		6
 #define AUDIO0_SEL		6
 #define AUDIO1_SEL		6
 #define AUDIO2_SEL		6
@@ -395,9 +396,9 @@ struct exynos5_phy_control;
 				| (AUDIO0_RATIO << 20))
 
 /* CLK_DIV_PERIC4 */
-#define SPI2_PRE_RATIO		0x2
-#define SPI1_PRE_RATIO		0x2
-#define SPI0_PRE_RATIO		0x2
+#define SPI2_PRE_RATIO		0x3
+#define SPI1_PRE_RATIO		0x3
+#define SPI0_PRE_RATIO		0x3
 #define CLK_DIV_PERIC4_VAL	((SPI2_PRE_RATIO << 24)	\
 				| (SPI1_PRE_RATIO << 16) \
 				| (SPI0_PRE_RATIO << 8))



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