[coreboot-gerrit] New patch to review for coreboot: c81d27c change to (u32 *)(Data+nvram_pos) in src/cpu/amd/agesa/s3_resume.c
Siyuan Wang (wangsiyuanbuaa@gmail.com)
gerrit at coreboot.org
Thu Jul 11 12:03:53 CEST 2013
Siyuan Wang (wangsiyuanbuaa at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3765
-gerrit
commit c81d27c9c58d0ad65a80b8b4650bc71e0701c346
Author: Siyuan Wang <wangsiyuanbuaa at gmail.com>
Date: Thu Jul 11 17:26:18 2013 +0800
change to (u32 *)(Data+nvram_pos) in src/cpu/amd/agesa/s3_resume.c
As Paul pointed in AMD S3 resume: Add framwork to write bigger data[1],
change pointer from (u8 *)(Data+nvram_pos) to (u32 *)(Data+nvram_pos).
I have tested on Parmer.
[1] http://review.coreboot.org/#/c/3413/
Change-Id: Icc0cedffc4c488d1e86d5d0aad526ba69584c77f
Signed-off-by: Siyuan Wang <SiYuan.Wang at amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa at gmail.com>
---
src/cpu/amd/agesa/s3_resume.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c
index 6ba9212..5cf37cb 100644
--- a/src/cpu/amd/agesa/s3_resume.c
+++ b/src/cpu/amd/agesa/s3_resume.c
@@ -272,9 +272,9 @@ u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data)
for (nvram_pos = 0; nvram_pos < DataSize - CONFIG_AMD_SB_SPI_TX_LEN; nvram_pos += CONFIG_AMD_SB_SPI_TX_LEN) {
data = *(u32 *) (Data + nvram_pos);
- flash->write(flash, nvram_pos + pos + 4, CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(Data + nvram_pos));
+ flash->write(flash, nvram_pos + pos + 4, CONFIG_AMD_SB_SPI_TX_LEN, (u32 *)(Data + nvram_pos));
}
- flash->write(flash, nvram_pos + pos + 4, DataSize % CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(Data + nvram_pos));
+ flash->write(flash, nvram_pos + pos + 4, DataSize % CONFIG_AMD_SB_SPI_TX_LEN, (u32 *)(Data + nvram_pos));
flash->spi->rw = SPI_WRITE_FLAG;
spi_release_bus(flash->spi);
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