[coreboot-gerrit] Patch set updated for coreboot: 081a3a3 intel/gm45: Use MMCONF_SUPPORT_DEFAULT
Kyösti Mälkki (kyosti.malkki@gmail.com)
gerrit at coreboot.org
Fri Jul 26 07:16:24 CEST 2013
Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3600
-gerrit
commit 081a3a3f2742a8ccf33b3085dedad5deb37e714b
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date: Mon Jul 1 11:21:53 2013 +0300
intel/gm45: Use MMCONF_SUPPORT_DEFAULT
Change all PCI configuration accesses to MMIO for all boards
with gm45 chipset. To enable MMIO style access, add explicit
PCI IO config write in the bootblock.
Change-Id: Id1c839b7d669946e0ca8b6837e5152ebcb9cd334
Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
src/northbridge/intel/gm45/Kconfig | 4 ++++
src/northbridge/intel/gm45/bootblock.c | 27 +++++++++++++++++++++++++++
src/northbridge/intel/gm45/early_init.c | 5 -----
3 files changed, 31 insertions(+), 5 deletions(-)
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index 16a0bf1..adf1c1b 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -29,4 +29,8 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select MMCONF_SUPPORT_DEFAULT
select IOMMU
+config BOOTBLOCK_NORTHBRIDGE_INIT
+ string
+ default "northbridge/intel/gm45/bootblock.c"
+
endif
diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c
new file mode 100644
index 0000000..fb40b94
--- /dev/null
+++ b/src/northbridge/intel/gm45/bootblock.c
@@ -0,0 +1,27 @@
+#include <arch/io.h>
+
+/* Just re-define these instead of including gm45.h. It blows up romcc. */
+#define D0F0_PCIEXBAR_LO 0x60
+#define D0F0_PCIEXBAR_HI 0x64
+
+static void bootblock_northbridge_init(void)
+{
+ uint32_t reg;
+
+ /*
+ * The "io" variant of the config access is explicitly used to
+ * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to
+ * to true. That way all subsequent non-explicit config accesses use
+ * MCFG. This code also assumes that bootblock_northbridge_init() is
+ * the first thing called in the non-asm boot block code. The final
+ * assumption is that no assembly code is using the
+ * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses.
+ *
+ * The PCIEXBAR is assumed to live in the memory mapped IO space under
+ * 4GiB.
+ */
+ reg = 0;
+ pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_HI, reg);
+ reg = CONFIG_MMCONF_BASE_ADDRESS | (2 << 1) | 1; /* 64MiB - 0-63 buses. */
+ pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg);
+}
diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c
index 052c517..ed5bf99 100644
--- a/src/northbridge/intel/gm45/early_init.c
+++ b/src/northbridge/intel/gm45/early_init.c
@@ -25,11 +25,6 @@ void gm45_early_init(void)
{
const device_t d0f0 = PCI_DEV(0, 0, 0);
- /* Setup PCIEXBAR. */
- pci_io_write_config32(d0f0, D0F0_PCIEXBAR_LO,
- /* 64MB, enable */
- DEFAULT_PCIEXBAR | (2 << 1) | 1);
-
/* Setup MCHBAR. */
pci_write_config32(d0f0, D0F0_MCHBAR_LO, DEFAULT_MCHBAR | 1);
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