[coreboot-gerrit] New patch to review for coreboot: 65eff4e Rename sb900 Oem.h to OEM.h and SbEarly.h to sb_cimx.h
Corey Osgood (corey.osgood@gmail.com)
gerrit at coreboot.org
Sun Jul 28 11:50:19 CEST 2013
Corey Osgood (corey.osgood at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3825
-gerrit
commit 65eff4eca11b9d55f37d1d22c78e71123116b6f9
Author: Corey Osgood <corey.osgood at gmail.com>
Date: Sun Jul 28 05:36:45 2013 -0400
Rename sb900 Oem.h to OEM.h and SbEarly.h to sb_cimx.h
Northbridge code includes these headers, so they all need to
have the same name to allow e.g. agesa/fam14 to use either
sb800 or sb900 seemlessly.
Change-Id: I7a654ce9ae591a636a56177f64fb8cb953b4b04f
Signed-off-by: Corey Osgood <corey.osgood at gmail.com>
---
src/mainboard/amd/torpedo/get_bus_conf.c | 2 +-
src/mainboard/amd/torpedo/romstage.c | 2 +-
src/northbridge/amd/agesa/family12/northbridge.c | 2 +-
src/southbridge/amd/cimx/sb900/SbEarly.h | 56 -----
src/southbridge/amd/cimx/sb900/SbPlatform.h | 2 +-
src/southbridge/amd/cimx/sb900/early.c | 2 +-
src/southbridge/amd/cimx/sb900/sb_cimx.h | 56 +++++
.../amd/agesa/f12/Proc/Fch/FchPlatform.h | 2 +-
src/vendorcode/amd/cimx/sb900/OEM.h | 233 +++++++++++++++++++++
src/vendorcode/amd/cimx/sb900/Oem.h | 233 ---------------------
10 files changed, 295 insertions(+), 295 deletions(-)
diff --git a/src/mainboard/amd/torpedo/get_bus_conf.c b/src/mainboard/amd/torpedo/get_bus_conf.c
index 4444937..fcc5e8d 100644
--- a/src/mainboard/amd/torpedo/get_bus_conf.c
+++ b/src/mainboard/amd/torpedo/get_bus_conf.c
@@ -24,7 +24,7 @@
#include <stdint.h>
#include <stdlib.h>
#include <cpu/amd/amdfam12.h>
-#include "SbEarly.h"
+#include "sb_cimx.h"
#include "agesawrapper.h"
/* Global variables for MB layouts and these will be shared by irqtable mptable
diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c
index bbcd764..00044c6 100644
--- a/src/mainboard/amd/torpedo/romstage.c
+++ b/src/mainboard/amd/torpedo/romstage.c
@@ -33,7 +33,7 @@
#include "cpu/x86/lapic/boot_cpu.c"
#include "drivers/pc80/i8254.c"
#include "drivers/pc80/i8259.c"
-#include "SbEarly.h"
+#include "sb_cimx.h"
#include "SbPlatform.h"
#include <arch/cpu.h>
#include "platform_cfg.h"
diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c
index 621246f..76a9604 100644
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -34,7 +34,7 @@
#include <cpu/amd/mtrr.h>
#include "northbridge.h"
-#include "SbEarly.h"
+#include "sb_cimx.h"
#include "agesawrapper.h"
//#define FX_DEVS NODE_NUMS
diff --git a/src/southbridge/amd/cimx/sb900/SbEarly.h b/src/southbridge/amd/cimx/sb900/SbEarly.h
deleted file mode 100644
index c5e37e5..0000000
--- a/src/southbridge/amd/cimx/sb900/SbEarly.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-#ifndef _CIMX_SB_EARLY_H_
-#define _CIMX_SB_EARLY_H_
-
-#define PM_INDEX 0xcd6
-#define PM_DATA 0xcd7
-
-#define SB900_ACPI_IO_BASE 0x800
-
-#define ACPI_PM_EVT_BLK (SB900_ACPI_IO_BASE + 0x00) /* 4 bytes */
-#define ACPI_PM1_CNT_BLK (SB900_ACPI_IO_BASE + 0x04) /* 2 bytes */
-#define ACPI_PMA_CNT_BLK (SB900_ACPI_IO_BASE + 0x0F) /* 1 byte */
-#define ACPI_PM_TMR_BLK (SB900_ACPI_IO_BASE + 0x08) /* 4 bytes */
-#define ACPI_GPE0_BLK (SB900_ACPI_IO_BASE + 0x20) /* 8 bytes */
-#define ACPI_CPU_CONTROL (SB900_ACPI_IO_BASE + 0x10) /* 6 bytes */
-
-#define REV_SB900_A11 0x11
-#define REV_SB900_A12 0x12
-
-/**
- * @brief Get SouthBridge device number, called by finalize_node_setup()
- * @param[in] bus target bus number
- * @return southbridge device number
- */
-u32 get_sbdn(u32 bus);
-
-/**
- * South Bridge CIMx romstage entry, sbPowerOnInit entry point wrapper.
- */
-void sb_poweron_init(void);
-void sb_before_pci_init(void);
-
-void sb_After_Pci_Init (void);
-void sb_Mid_Post_Init (void);
-void sb_Late_Post (void);
-
-#endif
diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h
index 36c186a..5e41978 100644
--- a/src/southbridge/amd/cimx/sb900/SbPlatform.h
+++ b/src/southbridge/amd/cimx/sb900/SbPlatform.h
@@ -67,7 +67,7 @@ typedef union _PCI_ADDR {
#include "AmdSbLib.h"
#include "SbSubFun.h"
#include "platform_cfg.h" /* mainboard specific configuration */
-#include "Oem.h" /* platform default configuration */
+#include "OEM.h" /* platform default configuration */
#include "AMD.h"
#include "SbBiosRamUsage.h"
#include "EcFan.h"
diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c
index d6036dd..8ed5c29 100644
--- a/src/southbridge/amd/cimx/sb900/early.c
+++ b/src/southbridge/amd/cimx/sb900/early.c
@@ -24,7 +24,7 @@
#include <device/pci_ids.h>
#include <arch/io.h>
#include "SbPlatform.h"
-#include "SbEarly.h"
+#include "sb_cimx.h"
#include <console/console.h>
#include <console/loglevel.h>
#include "smbus.h"
diff --git a/src/southbridge/amd/cimx/sb900/sb_cimx.h b/src/southbridge/amd/cimx/sb900/sb_cimx.h
new file mode 100644
index 0000000..c5e37e5
--- /dev/null
+++ b/src/southbridge/amd/cimx/sb900/sb_cimx.h
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+
+#ifndef _CIMX_SB_EARLY_H_
+#define _CIMX_SB_EARLY_H_
+
+#define PM_INDEX 0xcd6
+#define PM_DATA 0xcd7
+
+#define SB900_ACPI_IO_BASE 0x800
+
+#define ACPI_PM_EVT_BLK (SB900_ACPI_IO_BASE + 0x00) /* 4 bytes */
+#define ACPI_PM1_CNT_BLK (SB900_ACPI_IO_BASE + 0x04) /* 2 bytes */
+#define ACPI_PMA_CNT_BLK (SB900_ACPI_IO_BASE + 0x0F) /* 1 byte */
+#define ACPI_PM_TMR_BLK (SB900_ACPI_IO_BASE + 0x08) /* 4 bytes */
+#define ACPI_GPE0_BLK (SB900_ACPI_IO_BASE + 0x20) /* 8 bytes */
+#define ACPI_CPU_CONTROL (SB900_ACPI_IO_BASE + 0x10) /* 6 bytes */
+
+#define REV_SB900_A11 0x11
+#define REV_SB900_A12 0x12
+
+/**
+ * @brief Get SouthBridge device number, called by finalize_node_setup()
+ * @param[in] bus target bus number
+ * @return southbridge device number
+ */
+u32 get_sbdn(u32 bus);
+
+/**
+ * South Bridge CIMx romstage entry, sbPowerOnInit entry point wrapper.
+ */
+void sb_poweron_init(void);
+void sb_before_pci_init(void);
+
+void sb_After_Pci_Init (void);
+void sb_Mid_Post_Init (void);
+void sb_Late_Post (void);
+
+#endif
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/FchPlatform.h b/src/vendorcode/amd/agesa/f12/Proc/Fch/FchPlatform.h
index a8ff2f2..0561d3d 100644
--- a/src/vendorcode/amd/agesa/f12/Proc/Fch/FchPlatform.h
+++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/FchPlatform.h
@@ -108,7 +108,7 @@
#include "FchCommonCfg.h"
#include "AcpiLib.h"
#include "FchDef.h"
-#include "Oem.h"
+#include "OEM.h"
#include "FchBiosRamUsage.h"
#include "AmdFch.h"
diff --git a/src/vendorcode/amd/cimx/sb900/OEM.h b/src/vendorcode/amd/cimx/sb900/OEM.h
new file mode 100755
index 0000000..f374b30
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb900/OEM.h
@@ -0,0 +1,233 @@
+/*;********************************************************************************
+;
+; Copyright (c) 2011, Advanced Micro Devices, Inc.
+; All rights reserved.
+;
+; Redistribution and use in source and binary forms, with or without
+; modification, are permitted provided that the following conditions are met:
+; * Redistributions of source code must retain the above copyright
+; notice, this list of conditions and the following disclaimer.
+; * Redistributions in binary form must reproduce the above copyright
+; notice, this list of conditions and the following disclaimer in the
+; documentation and/or other materials provided with the distribution.
+; * Neither the name of Advanced Micro Devices, Inc. nor the names of
+; its contributors may be used to endorse or promote products derived
+; from this software without specific prior written permission.
+;
+; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;
+;*********************************************************************************/
+
+#ifndef BIOS_SIZE
+ #define BIOS_SIZE 0x04 //04 - 1MB
+#endif
+#ifndef LEGACY_FREE
+ #define LEGACY_FREE 0x00
+#endif
+#define ACPI_SLEEP_TRAP 0x01
+//#define SPREAD_SPECTRUM_EPROM_LOAD 0x01
+
+/**
+ * Module Specific Defines for platform BIOS
+ *
+ */
+
+/**
+ * PCIEX_BASE_ADDRESS - Define PCIE base address
+ *
+ * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000
+ */
+#ifdef MOVE_PCIEBAR_TO_F0000000
+ #define PCIEX_BASE_ADDRESS 0xF7000000
+#else
+ #define PCIEX_BASE_ADDRESS 0xE0000000
+#endif
+
+/**
+ * SMBUS0_BASE_ADDRESS - Smbus base address
+ *
+ */
+#ifndef SMBUS0_BASE_ADDRESS
+ #define SMBUS0_BASE_ADDRESS 0xB00
+#endif
+
+/**
+ * SMBUS1_BASE_ADDRESS - Smbus1 (ASF) base address
+ *
+ */
+#ifndef SMBUS1_BASE_ADDRESS
+ #define SMBUS1_BASE_ADDRESS 0xB20
+#endif
+
+/**
+ * SIO_PME_BASE_ADDRESS - Super IO PME base address
+ *
+ */
+#ifndef SIO_PME_BASE_ADDRESS
+ #define SIO_PME_BASE_ADDRESS 0xE00
+#endif
+
+/**
+ * SPI_BASE_ADDRESS - SPI controller (ROM) base address
+ *
+ */
+#ifndef SPI_BASE_ADDRESS
+ #define SPI_BASE_ADDRESS 0xFEC10000
+#endif
+
+/**
+ * WATCHDOG_TIMER_BASE_ADDRESS - WATCHDOG timer base address
+ *
+ */
+#ifndef WATCHDOG_TIMER_BASE_ADDRESS
+ #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address
+#endif
+
+/**
+ * HPET_BASE_ADDRESS - HPET base address
+ *
+ */
+#ifndef HPET_BASE_ADDRESS
+ #define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address
+#endif
+
+/**
+ * ALT_ADDR_400 - For some BIOS codebases which use 0x400 as ACPI base address
+ *
+ */
+#ifdef ALT_ADDR_400
+ #define ACPI_BLK_BASE 0x400
+#else
+ #define ACPI_BLK_BASE 0x800
+#endif
+
+#define PM1_STATUS_OFFSET 0x00
+#define PM1_ENABLE_OFFSET 0x02
+#define PM1_CONTROL_OFFSET 0x04
+#define PM_TIMER_OFFSET 0x08
+#define CPU_CONTROL_OFFSET 0x10
+#define EVENT_STATUS_OFFSET 0x20
+#define EVENT_ENABLE_OFFSET 0x24
+
+/**
+ * PM1_EVT_BLK_ADDRESS - ACPI power management Event Block base address
+ *
+ */
+#define PM1_EVT_BLK_ADDRESS ACPI_BLK_BASE + PM1_STATUS_OFFSET // AcpiPm1EvtBlkAddr
+
+/**
+ * PM1_CNT_BLK_ADDRESS - ACPI power management Control block base address
+ *
+ */
+#define PM1_CNT_BLK_ADDRESS ACPI_BLK_BASE + PM1_CONTROL_OFFSET // AcpiPm1CntBlkAddr
+
+/**
+ * PM1_TMR_BLK_ADDRESS - ACPI power management Timer block base address
+ *
+ */
+#define PM1_TMR_BLK_ADDRESS ACPI_BLK_BASE + PM_TIMER_OFFSET // AcpiPmTmrBlkAddr
+
+/**
+ * CPU_CNT_BLK_ADDRESS - ACPI power management CPU Control block base address
+ *
+ */
+#define CPU_CNT_BLK_ADDRESS ACPI_BLK_BASE + CPU_CONTROL_OFFSET // CpuControlBlkAddr
+
+/**
+ * GPE0_BLK_ADDRESS - ACPI power management General Purpose Event block base address
+ *
+ */
+#define GPE0_BLK_ADDRESS ACPI_BLK_BASE + EVENT_STATUS_OFFSET // AcpiGpe0BlkAddr
+
+/**
+ * SMI_CMD_PORT - ACPI SMI Command block base address
+ *
+ */
+#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr
+
+/**
+ * ACPI_PMA_CNT_BLK_ADDRESS - ACPI power management additional control block base address
+ *
+ */
+#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr
+
+/**
+ * SATA_IDE_MODE_SSID - Sata controller IDE mode SSID.
+ * Define value for SSID while SATA controller set to IDE mode.
+ */
+#define SATA_IDE_MODE_SSID 0x78001022
+/**
+ * SATA_RAID_MODE_SSID - Sata controller RAID mode SSID.
+ * Define value for SSID while SATA controller set to RAID mode.
+ */
+#define SATA_RAID_MODE_SSID 0x78021022
+
+/**
+ * SATA_RAID5_MODE_SSID - Sata controller RAID5 mode SSID.
+ * Define value for SSID while SATA controller set to RAID5 mode.
+ */
+#define SATA_RAID5_MODE_SSID 0x78031022
+
+/**
+ * SATA_AHCI_MODE_SSID - Sata controller AHCI mode SSID.
+ * Define value for SSID while SATA controller set to AHCI mode.
+ */
+#define SATA_AHCI_SSID 0x78011022
+
+/**
+ * OHCI_SSID - All SB OHCI controllers SSID value.
+ *
+ */
+#define OHCI_SSID 0x78071022
+
+/**
+ * EHCI_SSID - All SB EHCI controllers SSID value.
+ *
+ */
+#define EHCI_SSID 0x78081022
+
+/**
+ * OHCI4_SSID - OHCI (USB 1.1 mode *HW force) controllers SSID value.
+ *
+ */
+#define OHCI4_SSID 0x78091022
+
+/**
+ * SMBUS_SSID - Smbus controller (South Bridge device 0x14 function 0) SSID value.
+ *
+ */
+#define SMBUS_SSID 0x780B1022
+
+/**
+ * IDE_SSID - SATA IDE controller (South Bridge device 0x14 function 1) SSID value.
+ *
+ */
+#define IDE_SSID 0x780C1022
+
+/**
+ * AZALIA_SSID - AZALIA controller (South Bridge device 0x14 function 2) SSID value.
+ *
+ */
+#define AZALIA_SSID 0x780D1022
+
+/**
+ * LPC_SSID - LPC controller (South Bridge device 0x14 function 3) SSID value.
+ *
+ */
+#define LPC_SSID 0x780E1022
+
+/**
+ * PCIB_SSID - PCIB controller (South Bridge device 0x14 function 4) SSID value.
+ *
+ */
+#define PCIB_SSID 0x780F1022
+
diff --git a/src/vendorcode/amd/cimx/sb900/Oem.h b/src/vendorcode/amd/cimx/sb900/Oem.h
deleted file mode 100755
index f374b30..0000000
--- a/src/vendorcode/amd/cimx/sb900/Oem.h
+++ /dev/null
@@ -1,233 +0,0 @@
-/*;********************************************************************************
-;
-; Copyright (c) 2011, Advanced Micro Devices, Inc.
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; * Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; * Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; * Neither the name of Advanced Micro Devices, Inc. nor the names of
-; its contributors may be used to endorse or promote products derived
-; from this software without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;
-;*********************************************************************************/
-
-#ifndef BIOS_SIZE
- #define BIOS_SIZE 0x04 //04 - 1MB
-#endif
-#ifndef LEGACY_FREE
- #define LEGACY_FREE 0x00
-#endif
-#define ACPI_SLEEP_TRAP 0x01
-//#define SPREAD_SPECTRUM_EPROM_LOAD 0x01
-
-/**
- * Module Specific Defines for platform BIOS
- *
- */
-
-/**
- * PCIEX_BASE_ADDRESS - Define PCIE base address
- *
- * @param[Option] MOVE_PCIEBAR_TO_F0000000 Set PCIe base address to 0xF7000000
- */
-#ifdef MOVE_PCIEBAR_TO_F0000000
- #define PCIEX_BASE_ADDRESS 0xF7000000
-#else
- #define PCIEX_BASE_ADDRESS 0xE0000000
-#endif
-
-/**
- * SMBUS0_BASE_ADDRESS - Smbus base address
- *
- */
-#ifndef SMBUS0_BASE_ADDRESS
- #define SMBUS0_BASE_ADDRESS 0xB00
-#endif
-
-/**
- * SMBUS1_BASE_ADDRESS - Smbus1 (ASF) base address
- *
- */
-#ifndef SMBUS1_BASE_ADDRESS
- #define SMBUS1_BASE_ADDRESS 0xB20
-#endif
-
-/**
- * SIO_PME_BASE_ADDRESS - Super IO PME base address
- *
- */
-#ifndef SIO_PME_BASE_ADDRESS
- #define SIO_PME_BASE_ADDRESS 0xE00
-#endif
-
-/**
- * SPI_BASE_ADDRESS - SPI controller (ROM) base address
- *
- */
-#ifndef SPI_BASE_ADDRESS
- #define SPI_BASE_ADDRESS 0xFEC10000
-#endif
-
-/**
- * WATCHDOG_TIMER_BASE_ADDRESS - WATCHDOG timer base address
- *
- */
-#ifndef WATCHDOG_TIMER_BASE_ADDRESS
- #define WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 // Watchdog Timer Base Address
-#endif
-
-/**
- * HPET_BASE_ADDRESS - HPET base address
- *
- */
-#ifndef HPET_BASE_ADDRESS
- #define HPET_BASE_ADDRESS 0xFED00000 // HPET Base address
-#endif
-
-/**
- * ALT_ADDR_400 - For some BIOS codebases which use 0x400 as ACPI base address
- *
- */
-#ifdef ALT_ADDR_400
- #define ACPI_BLK_BASE 0x400
-#else
- #define ACPI_BLK_BASE 0x800
-#endif
-
-#define PM1_STATUS_OFFSET 0x00
-#define PM1_ENABLE_OFFSET 0x02
-#define PM1_CONTROL_OFFSET 0x04
-#define PM_TIMER_OFFSET 0x08
-#define CPU_CONTROL_OFFSET 0x10
-#define EVENT_STATUS_OFFSET 0x20
-#define EVENT_ENABLE_OFFSET 0x24
-
-/**
- * PM1_EVT_BLK_ADDRESS - ACPI power management Event Block base address
- *
- */
-#define PM1_EVT_BLK_ADDRESS ACPI_BLK_BASE + PM1_STATUS_OFFSET // AcpiPm1EvtBlkAddr
-
-/**
- * PM1_CNT_BLK_ADDRESS - ACPI power management Control block base address
- *
- */
-#define PM1_CNT_BLK_ADDRESS ACPI_BLK_BASE + PM1_CONTROL_OFFSET // AcpiPm1CntBlkAddr
-
-/**
- * PM1_TMR_BLK_ADDRESS - ACPI power management Timer block base address
- *
- */
-#define PM1_TMR_BLK_ADDRESS ACPI_BLK_BASE + PM_TIMER_OFFSET // AcpiPmTmrBlkAddr
-
-/**
- * CPU_CNT_BLK_ADDRESS - ACPI power management CPU Control block base address
- *
- */
-#define CPU_CNT_BLK_ADDRESS ACPI_BLK_BASE + CPU_CONTROL_OFFSET // CpuControlBlkAddr
-
-/**
- * GPE0_BLK_ADDRESS - ACPI power management General Purpose Event block base address
- *
- */
-#define GPE0_BLK_ADDRESS ACPI_BLK_BASE + EVENT_STATUS_OFFSET // AcpiGpe0BlkAddr
-
-/**
- * SMI_CMD_PORT - ACPI SMI Command block base address
- *
- */
-#define SMI_CMD_PORT 0xB0 // SmiCmdPortAddr
-
-/**
- * ACPI_PMA_CNT_BLK_ADDRESS - ACPI power management additional control block base address
- *
- */
-#define ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 // AcpiPmaCntBlkAddr
-
-/**
- * SATA_IDE_MODE_SSID - Sata controller IDE mode SSID.
- * Define value for SSID while SATA controller set to IDE mode.
- */
-#define SATA_IDE_MODE_SSID 0x78001022
-/**
- * SATA_RAID_MODE_SSID - Sata controller RAID mode SSID.
- * Define value for SSID while SATA controller set to RAID mode.
- */
-#define SATA_RAID_MODE_SSID 0x78021022
-
-/**
- * SATA_RAID5_MODE_SSID - Sata controller RAID5 mode SSID.
- * Define value for SSID while SATA controller set to RAID5 mode.
- */
-#define SATA_RAID5_MODE_SSID 0x78031022
-
-/**
- * SATA_AHCI_MODE_SSID - Sata controller AHCI mode SSID.
- * Define value for SSID while SATA controller set to AHCI mode.
- */
-#define SATA_AHCI_SSID 0x78011022
-
-/**
- * OHCI_SSID - All SB OHCI controllers SSID value.
- *
- */
-#define OHCI_SSID 0x78071022
-
-/**
- * EHCI_SSID - All SB EHCI controllers SSID value.
- *
- */
-#define EHCI_SSID 0x78081022
-
-/**
- * OHCI4_SSID - OHCI (USB 1.1 mode *HW force) controllers SSID value.
- *
- */
-#define OHCI4_SSID 0x78091022
-
-/**
- * SMBUS_SSID - Smbus controller (South Bridge device 0x14 function 0) SSID value.
- *
- */
-#define SMBUS_SSID 0x780B1022
-
-/**
- * IDE_SSID - SATA IDE controller (South Bridge device 0x14 function 1) SSID value.
- *
- */
-#define IDE_SSID 0x780C1022
-
-/**
- * AZALIA_SSID - AZALIA controller (South Bridge device 0x14 function 2) SSID value.
- *
- */
-#define AZALIA_SSID 0x780D1022
-
-/**
- * LPC_SSID - LPC controller (South Bridge device 0x14 function 3) SSID value.
- *
- */
-#define LPC_SSID 0x780E1022
-
-/**
- * PCIB_SSID - PCIB controller (South Bridge device 0x14 function 4) SSID value.
- *
- */
-#define PCIB_SSID 0x780F1022
-
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