[coreboot-gerrit] Patch merged into coreboot/master: f97ff3f dram: Add utilities for decoding DDR3 SPDs

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit f97ff3f72c038b711fd3c1e7b73abaa05add2094
Author: Alexandru Gagniuc <mr.nuke.me at gmail.com>
Date:   Tue May 21 14:43:45 2013 -0500

    dram: Add utilities for decoding DDR3 SPDs
    
    Add convenience utilities for decoding DDR3 SPDs and printing the
    information to the console. These have proven invaluable when writing the
    VX900 memory initialization.
    
    These are used in the VX900 branch
    
    Information printed has the following format:
    
    > SPD Data for DIMM 51
    >   Revision: 10
    >   Type    : b
    >   Key     : 2
    >   Banks   : 8
    >   Capacity: 1 Gb
    >   Supported voltages: 1.5V
    >   SDRAM width       : 8
    >   Bus extension     : 0 bits
    >   Bus width         : 64
    >   Optional features : DLL-Off_mode RZQ/7 RZQ/6
    >   Thermal features  : ASR ext_temp_range
    >   Thermal sensor    : no
    >   Standard SDRAM    : no
    >   Row    addr bits  : 13
    >   Column addr bits  : 10
    >   Number of ranks   : 1
    >   DIMM Capacity     : 1024 MB
    >   CAS latencies     : 6 7 8 9
    >   tCKmin            :   1.500 ns
    >   tAAmin            :  13.125 ns
    >   tWRmin            :  15.000 ns
    >   tRCDmin           :  13.125 ns
    >   tRRDmin           :   6.000 ns
    >   tRPmin            :  13.125 ns
    >   tRASmin           :  36.000 ns
    >   tRCmin            :  49.125 ns
    >   tRFCmin           : 110.000 ns
    >   tWTRmin           :   7.500 ns
    >   tRTPmin           :   7.500 ns
    >   tFAWmin           :  30.000 ns
    
    Change-Id: I30725a75caf74ac637db0a143344562bd9910466
    Signed-off-by: Alexandru Gagniuc <mr.nuke.me at gmail.com>
    Reviewed-on: http://review.coreboot.org/3267
    Tested-by: build bot (Jenkins)


See http://review.coreboot.org/3267 for details.

-gerrit