[coreboot-gerrit] Patch set updated for coreboot: d2e25fb Move the MARK_GRAPHICS_MEM_WRCOMB to x86 architecture

Ronald G. Minnich (rminnich@gmail.com) gerrit at coreboot.org
Tue Jun 4 22:10:29 CEST 2013


Ronald G. Minnich (rminnich at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3349

-gerrit

commit d2e25fb668677a6de0e6fb8ad4e9528f5d270c48
Author: Ronald G. Minnich <rminnich at gmail.com>
Date:   Fri May 31 19:36:52 2013 +0200

    Move the MARK_GRAPHICS_MEM_WRCOMB to x86 architecture
    
    The MARK_GRAPHICS_MEM_WRCOMB was spreading like a cancer
    since it was defined in sandybridge. It is really
    more of an x86 thing however, and we now have
    three systems that can use it.
    
    I considered making this more general, since it technically
    can apply to PTE-based systems like ARM, and maybe we should.
    But the 'WRCOMB' moniker is usually closely tied to the x86.
    
    Change-Id: I3eb6eb2113843643348a5e18e78c53d113899ff8
    Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
---
 src/arch/x86/Kconfig                      | 8 ++++++++
 src/northbridge/intel/haswell/Kconfig     | 8 --------
 src/northbridge/intel/sandybridge/Kconfig | 8 --------
 3 files changed, 8 insertions(+), 16 deletions(-)

diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index c7b2434..69cdc8a 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -1,5 +1,13 @@
 menu "Architecture (x86)"
 
+config MARK_GRAPHICS_MEM_WRCOMB
+	bool "Mark graphics memory as write-combining."
+	default n
+	help
+	 The graphics performance may increase if the graphics
+	 memory is set as write-combining cache type. This option
+	 enables marking the graphics memory as write-combining.
+
 # This is an SMP option. It relates to starting up APs.
 # It is usually set in mainboard/*/Kconfig.
 # TODO: Improve description.
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index 12f865a..f689780 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -82,14 +82,6 @@ config DCACHE_RAM_ROMSTAGE_STACK_SIZE
 	  The amount of anticipated stack usage from the data cache
 	  during pre-ram rom stage execution.
 
-config MARK_GRAPHICS_MEM_WRCOMB
-	bool "Mark graphics memory as write-combining."
-	default n
-	help
-	 The graphics performance may increase if the graphics
-	 memory is set as write-combining cache type. This option
-	 enables marking the graphics memory as write-combining.
-
 config HAVE_MRC
 	bool "Add a System Agent binary"
 	help
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 6c9ae99..56d2cd7 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -107,14 +107,6 @@ config DCACHE_RAM_MRC_VAR_SIZE
 	hex
 	default 0x4000
 
-config MARK_GRAPHICS_MEM_WRCOMB
-	bool "Mark graphics memory as write-combining."
-	default n
-	help
-	 The graphics performance may increase if the graphics
-	 memory is set as write-combining cache type. This option
-	 enables marking the graphics memory as write-combining.
-
 config HAVE_MRC
 	bool "Add a System Agent binary"
 	help



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