[coreboot-gerrit] New patch to review for coreboot: d5e6c6a usbdebug: Drop printk within console_init()

[Kyösti Mälkki (kyosti.malkki@gmail.com)]

Kyösti Mälkki (kyosti.malkki at gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3384

-gerrit

commit d5e6c6a3cd6da6cfd56355e7e53f2011f8f222ab
Author: Kyösti Mälkki <kyosti.malkki at gmail.com>
Date:   Thu Jun 6 12:53:03 2013 +0300

    usbdebug: Drop printk within console_init()
    
    In case with EARLY_CONSOLE, this printk is called before any other
    console is configured to transmit data. This outputs garbage on
    CONSOLE_SERIAL as baudrate is not yet programmed.
    
    For case without EARLY_CONSOLE, the order in which different console
    drivers initialize is obscure. Might sometimes work properly.
    
    Change-Id: I3792161e0a6dc17e17262048cc9136044dd69dc5
    Signed-off-by: Kyösti Mälkki <kyosti.malkki at gmail.com>
---
 src/southbridge/intel/bd82x6x/usb_debug.c   | 1 -
 src/southbridge/intel/i82801gx/usb_debug.c  | 1 -
 src/southbridge/intel/lynxpoint/usb_debug.c | 1 -
 src/southbridge/intel/sch/usb_debug.c       | 1 -
 4 files changed, 4 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/usb_debug.c b/src/southbridge/intel/bd82x6x/usb_debug.c
index 79a43bd..899b53f 100644
--- a/src/southbridge/intel/bd82x6x/usb_debug.c
+++ b/src/southbridge/intel/bd82x6x/usb_debug.c
@@ -37,7 +37,6 @@ void enable_usbdebug(unsigned int port)
 	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
 
 	/* Force ownership of the Debug Port to the EHCI controller. */
-	printk(BIOS_DEBUG, "Enabling OWNER_CNT\n");
 	dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
 	dbgctl |= (1 << 30);
 	write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl);
diff --git a/src/southbridge/intel/i82801gx/usb_debug.c b/src/southbridge/intel/i82801gx/usb_debug.c
index 10a308f3..397c686 100644
--- a/src/southbridge/intel/i82801gx/usb_debug.c
+++ b/src/southbridge/intel/i82801gx/usb_debug.c
@@ -44,7 +44,6 @@ void enable_usbdebug(unsigned int port)
 	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
 
 	/* Force ownership of the Debug Port to the EHCI controller. */
-	printk(BIOS_DEBUG, "Enabling OWNER_CNT\n");
 	dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
 	dbgctl |= (1 << 30);
 	write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl);
diff --git a/src/southbridge/intel/lynxpoint/usb_debug.c b/src/southbridge/intel/lynxpoint/usb_debug.c
index d8da7b5..022cde3 100644
--- a/src/southbridge/intel/lynxpoint/usb_debug.c
+++ b/src/southbridge/intel/lynxpoint/usb_debug.c
@@ -42,7 +42,6 @@ void enable_usbdebug(unsigned int port)
 	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
 
 	/* Force ownership of the Debug Port to the EHCI controller. */
-	printk(BIOS_DEBUG, "Enabling OWNER_CNT\n");
 	dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
 	dbgctl |= (1 << 30);
 	write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl);
diff --git a/src/southbridge/intel/sch/usb_debug.c b/src/southbridge/intel/sch/usb_debug.c
index 4189716..fb436b5 100644
--- a/src/southbridge/intel/sch/usb_debug.c
+++ b/src/southbridge/intel/sch/usb_debug.c
@@ -41,7 +41,6 @@ void enable_usbdebug(unsigned int port)
 	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
 
 	/* Force ownership of the Debug Port to the EHCI controller. */
-	printk(BIOS_DEBUG, "Enabling OWNER_CNT\n");
 	dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
 	dbgctl |= (1 << 30);
 	write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl);