[coreboot-gerrit] New patch to review for coreboot: 6827753 Add Lenovo ThinkPad x201 support
Stefan Reinauer (stefan.reinauer@coreboot.org)
gerrit at coreboot.org
Fri Jun 7 00:38:41 CEST 2013
Stefan Reinauer (stefan.reinauer at coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3401
-gerrit
commit 68277537c4f3f3e1e1ee450df609516448bbbbb9
Author: Stefan Reinauer <stefan.reinauer at coreboot.org>
Date: Fri Jun 7 00:28:01 2013 +0200
Add Lenovo ThinkPad x201 support
Change-Id: Icc1c05a9343a71577e058ebb90bacc2c0bd5688b
Signed-off-by: Vladimir Serbinenko <phcoder at gmail.com>
Signed-off-by: Stefan Reinauer <reinauer at google.com>
---
src/mainboard/lenovo/Kconfig | 9 +
src/mainboard/lenovo/x201/Kconfig | 59 ++
src/mainboard/lenovo/x201/Makefile.inc | 23 +
src/mainboard/lenovo/x201/acpi/dock.asl | 82 ++
src/mainboard/lenovo/x201/acpi/ec.asl | 26 +
src/mainboard/lenovo/x201/acpi/gpe.asl | 30 +
src/mainboard/lenovo/x201/acpi/ich7_pci_irqs.asl | 46 +
src/mainboard/lenovo/x201/acpi/mainboard.asl | 0
src/mainboard/lenovo/x201/acpi/platform.asl | 170 ++++
.../lenovo/x201/acpi/sandybridge_pci_irqs.asl | 87 ++
src/mainboard/lenovo/x201/acpi/superio.asl | 0
src/mainboard/lenovo/x201/acpi/video.asl | 69 ++
src/mainboard/lenovo/x201/acpi_tables.c | 275 ++++++
src/mainboard/lenovo/x201/cmos.layout | 139 +++
src/mainboard/lenovo/x201/devicetree.cb | 148 ++++
src/mainboard/lenovo/x201/dock.c | 61 ++
src/mainboard/lenovo/x201/dock.h | 28 +
src/mainboard/lenovo/x201/dsdt.asl | 94 ++
src/mainboard/lenovo/x201/fadt.c | 159 ++++
src/mainboard/lenovo/x201/irq_tables.c | 62 ++
src/mainboard/lenovo/x201/mainboard.c | 297 +++++++
src/mainboard/lenovo/x201/mptable.c | 61 ++
src/mainboard/lenovo/x201/romstage.c | 985 +++++++++++++++++++++
src/mainboard/lenovo/x201/smi.h | 27 +
src/mainboard/lenovo/x201/smihandler.c | 207 +++++
25 files changed, 3144 insertions(+)
diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig
index 8ee2778..07264b2 100644
--- a/src/mainboard/lenovo/Kconfig
+++ b/src/mainboard/lenovo/Kconfig
@@ -20,10 +20,19 @@ config BOARD_LENOVO_T60
Thinkpad T60p (Model 2007)
+config BOARD_LENOVO_X201
+ bool "ThinkPad X201"
+ help
+ The following T60 series ThinkPad machines have been verified to
+ work correctly:
+
+ Thinkpad x201
+
endchoice
source "src/mainboard/lenovo/x60/Kconfig"
source "src/mainboard/lenovo/t60/Kconfig"
+source "src/mainboard/lenovo/x201/Kconfig"
config MAINBOARD_VENDOR
string
diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig
new file mode 100644
index 0000000..a48cc0e
--- /dev/null
+++ b/src/mainboard/lenovo/x201/Kconfig
@@ -0,0 +1,59 @@
+if BOARD_LENOVO_X201
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_INTEL_MODEL_2065X
+ select NORTHBRIDGE_INTEL_NEHALEM
+ select SOUTHBRIDGE_INTEL_IBEXPEAK
+ select SOUTHBRIDGE_RICOH_RL5C476
+ select SUPERIO_NSC_PC87382
+ select SUPERIO_NSC_PC87392
+ select EC_LENOVO_PMH7
+ select EC_LENOVO_H8
+ select DRIVERS_ICS_954309
+ select HAVE_OPTION_TABLE
+ select HAVE_PIRQ_TABLE
+ select HAVE_MP_TABLE
+ select MMCONF_SUPPORT
+ select GFXUMA
+ select BOARD_ROMSIZE_KB_8192
+ select CHANNEL_XOR_RANDOMIZATION
+ select HAVE_ACPI_TABLES
+ select HAVE_ACPI_RESUME
+ select UDELAY_TSC
+ select EARLY_CBMEM_INIT
+
+config MAINBOARD_DIR
+ string
+ default lenovo/x201
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "3626EN1"
+
+config MAINBOARD_VERSION
+ string
+ default "ThinkPad X201"
+
+config MAINBOARD_VENDOR
+ string
+ default "LENOVO"
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xe0000000
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAX_CPUS
+ int
+ default 4
+
+config CPU_ADDR_BITS
+ int
+ default 36
+
+endif
diff --git a/src/mainboard/lenovo/x201/Makefile.inc b/src/mainboard/lenovo/x201/Makefile.inc
new file mode 100644
index 0000000..1ed3999
--- /dev/null
+++ b/src/mainboard/lenovo/x201/Makefile.inc
@@ -0,0 +1,23 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c
+romstage-y += dock.c
+ramstage-y += dock.c
+
diff --git a/src/mainboard/lenovo/x201/acpi/dock.asl b/src/mainboard/lenovo/x201/acpi/dock.asl
new file mode 100644
index 0000000..732ee90
--- /dev/null
+++ b/src/mainboard/lenovo/x201/acpi/dock.asl
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "smi.h"
+
+Scope (\_SB)
+{
+ Device(DOCK)
+ {
+ Name(_HID, "ACPI0003")
+ Name(_UID, 0x00)
+ Name(_PCL, Package() { \_SB } )
+
+ Method(_DCK, 1, NotSerialized)
+ {
+ if (Arg0) {
+ /* connect dock */
+ Store (1, \_SB.PCI0.LPCB.EC.DKR1)
+ Store (1, \_SB.PCI0.LPCB.EC.DKR2)
+ Store (1, \_SB.PCI0.LPCB.EC.DKR3)
+ } else {
+ /* disconnect dock */
+ Store (0, \_SB.PCI0.LPCB.EC.DKR1)
+ Store (0, \_SB.PCI0.LPCB.EC.DKR2)
+ Store (0, \_SB.PCI0.LPCB.EC.DKR3)
+ }
+ Xor(Arg0, \_SB.PCI0.LPCB.EC.DKR1, Local0)
+ Return (Local0)
+ }
+
+ Method(_STA, 0, NotSerialized)
+ {
+ Return (\_SB.PCI0.LPCB.EC.DKR1)
+ }
+ }
+}
+
+Scope(\_SB.PCI0.LPCB.EC)
+{
+ Method(_Q18, 0, NotSerialized)
+ {
+ Notify(\_SB.DOCK, 3)
+ }
+
+ Method(_Q45, 0, NotSerialized)
+ {
+ Notify(\_SB.DOCK, 3)
+ }
+
+ Method(_Q50, 0, NotSerialized)
+ {
+ Notify(\_SB.DOCK, 3)
+ }
+
+ Method(_Q58, 0, NotSerialized)
+ {
+ Notify(\_SB.DOCK, 0)
+ }
+
+ Method(_Q37, 0, NotSerialized)
+ {
+ Notify(\_SB.DOCK, 0)
+ }
+}
diff --git a/src/mainboard/lenovo/x201/acpi/ec.asl b/src/mainboard/lenovo/x201/acpi/ec.asl
new file mode 100644
index 0000000..4b3e72c
--- /dev/null
+++ b/src/mainboard/lenovo/x201/acpi/ec.asl
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <ec/lenovo/h8/acpi/ec.asl>
+
+Scope(\_SB.PCI0.LPCB.EC)
+{
+}
diff --git a/src/mainboard/lenovo/x201/acpi/gpe.asl b/src/mainboard/lenovo/x201/acpi/gpe.asl
new file mode 100644
index 0000000..b160b50
--- /dev/null
+++ b/src/mainboard/lenovo/x201/acpi/gpe.asl
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "smi.h"
+Scope (\_GPE)
+{
+ Method(_L18, 0, NotSerialized)
+ {
+ /* Read EC register to clear wake status */
+ Store(\_SB.PCI0.LPCB.EC.WAKE, Local0)
+ }
+}
diff --git a/src/mainboard/lenovo/x201/acpi/ich7_pci_irqs.asl b/src/mainboard/lenovo/x201/acpi/ich7_pci_irqs.asl
new file mode 100644
index 0000000..548996c
--- /dev/null
+++ b/src/mainboard/lenovo/x201/acpi/ich7_pci_irqs.asl
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the
+ * 0:1e.0 PCI bridge of the ICH7
+ */
+
+If (PICM) {
+ Return (Package() {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
+ Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 },
+ Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x15 },
+ Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x16 },
+ Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 }
+ })
+ } Else {
+ Return (Package() {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKA, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKC, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKA, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LPCB.LNKF, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LPCB.LNKG, 0x00 },
+ Package (0x04) { 0x0008FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 }
+ })
+}
diff --git a/src/mainboard/lenovo/x201/acpi/mainboard.asl b/src/mainboard/lenovo/x201/acpi/mainboard.asl
new file mode 100644
index 0000000..e69de29
diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl
new file mode 100644
index 0000000..2bf3a2b
--- /dev/null
+++ b/src/mainboard/lenovo/x201/acpi/platform.asl
@@ -0,0 +1,170 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* These come from the dynamically created CPU SSDT */
+External(PDC0)
+External(PDC1)
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+ APMC, 8, // APM command
+ APMS, 8 // APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+ DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+ Store (Arg0, SMIF) // SMI Function
+ Store (0, TRP0) // Generate trap
+ Return (SMIF) // Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+ // Remember the OS' IRQ routing choice.
+ Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+ \_SB.PCI0.LPCB.EC.MUTE(1)
+ \_SB.PCI0.LPCB.EC.USBP(0)
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ // CPU specific part
+
+ // Notify PCI Express slots in case a card
+ // was inserted while a sleep state was active.
+
+ // Are we going to S3?
+ If (LEqual(Arg0, 3)) {
+ // ..
+ }
+
+ // Are we going to S4?
+ If (LEqual(Arg0, 4)) {
+ // ..
+ }
+
+ // TODO: Windows XP SP2 P-State restore
+
+ Return(Package(){0,0})
+}
+
+/* System Bus */
+
+Scope(\_SB)
+{
+ /* This method is placed on the top level, so we can make sure it's the
+ * first executed _INI method.
+ */
+ Method(_INI, 0)
+ {
+ /* The DTS data in NVS is probably not up to date.
+ * Update temperature values and make sure AP thermal
+ * interrupts can happen
+ */
+
+ // TRAP(71) // TODO
+
+ /* Determine the Operating System and save the value in OSYS.
+ * We have to do this in order to be able to work around
+ * certain windows bugs.
+ *
+ * OSYS value | Operating System
+ * -----------+------------------
+ * 2000 | Windows 2000
+ * 2001 | Windows XP(+SP1)
+ * 2002 | Windows XP SP2
+ * 2006 | Windows Vista
+ * ???? | Windows 7
+ */
+
+ /* Let's assume we're running at least Windows 2000 */
+ Store (2000, OSYS)
+
+ If (CondRefOf(_OSI, Local0)) {
+ /* Linux answers _OSI with "True" for a couple of
+ * Windows version queries. But unlike Windows it
+ * needs a Video repost, so let's determine whether
+ * we're running Linux.
+ */
+/*
+ If (_OSI("Linux")) {
+ Store (1, LINX)
+ }*/
+
+ If (_OSI("Windows 2001")) {
+ Store (2001, OSYS)
+ }
+
+ If (_OSI("Windows 2001 SP1")) {
+ Store (2001, OSYS)
+ }
+
+ If (_OSI("Windows 2001 SP2")) {
+ Store (2002, OSYS)
+ }
+
+ If (_OSI("Windows 2006")) {
+ Store (2006, OSYS)
+ }
+ }
+
+ /* And the OS workarounds start right after we know what we're
+ * running: Windows XP SP1 needs to have C-State coordination
+ * enabled in SMM.
+ */
+ If (LAnd(LEqual(OSYS, 2001), MPEN)) {
+ // TRAP(61) // TODO
+ }
+
+ /* SMM power state and C4-on-C3 settings need to be updated */
+ // TRAP(43) // TODO
+ }
+}
+
diff --git a/src/mainboard/lenovo/x201/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/x201/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000..1fdef91
--- /dev/null
+++ b/src/mainboard/lenovo/x201/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the
+ * i945
+ */
+
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+ If (PICM) {
+ Return (Package() {
+ Package() { 0x0001ffff, 0, 0, 0x10 },
+ Package() { 0x0002ffff, 0, 0, 0x10 }, // VGA
+ Package() { 0x0003ffff, 0, 0, 0x10 },
+ Package() { 0x0016ffff, 0, 0, 0x10 }, // ME
+ Package() { 0x0016ffff, 1, 0, 0x11 }, // ME
+ Package() { 0x0016ffff, 2, 0, 0x12 }, // ME
+ Package() { 0x0016ffff, 3, 0, 0x13 }, // ME
+ Package() { 0x0019ffff, 0, 0, 0x14 }, // Ethernet
+ Package() { 0x001affff, 0, 0, 0x14 }, // USB
+ Package() { 0x001affff, 1, 0, 0x15 }, // USB
+ Package() { 0x001affff, 2, 0, 0x16 }, // USB
+ Package() { 0x001affff, 3, 0, 0x17 }, // USB
+ Package() { 0x001bffff, 1, 0, 0x11 }, // Audio
+ Package() { 0x001cffff, 0, 0, 0x14 }, // PCI bridge
+ Package() { 0x001cffff, 1, 0, 0x15 }, // PCI bridge
+ Package() { 0x001cffff, 2, 0, 0x16 }, // PCI bridge
+ Package() { 0x001cffff, 3, 0, 0x17 }, // PCI bridge
+ Package() { 0x001dffff, 0, 0, 0x10 }, // USB
+ Package() { 0x001dffff, 1, 0, 0x11 }, // USB
+ Package() { 0x001dffff, 2, 0, 0x12 }, // USB
+ Package() { 0x001dffff, 3, 0, 0x13 }, // USB
+ Package() { 0x001fffff, 0, 0, 0x17 }, // LPC
+ Package() { 0x001fffff, 1, 0, 0x10 }, // IDE
+ Package() { 0x001fffff, 2, 0, 0x11 }, // SATA
+ Package() { 0x001fffff, 3, 0, 0x13 } // SMBUS
+ })
+ } Else {
+ Return (Package() {
+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // VGA
+ Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // ME
+ Package() { 0x0016ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // ME
+ Package() { 0x0016ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // ME
+ Package() { 0x0016ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // ME
+ Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // Ethernet
+ Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // USB
+ Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // USB
+ Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // USB
+ Package() { 0x001affff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // USB
+ Package() { 0x001bffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // Audio
+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, // PCI
+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, // PCI
+ Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKG, 0 }, // PCI
+ Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKH, 0 }, // PCI
+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, // USB
+ Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, // USB
+ Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, // USB
+ Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, // USB
+ Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, // LPC
+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, // IDE
+ Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, // SATA
+ Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } // SMBus
+ })
+ }
+}
diff --git a/src/mainboard/lenovo/x201/acpi/superio.asl b/src/mainboard/lenovo/x201/acpi/superio.asl
new file mode 100644
index 0000000..e69de29
diff --git a/src/mainboard/lenovo/x201/acpi/video.asl b/src/mainboard/lenovo/x201/acpi/video.asl
new file mode 100644
index 0000000..95b7008
--- /dev/null
+++ b/src/mainboard/lenovo/x201/acpi/video.asl
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "smi.h"
+
+Scope (\_SB.PCI0.GFX0)
+{
+ Device (LCD0)
+ {
+ Name (_ADR, 0x0400)
+
+ Name (BRIG, Package (0x12)
+ {
+ 0xb2,
+ 0xb2,
+ 0x3,
+ 0x7,
+ 0x9,
+ 0xd,
+ 0x11,
+ 0x16,
+ 0x1a,
+ 0x21,
+ 0x27,
+ 0x2e,
+ 0x37,
+ 0x3f,
+ 0x4e,
+ 0x61,
+ 0x81,
+ 0xb2,
+ })
+
+
+ Method (_BCL, 0, NotSerialized)
+ {
+ Return (BRIG)
+ }
+
+ Method (_BCM, 1, NotSerialized)
+ {
+ Store (ShiftLeft (Arg0, 3), ^^BCLV)
+ }
+ Method (_BQC, 0, NotSerialized)
+ {
+ Store (^^BCLV, Local0)
+ ShiftRight (Local0, 3, Local0)
+ Return (Local0)
+ }
+ }
+}
diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c
new file mode 100644
index 0000000..665d7be
--- /dev/null
+++ b/src/mainboard/lenovo/x201/acpi_tables.c
@@ -0,0 +1,275 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+extern const unsigned char AmlCode[];
+#if CONFIG_HAVE_ACPI_SLIC
+unsigned long acpi_create_slic(unsigned long current);
+#endif
+
+#include "southbridge/intel/i82801gx/nvs.h"
+static void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ memset((void *)gnvs, 0, sizeof(*gnvs));
+ gnvs->apic = 1;
+ gnvs->mpen = 1; /* Enable Multi Processing */
+
+ /* Enable both COM ports */
+ gnvs->cmap = 0x01;
+ gnvs->cmbp = 0x01;
+
+ /* IGD Displays */
+ gnvs->ndid = 3;
+ gnvs->did[0] = 0x80000100;
+ gnvs->did[1] = 0x80000240;
+ gnvs->did[2] = 0x80000410;
+ gnvs->did[3] = 0x80000410;
+ gnvs->did[4] = 0x00000005;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 1, IO_APIC_ADDR, 0);
+
+ /* INT_SRC_OVR */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, MP_IRQ_POLARITY_DEFAULT | MP_IRQ_TRIGGER_DEFAULT);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL);
+
+ /* LAPIC_NMI */
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
+ current, 0,
+ MP_IRQ_POLARITY_HIGH |
+ MP_IRQ_TRIGGER_EDGE, 0x01);
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
+ current, 1, MP_IRQ_POLARITY_HIGH |
+ MP_IRQ_TRIGGER_EDGE, 0x01);
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
+ current, 2, MP_IRQ_POLARITY_HIGH |
+ MP_IRQ_TRIGGER_EDGE, 0x01);
+ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)
+ current, 3, MP_IRQ_POLARITY_HIGH |
+ MP_IRQ_TRIGGER_EDGE, 0x01);
+ return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+ generate_cpu_entries();
+ return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ // Not implemented
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ /* No NUMA, no SRAT */
+ return current;
+}
+
+void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
+
+#define ALIGN_CURRENT current = (ALIGN(current, 16))
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ int i;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ acpi_xsdt_t *xsdt;
+ acpi_hpet_t *hpet;
+ acpi_madt_t *madt;
+ acpi_mcfg_t *mcfg;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+#if CONFIG_HAVE_ACPI_SLIC
+ acpi_header_t *slic;
+#endif
+ acpi_header_t *ssdt;
+ acpi_header_t *dsdt;
+ void *gnvs;
+
+ current = start;
+
+ /* Align ACPI tables to 16byte */
+ ALIGN_CURRENT;
+
+ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ ALIGN_CURRENT;
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+ ALIGN_CURRENT;
+ xsdt = (acpi_xsdt_t *) current;
+ current += sizeof(acpi_xsdt_t);
+ ALIGN_CURRENT;
+
+ /* clear all table memory */
+ memset((void *) start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, xsdt);
+ acpi_write_rsdt(rsdt);
+ acpi_write_xsdt(xsdt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+ printk(BIOS_DEBUG, "ACPI: * HPET\n");
+
+ hpet = (acpi_hpet_t *) current;
+ current += sizeof(acpi_hpet_t);
+ ALIGN_CURRENT;
+ acpi_create_hpet(hpet);
+ acpi_add_table(rsdp, hpet);
+
+ /* If we want to use HPET Timers Linux wants an MADT */
+ printk(BIOS_DEBUG, "ACPI: * MADT\n");
+
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current += madt->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, madt);
+
+ printk(BIOS_DEBUG, "ACPI: * MCFG\n");
+ mcfg = (acpi_mcfg_t *) current;
+ acpi_create_mcfg(mcfg);
+ current += mcfg->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, mcfg);
+
+ printk(BIOS_DEBUG, "ACPI: * FACS\n");
+ facs = (acpi_facs_t *) current;
+ current += sizeof(acpi_facs_t);
+ ALIGN_CURRENT;
+ acpi_create_facs(facs);
+
+ dsdt = (acpi_header_t *) current;
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
+
+ /* Fix up global NVS region for SMI handler. The GNVS region lives
+ * in the (high) table area. The low memory map looks like this:
+ *
+ * 0x00000000 - 0x000003ff Real Mode IVT
+ * 0x00000020 - 0x0000019c Low MP Table (XXX conflict?)
+ * 0x00000400 - 0x000004ff BDA (somewhat unused)
+ * 0x00000500 - 0x0000052f Moved GDT
+ * 0x00000530 - 0x00000b64 coreboot table
+ * 0x0007c000 - 0x0007dfff OS boot sector (unused?)
+ * 0x0007e000 - 0x0007ffff free to use (so no good for acpi+smi)
+ * 0x00080000 - 0x0009fbff usable ram
+ * 0x0009fc00 - 0x0009ffff EBDA (unused?)
+ * 0x000a0000 - 0x000bffff VGA memory
+ * 0x000c0000 - 0x000cffff VGA option rom
+ * 0x000d0000 - 0x000dffff free for other option roms?
+ * 0x000e0000 - 0x000fffff SeaBIOS? (conflict with low tables:)
+ * 0x000f0000 - 0x000f03ff PIRQ table
+ * 0x000f0400 - 0x000f66?? ACPI tables
+ * 0x000f66?? - 0x000f???? DMI tables
+ */
+
+ ALIGN_CURRENT;
+
+ /* Pack GNVS into the ACPI table area */
+ for (i=0; i < dsdt->length; i++) {
+ if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
+ printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08x\n", i, (u32)current);
+ *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+ break;
+ }
+ }
+
+ /* And fill it */
+ acpi_create_gnvs((global_nvs_t *)current);
+
+ /* Keep pointer around */
+ gnvs = (void *)current;
+
+ current += 0x100;
+ ALIGN_CURRENT;
+
+ /* And tell SMI about it */
+ smm_setup_structures(gnvs, NULL, NULL);
+
+ /* We patched up the DSDT, so we need to recalculate the checksum */
+ dsdt->checksum = 0;
+ dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
+ dsdt->length);
+
+#if CONFIG_HAVE_ACPI_SLIC
+ printk(BIOS_DEBUG, "ACPI: * SLIC\n");
+ slic = (acpi_header_t *)current;
+ current += acpi_create_slic(current);
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, slic);
+#endif
+
+ printk(BIOS_DEBUG, "ACPI: * FADT\n");
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+ ALIGN_CURRENT;
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdp, fadt);
+
+ printk(BIOS_DEBUG, "ACPI: * SSDT\n");
+ ssdt = (acpi_header_t *)current;
+ acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR);
+ current += ssdt->length;
+ acpi_add_table(rsdp, ssdt);
+ ALIGN_CURRENT;
+
+ printk(BIOS_DEBUG, "current = %lx\n", current);
+ printk(BIOS_INFO, "ACPI: done.\n");
+
+ /* Enable Dummy DCC ON# for DVI */
+ printk(BIOS_DEBUG, "Laptop handling...\n");
+ outb(inb(0x60f) & ~(1 << 5), 0x60f);
+
+ return current;
+}
diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout
new file mode 100644
index 0000000..bce4fbf
--- /dev/null
+++ b/src/mainboard/lenovo/x201/cmos.layout
@@ -0,0 +1,139 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+# -----------------------------------------------------------------
+# Status Register A
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# Stumpy USB reset workaround disable
+400 8 r 0 stumpy_usb_reset_disable
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+#411 5 r 0 unused
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416 128 r 0 vbnv
+#544 440 r 0 unused
+
+# MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
+
+
diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb
new file mode 100644
index 0000000..0983cc6
--- /dev/null
+++ b/src/mainboard/lenovo/x201/devicetree.cb
@@ -0,0 +1,148 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+## Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+chip northbridge/intel/nehalem
+
+
+ # Enable DisplayPort Hotplug with 6ms pulse
+ register "gpu_dp_d_hotplug" = "0x06"
+
+ # Enable Panel as LVDS and configure power delays
+ register "gpu_panel_port_select" = "0" # LVDS
+ register "gpu_panel_power_cycle_delay" = "3"
+ register "gpu_panel_power_up_delay" = "250"
+ register "gpu_panel_power_down_delay" = "250"
+ register "gpu_panel_power_backlight_on_delay" = "2500"
+ register "gpu_panel_power_backlight_off_delay" = "2500"
+ register "gpu_cpu_backlight" = "0x58d"
+ register "gpu_pch_backlight" = "0x061a061a"
+
+ chip ec/lenovo/pmh7
+ device pnp ff.1 on # dummy
+ end
+ register "backlight_enable" = "0x01"
+ register "dock_event_enable" = "0x01"
+ end
+
+ chip ec/lenovo/h8
+ device pnp ff.2 on # dummy
+ io 0x60 = 0x62
+ io 0x62 = 0x66
+ io 0x64 = 0x1600
+ io 0x66 = 0x1604
+ end
+
+ register "config0" = "0xa6"
+ register "config1" = "0x05"
+ register "config2" = "0xa0"
+ register "config3" = "0x01"
+
+ register "beepmask0" = "0xfe"
+ register "beepmask1" = "0x96"
+
+ register "event2_enable" = "0xff"
+ register "event3_enable" = "0xff"
+ register "event4_enable" = "0xf4"
+ register "event5_enable" = "0x3c"
+ register "event6_enable" = "0x80"
+ register "event7_enable" = "0x01"
+ register "eventc_enable" = "0x3c"
+ register "event8_enable" = "0x01"
+ register "event9_enable" = "0xff"
+ register "eventa_enable" = "0xff"
+ register "eventb_enable" = "0xff"
+ register "eventc_enable" = "0xff"
+ register "eventd_enable" = "0xff"
+
+ register "wlan_enable" = "0x01"
+ register "trackpoint_enable" = "0x03"
+ end
+
+ device cpu_cluster 0 on
+ chip cpu/intel/model_206ax
+ device lapic 0 on end
+ end
+ end
+
+ device domain 0 on
+ device pci 00.0 on # Host bridge
+ subsystemid 0x17aa 0x2193
+ end
+ device pci 02.0 on # VGA controller
+ subsystemid 0x17aa 0x215a
+ end
+ chip southbridge/intel/ibexpeak
+ register "pirqa_routing" = "0x0b"
+ register "pirqb_routing" = "0x0b"
+ register "pirqc_routing" = "0x0b"
+ register "pirqd_routing" = "0x0b"
+ register "pirqe_routing" = "0x0b"
+ register "pirqf_routing" = "0x0b"
+ register "pirqg_routing" = "0x0b"
+ register "pirqh_routing" = "0x0b"
+
+ # GPI routing
+ # 0 No effect (default)
+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+ # 2 SCI (if corresponding GPIO_EN bit is also set)
+ register "gpi1_routing" = "2"
+ register "gpi13_routing" = "2"
+
+ register "sata_ahci" = "0x1"
+ register "sata_port_map" = "0x33"
+
+ register "gpe0_en" = "0x20022046"
+ register "alt_gp_smi_en" = "0x0000"
+
+ device pci 16.2 on # IDE/SATA
+ subsystemid 0x17aa 0x2161
+ end
+
+ device pci 19.0 on # Ethernet
+ subsystemid 0x17aa 0x2153
+ end
+
+ device pci 1a.0 on # USB2 EHCI
+ subsystemid 0x17aa 0x2163
+ end
+
+# register "c4onc3_enable" = "1"
+ device pci 1b.0 on # Audio Controller
+ subsystemid 0x17aa 0x215e
+ end
+ device pci 1d.0 on # USB2 EHCI
+ subsystemid 0x17aa 0x2163
+ end
+ device pci 1f.0 on # PCI-LPC bridge
+ subsystemid 0x17aa 0x2166
+ end
+ device pci 1f.2 on # IDE/SATA
+ subsystemid 0x17aa 0x2168
+ end
+ device pci 1f.3 on # SMBUS
+ subsystemid 0x17aa 0x2167
+ end
+ end
+ chip southbridge/ricoh/rl5c476
+ end
+ end
+end
diff --git a/src/mainboard/lenovo/x201/dock.c b/src/mainboard/lenovo/x201/dock.c
new file mode 100644
index 0000000..ebcb54f
--- /dev/null
+++ b/src/mainboard/lenovo/x201/dock.c
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#if !defined (__PRE_RAM__) && !defined (__SMM__)
+#define PCI_DEV(bus, dev, fn) dev_find_slot (bus, PCI_DEVFN (dev, fn))
+#endif
+#include <delay.h>
+#include "dock.h"
+#include "southbridge/intel/ibexpeak/pch.h"
+#include <ec/acpi/ec.h>
+
+int dock_connect(void)
+{
+ ec_set_bit (0x02, 0);
+ ec_set_bit (0x1a, 0);
+ ec_set_bit (0xfe, 4);
+ return 0;
+}
+
+void dock_disconnect(void)
+{
+ ec_clr_bit (0x02, 0);
+ ec_clr_bit (0x1a, 0);
+ ec_clr_bit (0xfe, 4);
+}
+
+int dock_present(void)
+{
+ u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
+ u8 st = inb(gpiobase + 0x0c);
+ printk (BIOS_DEBUG, "GPIO status is 0x%x\n", st);
+
+ return !((st >> 3) & 1);
+}
+
+int dock_ultrabay_device_present(void)
+{
+ return 0;
+}
diff --git a/src/mainboard/lenovo/x201/dock.h b/src/mainboard/lenovo/x201/dock.h
new file mode 100644
index 0000000..141ae48
--- /dev/null
+++ b/src/mainboard/lenovo/x201/dock.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef THINKPAD_X60_DOCK_H
+#define THINKPAD_X60_DOCK_H
+
+extern int dock_connect(void);
+extern void dock_disconnect(void);
+extern int dock_present(void);
+extern int dlpc_init(void);
+extern int dock_ultrabay_device_present(void);
+#endif
diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl
new file mode 100644
index 0000000..e66c463
--- /dev/null
+++ b/src/mainboard/lenovo/x201/dsdt.asl
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x03, // DSDT revision: ACPI v3.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20090419 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+
+ // global NVS and variables
+ #include <southbridge/intel/ibexpeak/acpi/globalnvs.asl>
+
+ // General Purpose Events
+ #include "acpi/gpe.asl"
+
+ // mainboard specific devices
+ #include "acpi/mainboard.asl"
+
+ #include <cpu/intel/model_206ax/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/calpella/acpi/calpella.asl>
+ #include <southbridge/intel/ibexpeak/acpi/pch.asl>
+ }
+ Device (UNCR)
+ {
+ Name (_BBN, 0xFF)
+ Name (_ADR, 0x00)
+ Name (RID, 0x00)
+ Name (_HID, EisaId ("PNP0A03"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x00FF, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0001, // Length
+ ,, )
+ })
+ Device (SAD)
+ {
+ Name (_ADR, 0x01)
+ Name (RID, 0x00)
+ OperationRegion (SADC, PCI_Config, 0x00, 0x0100)
+ Field (SADC, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x40),
+ PAM0, 8,
+ PAM1, 8,
+ PAM2, 8,
+ PAM3, 8,
+ PAM4, 8,
+ PAM5, 8,
+ PAM6, 8
+ }
+ }
+ }
+ }
+
+ #include "acpi/video.asl"
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
+
+ // Dock support code
+ #include "acpi/dock.asl"
+}
diff --git a/src/mainboard/lenovo/x201/fadt.c b/src/mainboard/lenovo/x201/fadt.c
new file mode 100644
index 0000000..8fbd0ac
--- /dev/null
+++ b/src/mainboard/lenovo/x201/fadt.c
@@ -0,0 +1,159 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+#include <cpu/x86/smm.h>
+
+/* FIXME: This needs to go into a separate .h file
+ * to be included by the ich7 smi handler, ich7 smi init
+ * code and the mainboard fadt.
+ */
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+ u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = 3;
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+ header->asl_compiler_revision = 0;
+
+ fadt->firmware_ctrl = (unsigned long) facs;
+ fadt->dsdt = (unsigned long) dsdt;
+ fadt->model = 0x00;
+ fadt->preferred_pm_profile = PM_MOBILE;
+ fadt->sci_int = 0x9;
+ fadt->smi_cmd = APM_CNT;
+ fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+ fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = APM_CNT_PST_CONTROL;
+
+ fadt->pm1a_evt_blk = pmbase;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + 0x4;
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = pmbase + 0x50;
+ fadt->pm_tmr_blk = pmbase + 0x8;
+ fadt->gpe0_blk = pmbase + 0x20;
+ fadt->gpe1_blk = 0;
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 1;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 0x10;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+ fadt->cst_cnt = APM_CNT_CST_CONTROL;
+ fadt->p_lvl2_lat = 1;
+ fadt->p_lvl3_lat = 0x23;
+ fadt->flush_size = 0;
+ fadt->flush_stride = 0;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 3;
+ fadt->day_alrm = 0xd;
+ fadt->mon_alrm = 0x00;
+ fadt->century = 0x32;
+ fadt->iapc_boot_arch = 0x00;
+ fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+ ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE |
+ ACPI_FADT_DOCKING_SUPPORTED;
+
+ fadt->reset_reg.space_id = 0;
+ fadt->reset_reg.bit_width = 0;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.resv = 0;
+ fadt->reset_reg.addrl = 0x0;
+ fadt->reset_reg.addrh = 0x0;
+
+ fadt->reset_value = 0;
+ fadt->x_firmware_ctl_l = (unsigned long)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = 32;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.addrl = pmbase;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 0;
+ fadt->x_pm1b_evt_blk.bit_width = 0;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.resv = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = 32;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 0;
+ fadt->x_pm1b_cnt_blk.bit_width = 0;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.resv = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.resv = 0;
+ fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = 128;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.resv = 0;
+ fadt->x_gpe0_blk.addrl = pmbase + 0x20;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = 0;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.resv = 0;
+ fadt->x_gpe1_blk.addrl = 0x0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum =
+ acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/lenovo/x201/irq_tables.c b/src/mainboard/lenovo/x201/irq_tables.c
new file mode 100644
index 0000000..f1ab06d
--- /dev/null
+++ b/src/mainboard/lenovo/x201/irq_tables.c
@@ -0,0 +1,62 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+static const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32 + 16 * 15, /* Max. number of devices on the bus */
+ 0x00, /* Interrupt router bus */
+ (0x1f << 3) | 0x0, /* Interrupt router dev */
+ 0, /* IRQs devoted exclusively to PCI usage */
+ 0x8086, /* Vendor */
+ 0x122e, /* Device */
+ 0, /* Miniport */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0xf5, /* Checksum (has to be set to some value that
+ * would give 0 after the sum of all bytes
+ * for this structure (including checksum).
+ */
+ {
+ /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00, (0x00 << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* Host 0:00.0 */
+ {0x00, (0x02 << 3) | 0x0, {{0x60, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* VGA 0:02.0 */
+ {0x00, (0x1b << 3) | 0x0, {{0x00, 0xdef8}, {0x61, 0x1cf8}, {0x00, 0xdef8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* HD Audio 0:1b.0 */
+ {0x00, (0x1c << 3) | 0x0, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.0 */
+ {0x00, (0x1c << 3) | 0x1, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.1 */
+ {0x00, (0x1c << 3) | 0x2, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.2 */
+ {0x00, (0x1c << 3) | 0x3, {{0x68, 0x1cf8}, {0x69, 0x1cf8}, {0x6a, 0x1cf8}, {0x6b, 0x1cf8}}, 0x0, 0x0}, /* PCIe 0:1c.3 */
+ {0x00, (0x1d << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.0 */
+ {0x00, (0x1d << 3) | 0x1, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.1 */
+ {0x00, (0x1d << 3) | 0x2, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.2 */
+ {0x00, (0x1d << 3) | 0x3, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* USB 0:1d.3 */
+ {0x00, (0x1e << 3) | 0x0, {{0x60, 0x1cf8}, {0x61, 0x1cf8}, {0x62, 0x1cf8}, {0x63, 0x1cf8}}, 0x0, 0x0}, /* PCI 0:1e.0 */
+ {0x00, (0x1f << 3) | 0x0, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* LPC 0:1f.0 */
+ {0x00, (0x1f << 3) | 0x1, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* IDE 0:1f.1 */
+ {0x00, (0x1f << 3) | 0x2, {{0x6b, 0x1cf8}, {0x60, 0x1cf8}, {0x60, 0x1cf8}, {0x00, 0xdef8}}, 0x0, 0x0}, /* SATA 0:1f.2 */
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr, &intel_irq_routing_table);
+}
diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c
new file mode 100644
index 0000000..56cdb85
--- /dev/null
+++ b/src/mainboard/lenovo/x201/mainboard.c
@@ -0,0 +1,297 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/io.h>
+#include <delay.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <ec/lenovo/pmh7/pmh7.h>
+#include <ec/acpi/ec.h>
+#include <ec/lenovo/h8/h8.h>
+#include <northbridge/intel/calpella/calpella.h>
+#include <southbridge/intel/ibexpeak/pch.h>
+
+#include <pc80/mc146818rtc.h>
+#include "dock.h"
+#include <arch/x86/include/arch/acpigen.h>
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+#include <x86emu/regs.h>
+#include <arch/interrupt.h>
+#endif
+#include <pc80/keyboard.h>
+#include <cpu/x86/lapic.h>
+#include <device/pci.h>
+#include <smbios.h>
+
+static acpi_cstate_t cst_entries[] = {
+ { 1, 1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } },
+ { 2, 1, 500, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 } },
+ { 2, 17, 250, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } },
+};
+
+int get_cst_entries(acpi_cstate_t **entries)
+{
+ *entries = cst_entries;
+ return ARRAY_SIZE(cst_entries);
+}
+
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+
+static int int15_handler(void)
+{
+ switch((X86_EAX & 0xffff)) {
+ /* Get boot display. */
+ case 0x5f35:
+ X86_EAX = 0x5f;
+#if 0
+ /* DisplayPort */
+ X86_ECX = 0x4;
+ /* VGA */
+ X86_ECX = 0x1;
+#endif
+ /* LCD */
+ X86_ECX = 0x8;
+
+ return 1;
+ case 0x5f40:
+ X86_EAX = 0x5f;
+ X86_ECX = 0x2;
+ return 1;
+ default:
+ printk(BIOS_WARNING, "Unknown INT15 function %04x!\n",
+ X86_EAX & 0xffff);
+ return 0;
+ }
+}
+#endif
+
+static void rcba_config(void)
+{
+#if 0
+#if 0
+ u32 reg32;
+
+ /*
+ * GFX INTA -> PIRQA (MSI)
+ * D28IP_P1IP WLAN INTA -> PIRQB
+ * D28IP_P4IP ETH0 INTB -> PIRQC (MSI)
+ * D29IP_E1P EHCI1 INTA -> PIRQD
+ * D26IP_E2P EHCI2 INTA -> PIRQB
+ * D31IP_SIP SATA INTA -> PIRQA (MSI)
+ * D31IP_SMIP SMBUS INTC -> PIRQH
+ * D31IP_TTIP THRT INTB -> PIRQG
+ * D27IP_ZIP HDA INTA -> PIRQG (MSI)
+ *
+ * LIGHTSENSOR -> PIRQE (Edge Triggered)
+ * TRACKPAD -> PIRQF (Edge Triggered)
+ */
+ /* Device interrupt pin register (board specific) */
+ RCBA32(D31IP) = (INTD << D31IP_TTIP) | (INTC << D31IP_SIP2) |
+ (INTD << D31IP_UNKIP) | (INTA << D31IP_SMIP) | (INTB << D31IP_SIP);
+ RCBA32(D30IP) = (NOINT << D30IP_PIP);
+ RCBA32(D29IP) = 0x40043214;//(INTA << D29IP_E1P);
+ RCBA32(D28IP) = 0x00014321;//(INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
+ // (INTB << D28IP_P4IP);
+ RCBA32(D27IP) = 0x00000002;//(INTA << D27IP_ZIP);
+ RCBA32(D26IP) = 0x30003214;//(INTA << D26IP_E2P);
+ RCBA32(D25IP) = (NOINT << D25IP_LIP);
+ RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+#endif
+ RCBA32 (0x30fc) = 0x00000000;
+ (void) RCBA32 (0x30fc);
+ RCBA32 (0x3100) = 0x04341200;
+ (void) RCBA32 (0x3100);
+ RCBA32 (0x3104) = 0x00000000;
+ (void) RCBA32 (0x3104);
+ RCBA32 (0x3108) = 0x40043214;
+ (void) RCBA32 (0x3108);
+ RCBA32 (0x310c) = 0x00014321;
+ (void) RCBA32 (0x310c);
+ RCBA32 (0x3110) = 0x00000002;
+ (void) RCBA32 (0x3110);
+ RCBA32 (0x3114) = 0x30003214;
+ (void) RCBA32 (0x3114);
+ RCBA32 (0x311c) = 0x00000002;
+ (void) RCBA32 (0x311c);
+ RCBA32 (0x3120) = 0x00000000;
+ (void) RCBA32 (0x3120);
+ RCBA32 (0x3124) = 0x00002321;
+ (void) RCBA32 (0x3124);
+ RCBA32 (0x313c) = 0x00000000;
+ (void) RCBA32 (0x313c);
+ RCBA32 (0x3140) = 0x00003107;
+ (void) RCBA32 (0x3140);
+ RCBA32 (0x3144) = 0x76543210;
+ (void) RCBA32 (0x3144);
+ RCBA32 (0x3148) = 0x00000010;
+ (void) RCBA32 (0x3148);
+ RCBA32 (0x314c) = 0x00007654;
+ (void) RCBA32 (0x314c);
+ RCBA32 (0x3150) = 0x00000004;
+ (void) RCBA32 (0x3150);
+ RCBA32 (0x3158) = 0x00000000;
+ (void) RCBA32 (0x3158);
+ RCBA32 (0x315c) = 0x00003210;
+ (void) RCBA32 (0x315c);
+ RCBA32 (0x31fc) = 0x03000000;
+ (void) RCBA32 (0x31fc);
+
+#if 0
+ /* Device interrupt route registers */
+ DIR_ROUTE(D31IR, PIRQA, PIRQG, PIRQH, PIRQB);
+ DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQG, PIRQH);
+ DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
+ DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB);
+ DIR_ROUTE(D26IR, PIRQB, PIRQC, PIRQD, PIRQA);
+ DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+ DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+ /* Enable IOAPIC (generic) */
+ RCBA16(OIC) = 0x0100;
+ /* PCH BWG says to read back the IOAPIC enable register */
+ (void) RCBA16(OIC);
+ /* Disable unused devices (board specific) */
+ reg32 = RCBA32(FD);
+ reg32 |= PCH_DISABLE_ALWAYS;
+ RCBA32(FD) = reg32;
+#endif
+
+#if 0
+ RCBA32 (0x3418) = 0x16e61fe1;
+ (void) RCBA32 (0x3418);
+#endif
+#endif
+}
+
+const char *smbios_mainboard_version(void)
+{
+ return "Lenovo X201";
+}
+
+static void mainboard_enable(device_t dev)
+{
+ device_t dev0;
+ u8 defaults_loaded = 0;
+ u16 pmbase;
+
+ printk(BIOS_SPEW, "starting SPI configure\n");
+
+ /* Configure SPI. */
+ RCBA32 (0x3800) = 0x07ff0500;
+ RCBA32 (0x3804) = 0x3f046008;
+ RCBA32 (0x3808) = 0x0058efc0;
+ RCBA32 (0x384c) = 0x92000000;
+ RCBA32 (0x3850) = 0x00000a0b;
+ RCBA32 (0x3858) = 0x07ff0500;
+ RCBA32 (0x385c) = 0x04ff0003;
+ RCBA32 (0x3860) = 0x00020001;
+ RCBA32 (0x3864) = 0x00000fff;
+ RCBA32 (0x3874) = 0x9fff07d0;
+ RCBA32 (0x3890) = 0xf8400000;
+ RCBA32 (0x3894) = 0x143b5006;
+ RCBA32 (0x3898) = 0x05200302;
+ RCBA32 (0x389c) = 0x0601209f;
+ RCBA32 (0x38b0) = 0x00000004;
+ RCBA32 (0x38b4) = 0x03040002;
+ RCBA32 (0x38c0) = 0x00000007;
+ RCBA32 (0x38c4) = 0x00802005;
+ RCBA32 (0x38c8) = 0x00002005;
+ RCBA32 (0x3804) = 0x3f04e008;
+
+ printk(BIOS_SPEW, "SPI configured\n");
+
+ pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
+ PMBASE) & 0xff80;
+
+ printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
+
+ outl(0, pmbase + SMI_EN);
+
+ printk(BIOS_ERR, " smi_en = 0x%08x\n", inl(pmbase + SMI_EN));
+
+ enable_lapic();
+ pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE, DEFAULT_GPIOBASE|1);
+ pci_write_config8(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_CNTL, 0x10);
+
+ rcba_config();
+
+#ifdef DISABLED
+ ec_clr_bit(0x03, 2);
+
+ if (inb(0x164c) & 0x08) {
+ ec_set_bit(0x03, 2);
+ ec_write(0x0c, 0x88);
+ }
+#endif
+ /* If we're resuming from suspend, blink suspend LED */
+ dev0 = dev_find_slot(0, PCI_DEVFN(0,0));
+ if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC)
+ ec_write(0x0c, 0xc7);
+
+#ifdef DISABLED
+ idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1));
+ if (idedev && idedev->chip_info && dock_ultrabay_device_present()) {
+ struct southbridge_intel_i82801gx_config *config = idedev->chip_info;
+ config->ide_enable_primary = 1;
+ /* enable Ultrabay power */
+ outb(inb(0x1628) | 0x01, 0x1628);
+ ec_write(0x0c, 0x84);
+ } else {
+ /* disable Ultrabay power */
+ outb(inb(0x1628) & ~0x01, 0x1628);
+ ec_write(0x0c, 0x04);
+ }
+#endif
+
+ if (get_option(&defaults_loaded, "cmos_defaults_loaded") < 0) {
+ printk(BIOS_INFO, "failed to get cmos_defaults_loaded");
+ defaults_loaded = 0;
+ }
+
+ if (!defaults_loaded) {
+ printk(BIOS_INFO, "Restoring CMOS defaults\n");
+ set_option("tft_brightness", &(u8[]){ 0xff });
+ set_option("volume", &(u8[]){ 0x03 });
+ /* set baudrate to 115200 baud */
+ set_option("baud_rate", &(u8[]){ 0x00 });
+ /* set default debug_level (DEFAULT_CONSOLE_LOGLEVEL starts at 1) */
+ set_option("debug_level", &(u8[]) { CONFIG_DEFAULT_CONSOLE_LOGLEVEL+1 });
+ set_option("cmos_defaults_loaded", &(u8[]){ 0x01 });
+ }
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+ /* Install custom int15 handler for VGA OPROM */
+ mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+
+ /* This sneaked in here, because X201 SuperIO chip isn't really
+ connected to anything and hence we don't init it.
+ */
+ pc_keyboard_init(0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
+
diff --git a/src/mainboard/lenovo/x201/mptable.c b/src/mainboard/lenovo/x201/mptable.c
new file mode 100644
index 0000000..a83a3a2
--- /dev/null
+++ b/src/mainboard/lenovo/x201/mptable.c
@@ -0,0 +1,61 @@
+/* generated by MPTable, version 2.0.15*/
+/* as modified by RGM for coreboot */
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+
+#define INTA 0x00
+#define INTB 0x01
+#define INTC 0x02
+#define INTD 0x03
+
+static void *smp_write_config_table(void *v)
+{
+ struct mp_config_table *mc;
+ int isa_bus;
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+
+ mptable_init(mc, LOCAL_APIC_ADDR);
+
+ smp_write_processors(mc);
+
+ mptable_write_buses(mc, NULL, &isa_bus);
+ /* I/O APICs: APIC ID Version State Address */
+ smp_write_ioapic(mc, 0x2, 0x20, 0xfec00000);
+
+ mptable_add_isa_interrupts(mc, isa_bus, 0x2, 0);
+
+ /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x0, 0x2, 0x0);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x1, 0x2, 0x1);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x0, 0x2, 0x2);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x3, 0x2, 0x3);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x4, 0x2, 0x4);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x5, 0x2, 0x5);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x6, 0x2, 0x6);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x7, 0x2, 0x7);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x8, 0x2, 0x8);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x9, 0x2, 0x9);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xa, 0x2, 0xa);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xb, 0x2, 0xb);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xc, 0x2, 0xc);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xd, 0x2, 0xd);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xe, 0x2, 0xe);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xf, 0x2, 0xf);
+ /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x0, MP_APIC_ALL, 0x0);
+ smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x0, MP_APIC_ALL, 0x1);
+
+ return mptable_finalize(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr, 0);
+ return (unsigned long)smp_write_config_table(v);
+}
diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
new file mode 100644
index 0000000..baf8e71
--- /dev/null
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -0,0 +1,985 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// __PRE_RAM__ means: use "unsigned" for device, not a struct.
+
+#include <stdint.h>
+#include <string.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/car.h>
+#include <lib.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <cpu/x86/bist.h>
+#include <ec/acpi/ec.h>
+#include <delay.h>
+#include <timestamp.h>
+
+#include "dock.h"
+#include "southbridge/intel/ibexpeak/pch.h"
+#include "southbridge/intel/ibexpeak/gpio.h"
+#include "northbridge/intel/calpella/calpella.h"
+
+#include "northbridge/intel/calpella/calpella.h"
+#include "northbridge/intel/calpella/raminit.h"
+#include "southbridge/intel/ibexpeak/pch.h"
+#include "southbridge/intel/ibexpeak/gpio.h"
+#include "southbridge/intel/ibexpeak/me.h"
+
+//#define SERIALICE 1
+
+static void pch_enable_lpc(void)
+{
+ /* Parrot EC Decode Range Port60/64, Port62/66 */
+ /* Enable EC, PS/2 Keyboard/Mouse */
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | COMA_LPC_EN);
+
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x1c1681);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, (0x68 & ~3) | 0x00040001);
+
+ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
+}
+
+
+static void rcba_config(void)
+{
+ static const u32 rcba_dump3[] = {
+ /* 30fc */ 0x00000000,
+ /* 3100 */ 0x04341200, 0x00000000, 0x40043214, 0x00014321,
+ /* 3110 */ 0x00000002, 0x30003214, 0x00000001, 0x00000002,
+ /* 3120 */ 0x00000000, 0x00002321, 0x00000000, 0x00000000,
+ /* 3130 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3140 */ 0x00003107, 0x76543210, 0x00000010, 0x00007654,
+ /* 3150 */ 0x00000004, 0x00000000, 0x00000000, 0x00003210,
+ /* 3160 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3170 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 31a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 31b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 31c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 31d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 31e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 31f0 */ 0x00000000, 0x00000000, 0x00000000, 0x03000000,
+ /* 3200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3280 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3290 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 32a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 32b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 32c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 32d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 32e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 32f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3300 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000,
+ /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000,
+ /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3340 */ 0x000fffff, 0x00000000, 0x00000000, 0x00000000,
+ /* 3350 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3370 */ 0x00000000, 0x00000000, 0x7f8fdfff, 0x00000000,
+ /* 3380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 33a0 */ 0x00003900, 0x00000000, 0x00000000, 0x00000000,
+ /* 33b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 33c0 */ 0x00010000, 0x00000000, 0x00000000, 0x0001004b,
+ /* 33d0 */ 0x06000008, 0x00010000, 0x00000000, 0x00000000,
+ /* 33e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 33f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000,
+ /* 3410 */ 0x00000c61, 0x00000000, 0x16e61fe1, 0xbf4f001f,
+ /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xdeaddeed, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x20000557, 0x2000055f, 0x2000074b, 0x2000074b,
+ 0x20000557, 0x2000014b, 0x2000074b, 0x2000074b,
+ 0x2000074b, 0x2000074b, 0x2000055f, 0x2000055f,
+ 0x20000557, 0x2000055f, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000001, 0x000026a3, 0x00040002, 0x01000052,
+ 0x02000772, 0x16000f8f, 0x1800ff4f, 0x0001d630,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xfc000201, 0x3c000201, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x0a001f00, 0x00000000, 0x00000000, 0x00000001,
+ 0x00010000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x089c0018, 0x00000000, 0x00000000,
+ 0x11111111, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x4e564d49, 0x00000000, 0x00000000,
+ };
+ unsigned i;
+ for (i = 0; i < sizeof (rcba_dump3) / 4; i++)
+ {
+ RCBA32 (4 * i + 0x30fc) = rcba_dump3[i];
+ (void) RCBA32 (4 * i + 0x30fc);
+ }
+
+#if 0
+ RCBA32 (0x30fc) = 0x00000000;
+ (void) RCBA32 (0x30fc);
+ RCBA32 (0x3100) = 0x04341200;
+ (void) RCBA32 (0x3100);
+ RCBA32 (0x3104) = 0x00000000;
+ (void) RCBA32 (0x3104);
+ RCBA32 (0x3108) = 0x40043214;
+ (void) RCBA32 (0x3108);
+ RCBA32 (0x310c) = 0x00014321;
+ (void) RCBA32 (0x310c);
+ RCBA32 (0x3110) = 0x00000002;
+ (void) RCBA32 (0x3110);
+ RCBA32 (0x3114) = 0x30003214;
+ (void) RCBA32 (0x3114);
+ RCBA32 (0x311c) = 0x00000002;
+ (void) RCBA32 (0x311c);
+ RCBA32 (0x3120) = 0x00000000;
+ (void) RCBA32 (0x3120);
+ RCBA32 (0x3124) = 0x00002321;
+ (void) RCBA32 (0x3124);
+ RCBA32 (0x313c) = 0x00000000;
+ (void) RCBA32 (0x313c);
+ RCBA32 (0x3140) = 0x00003107;
+ (void) RCBA32 (0x3140);
+ RCBA32 (0x3144) = 0x76543210;
+ (void) RCBA32 (0x3144);
+ RCBA32 (0x3148) = 0x00000010;
+ (void) RCBA32 (0x3148);
+ RCBA32 (0x314c) = 0x00007654;
+ (void) RCBA32 (0x314c);
+ RCBA32 (0x3150) = 0x00000004;
+ (void) RCBA32 (0x3150);
+ RCBA32 (0x3158) = 0x00000000;
+ (void) RCBA32 (0x3158);
+ RCBA32 (0x315c) = 0x00003210;
+ (void) RCBA32 (0x315c);
+ RCBA32 (0x31fc) = 0x03000000;
+ (void) RCBA32 (0x31fc);
+#endif
+}
+
+#include <cbmem.h>
+
+#ifdef SERIALICE
+static void
+sio_putc (char c)
+{
+ usbdebug_tx_byte(0, c);
+ usbdebug_tx_flush (0);
+}
+
+static char
+sio_getc (void)
+{
+ return usbdebug_rx_byte(0);
+}
+
+/* SIO helpers */
+
+static void sio_putstring(const char *string)
+{
+ /* Very simple, no %d, %x etc. */
+ while (*string) {
+ if (*string == '\n')
+ sio_putc('\r');
+ sio_putc(*string);
+ string++;
+ }
+}
+
+#define sio_put_nibble(nibble) \
+ if (nibble > 9) \
+ nibble += ('a' - 10); \
+ else \
+ nibble += '0'; \
+ sio_putc(nibble)
+
+static void sio_put8(u8 data)
+{
+ u8 c;
+
+ c = (data >> 4) & 0xf;
+ sio_put_nibble(c);
+
+ c = data & 0xf;
+ sio_put_nibble(c);
+}
+
+static void sio_put16(u16 data)
+{
+ int i;
+ for (i=12; i >= 0; i -= 4) {
+ u8 c = (data >> i) & 0xf;
+ sio_put_nibble(c);
+ }
+}
+
+static void sio_put32(u32 data)
+{
+ int i;
+ for (i=28; i >= 0; i -= 4) {
+ u8 c = (data >> i) & 0xf;
+ sio_put_nibble(c);
+ }
+}
+
+static void sio_put64(u64 data)
+{
+ int i;
+ for (i=60; i >= 0; i -= 4) {
+ u8 c = (data >> i) & 0xf;
+ sio_put_nibble(c);
+ }
+}
+
+typedef struct _u128
+{
+ u64 lo;
+ u64 hi;
+} u128;
+
+static void sio_put128(u128 data)
+{
+ sio_put64 (data.hi);
+ sio_put64 (data.lo);
+}
+
+static u8 sio_get_nibble(void)
+{
+ u8 ret = 0;
+ u8 nibble = sio_getc();
+
+ if (nibble >= '0' && nibble <= '9') {
+ ret = (nibble - '0');
+ } else if (nibble >= 'a' && nibble <= 'f') {
+ ret = (nibble - 'a') + 0xa;
+ } else if (nibble >= 'A' && nibble <= 'F') {
+ ret = (nibble - 'A') + 0xa;
+ } else {
+ sio_putstring("ERROR: parsing number\n");
+ }
+ return ret;
+}
+
+static u8 sio_get8(void)
+{
+ u8 data;
+ data = sio_get_nibble();
+ data = data << 4;
+ data |= sio_get_nibble();
+ return data;
+}
+
+static u16 sio_get16(void)
+{
+ u16 data;
+
+ data = sio_get_nibble();
+ data = data << 4;
+ data |= sio_get_nibble();
+ data = data << 4;
+ data |= sio_get_nibble();
+ data = data << 4;
+ data |= sio_get_nibble();
+
+ return data;
+}
+
+static u32 sio_get32(void)
+{
+ u32 data;
+
+ data = sio_get_nibble();
+ data = data << 4;
+ data |= sio_get_nibble();
+ data = data << 4;
+ data |= sio_get_nibble();
+ data = data << 4;
+ data |= sio_get_nibble();
+ data = data << 4;
+ data |= sio_get_nibble();
+ data = data << 4;
+ data |= sio_get_nibble();
+ data = data << 4;
+ data |= sio_get_nibble();
+ data = data << 4;
+ data |= sio_get_nibble();
+
+ return data;
+}
+
+static u64 sio_get64(void)
+{
+ u64 data = 0;
+ int i;
+
+ for (i = 0; i < 64; i+=4)
+ {
+ data |= sio_get_nibble();
+ data = data << 4;
+ }
+
+ return data;
+}
+
+static u128 sio_get128(void)
+{
+ u128 data;
+ data.hi = sio_get64 ();
+ data.lo = sio_get64 ();
+
+ return data;
+}
+
+static u64
+read64 (u32 addr)
+{
+ u64 ret;
+ u64 stor;
+ asm volatile ("movq %%xmm0, %0\n"
+ "movq (%2), %%xmm0\n"
+ "movq %%xmm0, %1\n"
+ "movq %0, %%xmm0":"+m"(stor),"=m"(ret):"r"(addr));
+
+ return ret;
+}
+
+static void
+write64 (u32 addr, u64 val)
+{
+ u64 stor;
+ asm volatile ("movq %%xmm0, %0\n"
+ "movq %%xmm0, %1\n"
+ "movq (%2), %%xmm0\n"
+ "movq %0, %%xmm0":"+m"(stor):"m"(val),"r"(addr));
+}
+
+static u128
+read128 (u32 addr)
+{
+ u128 ret;
+ u128 stor;
+ asm volatile ("movdqu %%xmm0, %0\n"
+ "movdqa (%2), %%xmm0\n"
+ "movdqu %%xmm0, %1\n"
+ "movdqu %0, %%xmm0":"+m"(stor),"=m"(ret):"r"(addr));
+
+ return ret;
+}
+
+static void
+write128 (u32 addr, u128 val)
+{
+ u128 stor;
+ asm volatile ("movdqu %%xmm0, %0\n"
+ "movdqu %%xmm0, %1\n"
+ "movdqa (%2), %%xmm0\n"
+ "movdqu %0, %%xmm0":"+m"(stor):"m"(val),"r"(addr));
+}
+
+/* Accessor functions */
+
+static void serialice_read_memory(void)
+{
+ u8 width;
+ u32 addr;
+
+ // Format:
+ // *rm00000000.w
+ addr = sio_get32();
+ sio_getc(); // skip .
+ width = sio_getc();
+
+ sio_putc('\r'); sio_putc('\n');
+
+ switch (width) {
+ case 'b': sio_put8(read8(addr)); break;
+ case 'w': sio_put16(read16(addr)); break;
+ case 'l': sio_put32(read32(addr)); break;
+ case 'q': sio_put64(read64(addr)); break;
+ case 'p': sio_put128(read128(addr)); break;
+ }
+}
+
+static void serialice_clflush(void)
+{
+ u32 addr;
+
+ // Format:
+ // *fm00000000
+ addr = sio_get32();
+
+ sio_putc('\r'); sio_putc('\n');
+
+ asm volatile ("clflush (%0)" : : "r" (addr));
+}
+
+static void serialice_write_memory(void)
+{
+ u8 width;
+ u32 addr;
+ u64 data;
+ u128 data128;
+
+ // Format:
+ // *wm00000000.w=0000
+ addr = sio_get32();
+ sio_getc(); // skip .
+ width = sio_getc();
+ sio_getc(); // skip =
+
+ switch (width) {
+ case 'b': data = sio_get8(); write8(addr, (u8)data); break;
+ case 'w': data = sio_get16(); write16(addr, (u16)data); break;
+ case 'l': data = sio_get32(); write32(addr, (u32)data); break;
+ case 'q': data = sio_get64(); write64(addr, data); break;
+ case 'p': data128 = sio_get128(); write128(addr, data128); break;
+ }
+}
+
+static void serialice_read_io(void)
+{
+ u8 width;
+ u16 port;
+
+ // Format:
+ // *ri0000.w
+ port = sio_get16();
+ sio_getc(); // skip .
+ width = sio_getc();
+
+ sio_putc('\r'); sio_putc('\n');
+
+ switch (width) {
+ case 'b': sio_put8(inb(port)); break;
+ case 'w': sio_put16(inw(port)); break;
+ case 'l': sio_put32(inl(port)); break;
+ }
+}
+
+static void serialice_write_io(void)
+{
+ u8 width;
+ u16 port;
+ u32 data;
+
+ // Format:
+ // *wi0000.w=0000
+ port = sio_get16();
+ sio_getc(); // skip .
+ width = sio_getc();
+ sio_getc(); // skip =
+
+ switch (width) {
+ case 'b': data = sio_get8(); outb((u8)data, port); break;
+ case 'w': data = sio_get16(); outw((u16)data, port); break;
+ case 'l': data = sio_get32(); outl((u32)data, port); break;
+ }
+}
+
+static inline msr_t serialice_rdmsr(u32 index, u32 key)
+{
+ msr_t result;
+ __asm__ __volatile__ (
+ "rdmsr"
+ : "=a" (result.lo), "=d" (result.hi)
+ : "c" (index), "D" (key)
+ );
+ return result;
+}
+
+static inline void serialice_wrmsr(u32 index, msr_t msr, u32 key)
+{
+ __asm__ __volatile__ (
+ "wrmsr"
+ : /* No outputs */
+ : "c" (index), "a" (msr.lo), "d" (msr.hi), "D" (key)
+ );
+}
+
+
+static void serialice_read_msr(void)
+{
+ u32 addr, key;
+ msr_t msr;
+
+ // Format:
+ // *rc00000000.9c5a203a
+ addr = sio_get32();
+ sio_getc(); // skip .
+ key = sio_get32(); // key in %edi
+
+ sio_putc('\r'); sio_putc('\n');
+
+ msr = serialice_rdmsr(addr, key);
+ sio_put32(msr.hi);
+ sio_putc('.');
+ sio_put32(msr.lo);
+}
+
+static void serialice_write_msr(void)
+{
+ u32 addr, key;
+ msr_t msr;
+
+ // Format:
+ // *wc00000000.9c5a203a=00000000.00000000
+ addr = sio_get32();
+ sio_getc(); // skip .
+ key = sio_get32(); // read key in %edi
+ sio_getc(); // skip =
+ msr.hi = sio_get32();
+ sio_getc(); // skip .
+ msr.lo = sio_get32();
+
+ serialice_wrmsr(addr, msr, key);
+}
+
+/* CPUID functions */
+
+static inline u32 cpuid_eax(u32 op, u32 op2)
+{
+ u32 eax;
+
+ __asm__("cpuid"
+ : "=a" (eax)
+ : "a" (op), "c" (op2)
+ : "ebx", "edx" );
+ return eax;
+}
+
+static inline u32 cpuid_ebx(u32 op, u32 op2)
+{
+ u32 ebx;
+
+ __asm__("cpuid"
+ : "=b" (ebx)
+ : "a" (op), "c" (op2)
+ : "edx");
+ return ebx;
+}
+
+static inline u32 cpuid_ecx(u32 op, u32 op2)
+{
+ u32 ecx;
+
+ __asm__("cpuid"
+ : "=c" (ecx)
+ : "a" (op), "c" (op2)
+ : "ebx", "edx" );
+ return ecx;
+}
+
+static inline u32 cpuid_edx(u32 op, u32 op2)
+{
+ u32 edx;
+
+ __asm__("cpuid"
+ : "=d" (edx)
+ : "a" (op), "c" (op2)
+ : "ebx");
+ return edx;
+}
+
+static void serialice_cpuinfo(void)
+{
+ u32 eax, ecx;
+ u32 reg32;
+
+ // Format:
+ // --EAX--- --ECX---
+ // *ci00000000.00000000
+ eax = sio_get32();
+ sio_getc(); // skip .
+ ecx = sio_get32();
+
+ sio_putc('\r'); sio_putc('\n');
+
+ /* This code looks quite crappy but this way we don't
+ * have to worry about running out of registers if we
+ * occupy eax, ebx, ecx, edx at the same time
+ */
+ reg32 = cpuid_eax(eax, ecx);
+ sio_put32(reg32);
+ sio_putc('.');
+
+ reg32 = cpuid_ebx(eax, ecx);
+ sio_put32(reg32);
+ sio_putc('.');
+
+ reg32 = cpuid_ecx(eax, ecx);
+ sio_put32(reg32);
+ sio_putc('.');
+
+ reg32 = cpuid_edx(eax, ecx);
+ sio_put32(reg32);
+}
+
+static void serialice_mainboard(void)
+{
+ sio_putc('\r'); sio_putc('\n');
+
+ /* must be defined in mainboard/<boardname>.c */
+ sio_putstring("Lenovo X201");
+}
+
+static void serialice_version(void)
+{
+ sio_putstring("\nSerialICE vphcoder (" __DATE__ ")\n");
+}
+
+static void s3_checksum (void)
+{
+ int i, j;
+ u32 s;
+ u32 b = 0;
+
+ printk (BIOS_ERR, "S3 test\n") ;
+
+ for (i = 0; i < 2048; i++)
+ {
+ s = 0;
+ for (j = ((i == 72) ? 0x800 : 0); j < (i ? 0x100000 : 0xa0000); j += 4)
+ {
+ u32 v = *(u32 *) ((i << 20) | j);
+ if (v != ((i << 20) | j) && i >= 1)
+ b++;
+ s += v;
+ }
+ if (((u8 *)(72 << 20))[i] != s % 255)
+ {
+ printk (BIOS_ERR, "MiB %d corrupted %x vs %x\n", i,
+ ((u8 *)(72 << 20))[i], s % 255);
+ }
+ }
+
+ printk (BIOS_ERR, "S3 test end, bad=%x\n", b);
+}
+
+
+static void serialice (void)
+{
+ serialice_version();
+
+ while(1) {
+ u16 c;
+ sio_putstring("\n> ");
+
+ c = sio_getc();
+ if (c != '*')
+ continue;
+
+ c = sio_getc() << 8;
+ c |= sio_getc();
+
+ switch(c) {
+ case (('r' << 8)|'a'):
+ {
+ u32 addr, len;
+ sio_getc(); // skip .
+ addr = sio_get32();
+ sio_getc(); // skip .
+ len = sio_get32 ();
+ ram_check (addr, len);
+ break;
+ }
+ case (('c' << 8)|'s'):
+ s3_checksum();
+ break;
+ case (('q' << 8)|'r'):
+ quick_ram_check();
+ break;
+ case (('q' << 8)|'s'):
+ return;
+ case (('r' << 8)|'m'): // Read Memory *rm
+ serialice_read_memory();
+ break;
+ case (('f' << 8)|'m'): // Flush Memory *fm
+ serialice_clflush();
+ break;
+ case (('w' << 8)|'m'): // Write Memory *wm
+ serialice_write_memory();
+ break;
+ case (('r' << 8)|'i'): // Read IO *ri
+ serialice_read_io();
+ break;
+ case (('w' << 8)|'i'): // Write IO *wi
+ serialice_write_io();
+ break;
+ case (('r' << 8)|'c'): // Read CPU MSR *rc
+ serialice_read_msr();
+ break;
+ case (('w' << 8)|'c'): // Write CPU MSR *wc
+ serialice_write_msr();
+ break;
+ case (('c' << 8)|'i'): // Read CPUID *ci
+ serialice_cpuinfo();
+ break;
+ case (('m' << 8)|'b'): // Read mainboard type *mb
+ serialice_mainboard();
+ break;
+ case (('v' << 8)|'i'): // Read version info *vi
+ serialice_version();
+ break;
+ case (('s' << 8)|'i'):
+ raminit (0);
+ break;
+ case (('s' << 8)|'3'):
+ raminit (1);
+ break;
+ case (('s' << 8)|'f'):
+ raminit (2);
+ break;
+ default:
+ sio_putstring("ERROR\n");
+ break;
+ }
+ }
+}
+#endif
+
+#if CONFIG_COLLECT_TIMESTAMPS
+tsc_t before_spd CAR_GLOBAL, after_spd CAR_GLOBAL, before_training CAR_GLOBAL, after_training CAR_GLOBAL;
+#endif
+
+void main(unsigned long bist)
+{
+ u32 reg32;
+ int s3resume = 0;
+#if CONFIG_COLLECT_TIMESTAMPS
+ tsc_t start_romstage_time;
+ tsc_t before_dram_time;
+ tsc_t after_dram_time;
+ tsc_t base_time = rdtsc ();
+#endif
+
+#if CONFIG_COLLECT_TIMESTAMPS
+ start_romstage_time = base_time;
+#endif
+
+ if (bist == 0)
+ enable_lapic();
+
+ /* Force PCIRST# */
+ pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
+ pci_write_config16(PCI_DEV(0, 0, 0), BCTRL, SBR);
+ udelay(200 * 1000);
+ pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0);
+ pci_write_config16(PCI_DEV(0, 0, 0), BCTRL, 0);
+
+ /* Enable USB Power. */
+ ec_set_bit(0x3b, 4);
+
+ pch_enable_lpc();
+
+ /* Enable GPIOs */
+ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
+ pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
+
+ inw (DEFAULT_GPIOBASE | 0x38); // = 0x10
+ outl (0x7963a5ff, DEFAULT_GPIOBASE);
+ outl (0xffffffff, DEFAULT_GPIOBASE | 0xc);
+ outl (0x87bf6aff, DEFAULT_GPIOBASE | 0x4);
+ outl (0x0, DEFAULT_GPIOBASE | 0x18);
+ outl (0x120c6, DEFAULT_GPIOBASE | 0x2c);
+ outl (0x27706fe, DEFAULT_GPIOBASE | 0x30);
+ outl (0x29fffff, DEFAULT_GPIOBASE | 0x38);
+ outl (0x1b01f9f4, DEFAULT_GPIOBASE | 0x34);
+ outl (0x0, DEFAULT_GPIOBASE | 0x40);
+ outl (0x0, DEFAULT_GPIOBASE | 0x48);
+ outl (0xf00, DEFAULT_GPIOBASE | 0x44);
+ outl (0x41000000, DEFAULT_GPIOBASE | 0x60);
+
+ calpella_early_initialization(CALPELLA_MOBILE);
+
+ /* This should probably go away. Until now it is required
+ * and mainboard specific
+ */
+ rcba_config();
+
+ console_init();
+
+#ifdef SERIALICE
+ serialice ();
+#endif
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ /* Read PM1_CNT */
+ reg32 = inl(DEFAULT_PMBASE + 0x04);
+ printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
+ if (((reg32 >> 10) & 7) == 5) {
+ u8 reg8;
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
+ printk(BIOS_DEBUG, "a2: %02x\n", reg8);
+ if (!(reg8 & 0x20))
+ {
+ outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+ printk(BIOS_DEBUG, "Bad resume from S3 detected.\n");
+ }
+ else
+ {
+#if CONFIG_HAVE_ACPI_RESUME
+ printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+ s3resume = 1;
+#else
+ printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+#endif
+ }
+ }
+
+#ifndef SERIALICE
+#if CONFIG_COLLECT_TIMESTAMPS
+ before_dram_time = rdtsc ();
+#endif
+ raminit(s3resume);
+#if CONFIG_COLLECT_TIMESTAMPS
+ after_dram_time = rdtsc ();
+#endif
+#endif
+
+ intel_early_me_status();
+
+ if (s3resume)
+ {
+ /* Clear SLP_TYPE. This will break stage2 but
+ * we care for that when we get there.
+ */
+ reg32 = inl(DEFAULT_PMBASE + 0x04);
+ outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+ }
+
+#if CONFIG_HAVE_ACPI_RESUME
+ /* Start address of high memory tables */
+ unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
+
+ /* If there is no high memory area, we didn't boot before, so
+ * this is not a resume. In that case we just create the cbmem toc.
+ */
+ if (s3resume && cbmem_reinit((u64)high_ram_base)) {
+ void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+#if 0
+ s3_checksum ();
+#endif
+ /* for (i = 0; i < 65536; i++)
+ if (read8 (i) != read8 (i + 0x100000))
+ printk (BIOS_ERR, "Corruption at %x: %x vs %x\n", i,
+ read8 (i), read8 (i + 0x100000));*/
+
+
+ /* copy 1MB - 64K to high tables ram_base to prevent memory corruption
+ * through stage 2. We could keep stuff like stack and heap in high tables
+ * memory completely, but that's a wonderful clean up task for another
+ * day.
+ */
+ if (resume_backup_memory)
+ memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
+#if 0
+ printk (BIOS_ERR, "move: %x, %x, %x\n",(unsigned)resume_backup_memory, (unsigned)CONFIG_RAMBASE, (unsigned)HIGH_MEMORY_SAVE);
+
+ s = 0;
+ for (j = 0; j < 0x100000; j += 4)
+ s += ((u32 *)resume_backup_memory)[j / 4];
+ if (((u8 *)(72 << 20))[1] != s % 255)
+ {
+ printk (BIOS_ERR, "MiB 1 (copy) corrupted %x vs %x\n",
+ ((u8 *)(72 << 20))[1], s % 255);
+ }
+ else
+ printk (BIOS_ERR, "MiB 1 (copy) ok %x == %x\n",
+ ((u8 *)(72 << 20))[1], s % 255);
+#endif
+ /* Magic for S3 resume */
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+ }
+ else if (s3resume) {
+ printk(BIOS_ERR, "Failed S3 resume.\n");
+ ram_check (0x100000, 0x200000);
+
+ /* Failed S3 resume, reset to come up cleanly */
+ outb(0xe, 0xcf9);
+ hlt();
+ } else {
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
+ quick_ram_check();
+ }
+#endif
+
+#if CONFIG_COLLECT_TIMESTAMPS
+ timestamp_init(base_time);
+ timestamp_add(TS_START_ROMSTAGE, start_romstage_time);
+ timestamp_add(TS_BEFORE_INITRAM, before_dram_time);
+ timestamp_add(101, before_spd);
+ timestamp_add(102, after_spd);
+ timestamp_add(103, before_training);
+ timestamp_add(104, after_training);
+ timestamp_add(TS_AFTER_INITRAM, after_dram_time);
+ timestamp_add_now(TS_END_ROMSTAGE);
+#endif
+
+#if CONFIG_CONSOLE_CBMEM
+ /* Keep this the last thing this function does. */
+ cbmemc_reinit();
+#endif
+}
diff --git a/src/mainboard/lenovo/x201/smi.h b/src/mainboard/lenovo/x201/smi.h
new file mode 100644
index 0000000..c5f48a1
--- /dev/null
+++ b/src/mainboard/lenovo/x201/smi.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens at stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef MAINBOARD_LENOVO_X60_SMI_H
+#define MAINBOARD_LENOVO_X60_SMI_H
+
+#define SMI_DOCK_CONNECT 0x01
+#define SMI_DOCK_DISCONNECT 0x02
+#define SMI_SAVE_CMOS 0x03
+
+#endif
diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c
new file mode 100644
index 0000000..5a7130f
--- /dev/null
+++ b/src/mainboard/lenovo/x201/smihandler.c
@@ -0,0 +1,207 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include "southbridge/intel/i82801gx/nvs.h"
+#include "southbridge/intel/i82801gx/i82801gx.h"
+#include <ec/acpi/ec.h>
+#include <pc80/mc146818rtc.h>
+#include <ec/lenovo/h8/h8.h>
+#include <delay.h>
+#include "dock.h"
+#include "smi.h"
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+static void mainboard_smm_init(void)
+{
+ printk(BIOS_DEBUG, "initializing SMI\n");
+ /* Enable 0x1600/0x1600 register pair */
+ ec_set_bit(0x00, 0x05);
+}
+
+static void mainboard_smi_save_cmos(void)
+{
+ u8 val;
+ u8 tmp70, tmp72;
+
+ tmp70 = inb(0x70);
+ tmp72 = inb(0x72);
+
+ val = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4);
+ set_option("tft_brightness", &val);
+ val = ec_read(H8_VOLUME_CONTROL);
+ set_option("volume", &val);
+
+ outb(tmp70, 0x70);
+ outb(tmp72, 0x72);
+}
+
+int mainboard_io_trap_handler(int smif)
+{
+ static int smm_initialized;
+
+ if (!smm_initialized) {
+ mainboard_smm_init();
+ smm_initialized = 1;
+ }
+
+ switch (smif) {
+ case SMI_DOCK_CONNECT:
+ ec_clr_bit(0x03, 2);
+ udelay(250000);
+ if (!dock_connect()) {
+ ec_set_bit(0x03, 2);
+ /* set dock LED to indicate status */
+ ec_write(0x0c, 0x09);
+ ec_write(0x0c, 0x88);
+ } else {
+ /* blink dock LED to indicate failure */
+ ec_write(0x0c, 0x08);
+ ec_write(0x0c, 0xc9);
+ }
+ break;
+
+ case SMI_DOCK_DISCONNECT:
+ ec_clr_bit(0x03, 2);
+ dock_disconnect();
+ break;
+
+ case SMI_SAVE_CMOS:
+ mainboard_smi_save_cmos();
+ break;
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 1
+ * On failure, the IO Trap Handler returns a value != 1 */
+ return 1;
+}
+
+static void mainboard_smi_brightness_up(void)
+{
+ u8 value;
+
+ if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0)
+ pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf);
+}
+
+static void mainboard_smi_brightness_down(void)
+{
+ u8 value;
+
+ if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10)
+ pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value - 0x10) & 0xf0);
+}
+
+static void mainboard_smi_handle_ec_sci(void)
+{
+ u8 status = inb(EC_SC);
+ u8 event;
+
+ if (!(status & EC_SCI_EVT))
+ return;
+
+ event = ec_query();
+ printk(BIOS_DEBUG, "EC event %02x\n", event);
+
+ switch(event) {
+ /* brightness up */
+ case 0x14:
+ mainboard_smi_brightness_up();
+ mainboard_smi_save_cmos();
+ break;
+ /* brightness down */
+ case 0x15:
+ mainboard_smi_brightness_down();
+ mainboard_smi_save_cmos();
+ break;
+ /* Fn-F9 key */
+ case 0x18:
+ /* Power loss */
+ case 0x27:
+ /* Undock Key */
+ case 0x50:
+ mainboard_io_trap_handler(SMI_DOCK_DISCONNECT);
+ break;
+ /* Dock Event */
+ case 0x37:
+ case 0x58:
+ mainboard_io_trap_handler(SMI_DOCK_CONNECT);
+ break;
+ default:
+ break;
+ }
+}
+
+void mainboard_smi_gpi(u16 gpi)
+{
+ if (gpi & (1 << 12))
+ mainboard_smi_handle_ec_sci();
+}
+
+int mainboard_smi_apmc(u8 data)
+{
+ u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+ u8 tmp;
+
+ printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data);
+
+ if (!pmbase)
+ return 0;
+
+ switch(data) {
+ case APM_CNT_ACPI_ENABLE:
+ /* use 0x1600/0x1604 to prevent races with userspace */
+ ec_set_ports(0x1604, 0x1600);
+ /* route H8SCI to SCI */
+ outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN);
+ tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
+ tmp &= ~0x03;
+ tmp |= 0x02;
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+ /* discard all events, and enable attention */
+ ec_write(0x80, 0x01);
+ break;
+ case APM_CNT_ACPI_DISABLE:
+ /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
+ provide a EC query function */
+ ec_set_ports(0x66, 0x62);
+ /* route H8SCI# to SMI */
+ outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN);
+ tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
+ tmp &= ~0x03;
+ tmp |= 0x01;
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
+ /* discard all events, and enable attention */
+ ec_write(0x80, 0x01);
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
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